diff mbox series

[v4,1/1] driver: watchdog: get platform clock from dt file

Message ID 20200406075952.525-1-rayagonda.kokatanur@broadcom.com
State Accepted
Commit 19a159f94ac1532ec12cf14a96c9daf172ade988
Delegated to: Stefan Roese
Headers show
Series [v4,1/1] driver: watchdog: get platform clock from dt file | expand

Commit Message

Rayagonda Kokatanur April 6, 2020, 7:59 a.m. UTC 
Get the watchdog platform clock from the DTS file
using clk subsystem and use the same for calculating
ticks in msec.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
---
Changes from v3:
 -Address review comments from Stefan Roese,
  Don't return error if clk_get_by_index() fails
  becasue all platform may not have clock support.

Changes from v2:
 -Address review comments from Stefan Roese,
  Use clk subsystem to get the base frequency of device instead
  of dt parameter "clk_mhz".

Changes from v1:
 -Address review comments from Stefan Roese,
  Remove default timeout reading in probe() as it is read in include/wdt.h.
  Add paranthesis on multi-line statements.

 drivers/watchdog/sp805_wdt.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

Comments

Stefan Roese April 7, 2020, 5:37 a.m. UTC | #1 
On 06.04.20 09:59, Rayagonda Kokatanur wrote:
> Get the watchdog platform clock from the DTS file
> using clk subsystem and use the same for calculating
> ticks in msec.
> 
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>

Reviewed-by: Stefan Roese <sr@denx.de>

But I still would like to see a comment or best "tested-by" tag from
seom NXP folks, using this driver.

Thanks,
Stefan

> ---
> Changes from v3:
>   -Address review comments from Stefan Roese,
>    Don't return error if clk_get_by_index() fails
>    becasue all platform may not have clock support.
> 
> Changes from v2:
>   -Address review comments from Stefan Roese,
>    Use clk subsystem to get the base frequency of device instead
>    of dt parameter "clk_mhz".
> 
> Changes from v1:
>   -Address review comments from Stefan Roese,
>    Remove default timeout reading in probe() as it is read in include/wdt.h.
>    Add paranthesis on multi-line statements.
> 
>   drivers/watchdog/sp805_wdt.c | 15 +++++++++++++--
>   1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
> index ca3ccbe76c..65fd2384f1 100644
> --- a/drivers/watchdog/sp805_wdt.c
> +++ b/drivers/watchdog/sp805_wdt.c
> @@ -7,6 +7,7 @@
>   
>   #include <asm/io.h>
>   #include <common.h>
> +#include <clk.h>
>   #include <dm/device.h>
>   #include <dm/fdtaddr.h>
>   #include <dm/read.h>
> @@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
>   
>   struct sp805_wdt_priv {
>   	void __iomem *reg;
> +	unsigned long clk_rate;
>   };
>   
>   static int sp805_wdt_reset(struct udevice *dev)
> @@ -63,8 +65,13 @@ static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
>   	 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
>   	 * not overflow.
>   	 */
> -	load_value = (gd->bus_clk) /
> -		(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
> +	if (gd->bus_clk) {
> +		load_value = (gd->bus_clk) /
> +			(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
> +	} else {
> +		/* platform provide clk */
> +		load_value = (timeout / 2) * (priv->clk_rate / 1000);
> +	}
>   
>   	writel(UNLOCK, priv->reg + WDTLOCK);
>   	writel(load_value, priv->reg + WDTLOAD);
> @@ -105,11 +112,15 @@ static int sp805_wdt_probe(struct udevice *dev)
>   static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
>   {
>   	struct sp805_wdt_priv *priv = dev_get_priv(dev);
> +	struct clk clk;
>   
>   	priv->reg = (void __iomem *)dev_read_addr(dev);
>   	if (IS_ERR(priv->reg))
>   		return PTR_ERR(priv->reg);
>   
> +	if (!clk_get_by_index(dev, 0, &clk))
> +		priv->clk_rate = clk_get_rate(&clk);
> +
>   	return 0;
>   }
>   
> 


Viele Grüße,
Stefan
Stefan Roese April 15, 2020, 9:39 a.m. UTC | #2 
On 06.04.20 09:59, Rayagonda Kokatanur wrote:
> Get the watchdog platform clock from the DTS file
> using clk subsystem and use the same for calculating
> ticks in msec.
> 
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
> Changes from v3:
>   -Address review comments from Stefan Roese,
>    Don't return error if clk_get_by_index() fails
>    becasue all platform may not have clock support.
> 
> Changes from v2:
>   -Address review comments from Stefan Roese,
>    Use clk subsystem to get the base frequency of device instead
>    of dt parameter "clk_mhz".
> 
> Changes from v1:
>   -Address review comments from Stefan Roese,
>    Remove default timeout reading in probe() as it is read in include/wdt.h.
>    Add paranthesis on multi-line statements.
> 
>   drivers/watchdog/sp805_wdt.c | 15 +++++++++++++--
>   1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
> index ca3ccbe76c..65fd2384f1 100644
> --- a/drivers/watchdog/sp805_wdt.c
> +++ b/drivers/watchdog/sp805_wdt.c
> @@ -7,6 +7,7 @@
>   
>   #include <asm/io.h>
>   #include <common.h>
> +#include <clk.h>
>   #include <dm/device.h>
>   #include <dm/fdtaddr.h>
>   #include <dm/read.h>
> @@ -34,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
>   
>   struct sp805_wdt_priv {
>   	void __iomem *reg;
> +	unsigned long clk_rate;
>   };
>   
>   static int sp805_wdt_reset(struct udevice *dev)
> @@ -63,8 +65,13 @@ static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
>   	 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
>   	 * not overflow.
>   	 */
> -	load_value = (gd->bus_clk) /
> -		(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
> +	if (gd->bus_clk) {
> +		load_value = (gd->bus_clk) /
> +			(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
> +	} else {
> +		/* platform provide clk */
> +		load_value = (timeout / 2) * (priv->clk_rate / 1000);
> +	}
>   
>   	writel(UNLOCK, priv->reg + WDTLOCK);
>   	writel(load_value, priv->reg + WDTLOAD);
> @@ -105,11 +112,15 @@ static int sp805_wdt_probe(struct udevice *dev)
>   static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
>   {
>   	struct sp805_wdt_priv *priv = dev_get_priv(dev);
> +	struct clk clk;
>   
>   	priv->reg = (void __iomem *)dev_read_addr(dev);
>   	if (IS_ERR(priv->reg))
>   		return PTR_ERR(priv->reg);
>   
> +	if (!clk_get_by_index(dev, 0, &clk))
> +		priv->clk_rate = clk_get_rate(&clk);
> +
>   	return 0;
>   }
>   
> 


Viele Grüße,
Stefan
diff mbox series

Patch

diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index ca3ccbe76c..65fd2384f1 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -7,6 +7,7 @@ 
 
 #include <asm/io.h>
 #include <common.h>
+#include <clk.h>
 #include <dm/device.h>
 #include <dm/fdtaddr.h>
 #include <dm/read.h>
@@ -34,6 +35,7 @@  DECLARE_GLOBAL_DATA_PTR;
 
 struct sp805_wdt_priv {
 	void __iomem *reg;
+	unsigned long clk_rate;
 };
 
 static int sp805_wdt_reset(struct udevice *dev)
@@ -63,8 +65,13 @@  static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
 	 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
 	 * not overflow.
 	 */
-	load_value = (gd->bus_clk) /
-		(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
+	if (gd->bus_clk) {
+		load_value = (gd->bus_clk) /
+			(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
+	} else {
+		/* platform provide clk */
+		load_value = (timeout / 2) * (priv->clk_rate / 1000);
+	}
 
 	writel(UNLOCK, priv->reg + WDTLOCK);
 	writel(load_value, priv->reg + WDTLOAD);
@@ -105,11 +112,15 @@  static int sp805_wdt_probe(struct udevice *dev)
 static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
 {
 	struct sp805_wdt_priv *priv = dev_get_priv(dev);
+	struct clk clk;
 
 	priv->reg = (void __iomem *)dev_read_addr(dev);
 	if (IS_ERR(priv->reg))
 		return PTR_ERR(priv->reg);
 
+	if (!clk_get_by_index(dev, 0, &clk))
+		priv->clk_rate = clk_get_rate(&clk);
+
 	return 0;
 }