| Message ID | 20200317180454.22393-1-grygorii.strashko@ti.com |
|---|---|
| State | Accepted |
| Delegated to: | David Miller |
| Headers | show |
| Series | net: phy: dp83867: w/a for fld detect threshold bootstrapping issue | expand |
From: Grygorii Strashko <grygorii.strashko@ti.com> Date: Tue, 17 Mar 2020 20:04:54 +0200 > When the DP83867 PHY is strapped to enable Fast Link Drop (FLD) feature > STRAP_STS2.STRAP_ FLD (reg 0x006F bit 10), the Energy Lost Threshold for > FLD Energy Lost Mode FLD_THR_CFG.ENERGY_LOST_FLD_THR (reg 0x002e bits 2:0) > will be defaulted to 0x2. This may cause the phy link to be unstable. The > new DP83867 DM recommends to always restore ENERGY_LOST_FLD_THR to 0x1. > > Hence, restore default value of FLD_THR_CFG.ENERGY_LOST_FLD_THR to 0x1 when > FLD is enabled by bootstrapping as recommended by DM. > > Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Applied, thank you. Let me know if I should queue this up for -stable.
On 22/03/2020 05:10, David Miller wrote: > From: Grygorii Strashko <grygorii.strashko@ti.com> > Date: Tue, 17 Mar 2020 20:04:54 +0200 > >> When the DP83867 PHY is strapped to enable Fast Link Drop (FLD) feature >> STRAP_STS2.STRAP_ FLD (reg 0x006F bit 10), the Energy Lost Threshold for >> FLD Energy Lost Mode FLD_THR_CFG.ENERGY_LOST_FLD_THR (reg 0x002e bits 2:0) >> will be defaulted to 0x2. This may cause the phy link to be unstable. The >> new DP83867 DM recommends to always restore ENERGY_LOST_FLD_THR to 0x1. >> >> Hence, restore default value of FLD_THR_CFG.ENERGY_LOST_FLD_THR to 0x1 when >> FLD is enabled by bootstrapping as recommended by DM. >> >> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> > > Applied, thank you. > Thank you. > Let me know if I should queue this up for -stable. > yes, please, as there are real link instability issues were observed without this change.
From: Grygorii Strashko <grygorii.strashko@ti.com> Date: Mon, 23 Mar 2020 22:36:32 +0200 > On 22/03/2020 05:10, David Miller wrote: >> Let me know if I should queue this up for -stable. >> > > yes, please, as there are real link instability issues were observed > without this change. Ok, done.
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 13f7f2d5a2ea..b55e3c0403ed 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -30,7 +30,8 @@ #define DP83867_CTRL 0x1f /* Extended Registers */ -#define DP83867_CFG4 0x0031 +#define DP83867_FLD_THR_CFG 0x002e +#define DP83867_CFG4 0x0031 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) @@ -93,6 +94,7 @@ #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) +#define DP83867_STRAP_STS2_STRAP_FLD BIT(10) /* PHY CTRL bits */ #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 @@ -145,6 +147,9 @@ /* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) +/* FLD_THR_CFG */ +#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7 + enum { DP83867_PORT_MIRROING_KEEP, DP83867_PORT_MIRROING_EN, @@ -622,6 +627,20 @@ static int dp83867_config_init(struct phy_device *phydev) phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, BIT(7)); + bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); + if (bs & DP83867_STRAP_STS2_STRAP_FLD) { + /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will + * be set to 0x2. This may causes the PHY link to be unstable - + * the default value 0x1 need to be restored. + */ + ret = phy_modify_mmd(phydev, DP83867_DEVADDR, + DP83867_FLD_THR_CFG, + DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK, + 0x1); + if (ret) + return ret; + } + if (phy_interface_is_rgmii(phydev) || phydev->interface == PHY_INTERFACE_MODE_SGMII) { val = phy_read(phydev, MII_DP83867_PHYCTRL);
When the DP83867 PHY is strapped to enable Fast Link Drop (FLD) feature STRAP_STS2.STRAP_ FLD (reg 0x006F bit 10), the Energy Lost Threshold for FLD Energy Lost Mode FLD_THR_CFG.ENERGY_LOST_FLD_THR (reg 0x002e bits 2:0) will be defaulted to 0x2. This may cause the phy link to be unstable. The new DP83867 DM recommends to always restore ENERGY_LOST_FLD_THR to 0x1. Hence, restore default value of FLD_THR_CFG.ENERGY_LOST_FLD_THR to 0x1 when FLD is enabled by bootstrapping as recommended by DM. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> --- drivers/net/phy/dp83867.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-)