@@ -99,6 +99,7 @@
#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
#define DP83867_PHYCR_RESERVED_MASK BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
@@ -627,7 +628,7 @@ static int dp83867_config_init(struct phy_device *phydev)
static int dp83867_phy_reset(struct phy_device *phydev)
{
- int err;
+ int val, err;
err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
if (err < 0)
@@ -635,6 +636,16 @@ static int dp83867_phy_reset(struct phy_device *phydev)
usleep_range(10, 20);
+ /* After reset FORCE_LINK_GOOD bit is set. Although the
+ * default value should be unset. Disable FORCE_LINK_GOOD
+ * for the phy to work properly.
+ */
+ val = phy_read(phydev, MII_DP83867_PHYCTRL);
+ if (val & DP83867_PHYCR_FORCE_LINK_GOOD) {
+ val &= ~(DP83867_PHYCR_FORCE_LINK_GOOD);
+ phy_write(phydev, MII_DP83867_PHYCTRL, val);
+ }
+
return 0;
}
According to the Datasheet this bit should be 0 (Normal operation) in default. With the FORCE_LINK_GOOD bit set, it is not possible to get a link. This patch sets FORCE_LINK_GOOD to the default value after resetting the phy. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- drivers/net/phy/dp83867.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)