| Message ID | 20191211170724.30768-1-fbarrat@linux.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | npu2-opencapi: don't fence on masked XSL errors | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch master (d75e82dbfbb9443efeb3f9a5921ac23605aab469) |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | success | Test snowpatch/job/snowpatch-skiboot on branch master |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco | success | Signed-off-by present |
Le 11/12/2019 à 18:07, Frederic Barrat a écrit : > An upcoming change in the initfile is going to modify the default > action and fence behavior of some of the NPU FIR2 bits. We're already > overriding the settings of most of those. The one exception is for > bits 41 and 42, which are XSL errors impacting 2 links that we > mask (instead we rely on the subsequent OTL error, which is per link). > > The new initfile will fence-on-error for bits 41 and 42. And even if > the FIRs are masked, the NPU logic could fence the links, which is not > what we want. So this patch makes sure we don't fence on the FIRs we > want to ignore. It has no effect on existing firmware. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- ping? > hw/npu2-opencapi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c > index ed6650f4..3b8b5976 100644 > --- a/hw/npu2-opencapi.c > +++ b/hw/npu2-opencapi.c > @@ -1681,6 +1681,7 @@ static int enable_interrupts(struct npu2 *p) > reg = npu2_scom_read(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, > NPU2_MISC_DA_LEN_8B); > reg |= xstop_override; > + reg &= ~(PPC_BIT(41) | PPC_BIT(42)); > npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, > NPU2_MISC_DA_LEN_8B, reg); > >
On 12/12/19 4:07 am, Frederic Barrat wrote: > An upcoming change in the initfile is going to modify the default > action and fence behavior of some of the NPU FIR2 bits. We're already > overriding the settings of most of those. The one exception is for > bits 41 and 42, which are XSL errors impacting 2 links that we > mask (instead we rely on the subsequent OTL error, which is per link). > > The new initfile will fence-on-error for bits 41 and 42. And even if > the FIRs are masked, the NPU logic could fence the links, which is not > what we want. So this patch makes sure we don't fence on the FIRs we > want to ignore. It has no effect on existing firmware. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> > --- > hw/npu2-opencapi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c > index ed6650f4..3b8b5976 100644 > --- a/hw/npu2-opencapi.c > +++ b/hw/npu2-opencapi.c > @@ -1681,6 +1681,7 @@ static int enable_interrupts(struct npu2 *p) > reg = npu2_scom_read(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, > NPU2_MISC_DA_LEN_8B); > reg |= xstop_override; > + reg &= ~(PPC_BIT(41) | PPC_BIT(42)); We do define macros for these bits which might be more explanatory. A comment might also be helpful... > npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, > NPU2_MISC_DA_LEN_8B, reg); > >
On 11/12/2019 18:07, Frederic Barrat wrote: > An upcoming change in the initfile is going to modify the default > action and fence behavior of some of the NPU FIR2 bits. We're already > overriding the settings of most of those. The one exception is for > bits 41 and 42, which are XSL errors impacting 2 links that we > mask (instead we rely on the subsequent OTL error, which is per link). > > The new initfile will fence-on-error for bits 41 and 42. And even if > the FIRs are masked, the NPU logic could fence the links, which is not > what we want. So this patch makes sure we don't fence on the FIRs we > want to ignore. It has no effect on existing firmware. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- > hw/npu2-opencapi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c > index ed6650f4..3b8b5976 100644 > --- a/hw/npu2-opencapi.c > +++ b/hw/npu2-opencapi.c > @@ -1681,6 +1681,7 @@ static int enable_interrupts(struct npu2 *p) > reg = npu2_scom_read(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, > NPU2_MISC_DA_LEN_8B); > reg |= xstop_override; > + reg &= ~(PPC_BIT(41) | PPC_BIT(42)); > npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, > NPU2_MISC_DA_LEN_8B, reg); > > Sounds good. Thanks Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Le 08/01/2020 à 01:05, Andrew Donnellan a écrit : > On 12/12/19 4:07 am, Frederic Barrat wrote: >> An upcoming change in the initfile is going to modify the default >> action and fence behavior of some of the NPU FIR2 bits. We're already >> overriding the settings of most of those. The one exception is for >> bits 41 and 42, which are XSL errors impacting 2 links that we >> mask (instead we rely on the subsequent OTL error, which is per link). >> >> The new initfile will fence-on-error for bits 41 and 42. And even if >> the FIRs are masked, the NPU logic could fence the links, which is not >> what we want. So this patch makes sure we don't fence on the FIRs we >> want to ignore. It has no effect on existing firmware. >> >> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > > Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> > >> --- >> hw/npu2-opencapi.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c >> index ed6650f4..3b8b5976 100644 >> --- a/hw/npu2-opencapi.c >> +++ b/hw/npu2-opencapi.c >> @@ -1681,6 +1681,7 @@ static int enable_interrupts(struct npu2 *p) >> reg = npu2_scom_read(p->chip_id, p->xscom_base, >> NPU2_MISC_FENCE_ENABLE2, >> NPU2_MISC_DA_LEN_8B); >> reg |= xstop_override; >> + reg &= ~(PPC_BIT(41) | PPC_BIT(42)); > > We do define macros for these bits which might be more explanatory. A > comment might also be helpful... Arg! I had never seen those! v2 on its way... >> npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, >> NPU2_MISC_DA_LEN_8B, reg); >> >
diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index ed6650f4..3b8b5976 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -1681,6 +1681,7 @@ static int enable_interrupts(struct npu2 *p) reg = npu2_scom_read(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, NPU2_MISC_DA_LEN_8B); reg |= xstop_override; + reg &= ~(PPC_BIT(41) | PPC_BIT(42)); npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, NPU2_MISC_DA_LEN_8B, reg);
An upcoming change in the initfile is going to modify the default action and fence behavior of some of the NPU FIR2 bits. We're already overriding the settings of most of those. The one exception is for bits 41 and 42, which are XSL errors impacting 2 links that we mask (instead we rely on the subsequent OTL error, which is per link). The new initfile will fence-on-error for bits 41 and 42. And even if the FIRs are masked, the NPU logic could fence the links, which is not what we want. So this patch makes sure we don't fence on the FIRs we want to ignore. It has no effect on existing firmware. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/npu2-opencapi.c | 1 + 1 file changed, 1 insertion(+)