mbox series

[v7,0/8] Add support for H6 PWM

Message ID 20191119175319.16561-1-peron.clem@gmail.com
Headers show
Series Add support for H6 PWM | expand

Message

Clément Péron Nov. 19, 2019, 5:53 p.m. UTC 
Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

I didn't add the acked-tags as there are big changes.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v7:
 - Fix indent in Yaml bindings

Changes in v6:
 - Update git commit log
 - Distinguish error message 

Changes in v5:
 - Move bypass calculation to pwm_calculate
 - Split mod_clock fallback from bus_clk probe    
 - Update comment
 - Move my SoB after acked-by/reviewed-by

Changes in v4:
 - item description in correct order and add a blank line
 - use %pe for printing PTR_ERR
 - don't print error when it's an EPROBE_DEFER
 - change output clock bypass formula to match PWM policy

Changes in v3:
 - Documentation update to allow one clock without name
 - Change reset optional to shared
 - If reset probe failed return an error
 - Remove old clock probe
 - Update bypass enabled formula

Changes in v2:
 - Remove allOf in Documentation
 - Add H6 example in Documentation
 - Change clock name from "pwm" to "mod"
 - Change reset quirk to optional probe
 - Change bus_clock quirk to optional probe
 - Add limitation comment about mod_clk_output
 - Add quirk for mod_clk_output
 - Change bypass formula

Clément Péron (2):
  pwm: sun4i: Prefer "mod" clock to unnamed
  [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM

Jernej Skrabec (6):
  dt-bindings: pwm: allwinner: Add H6 PWM description
  pwm: sun4i: Add an optional probe for reset line
  pwm: sun4i: Add an optional probe for bus clock
  pwm: sun4i: Add support to output source clock directly
  pwm: sun4i: Add support for H6 PWM
  arm64: dts: allwinner: h6: Add PWM node

 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  48 +++++
 .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |   4 +
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  10 +
 drivers/pwm/pwm-sun4i.c                       | 185 +++++++++++++++---
 4 files changed, 215 insertions(+), 32 deletions(-)

Comments

Maxime Ripard Nov. 21, 2019, 7:24 a.m. UTC | #1 
On Tue, Nov 19, 2019 at 06:53:11PM +0100, Clément Péron wrote:
> Hi,
>
> This is a rework of Jernej's previous work[1] taking account all the
> previous remarks.
>
> Bindings is still strict but probe in the driver are now optionnals.
>
> If someone could confirm that the PWM is not broken, as my board
> doesn't output it.
>
> I didn't add the acked-tags as there are big changes.

Applied 1 and 7 for 5.6, thanks!
Maxime
Uwe Kleine-König Nov. 21, 2019, 7:26 a.m. UTC | #2 
On Tue, Nov 19, 2019 at 06:53:14PM +0100, Clément Péron wrote:
> New device tree bindings called the source clock of the module
> "mod" when several clocks are defined.
> 
> Try to get a clock called "mod" if nothing is found try to get
> an unnamed clock.
> 
> Signed-off-by: Clément Péron <peron.clem@gmail.com>

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Thanks
Uwe
Uwe Kleine-König Nov. 21, 2019, 7:28 a.m. UTC | #3 
Hello Clément,

On Tue, Nov 19, 2019 at 06:53:15PM +0100, Clément Péron wrote:
> +	/*
> +	 * We're keeping the bus clock on for the sake of simplicity.
> +	 * Actually it only needs to be on for hardware register accesses.
> +	 */
> +	ret = clk_prepare_enable(pwm->bus_clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");

Maybe add the error code to the message?

Best regards
Uwe
Uwe Kleine-König Nov. 21, 2019, 7:36 a.m. UTC | #4 
Hello Clément,

On Tue, Nov 19, 2019 at 06:53:16PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> PWM core has an option to bypass whole logic and output unchanged source
> clock as PWM output. This is achieved by enabling bypass bit.
> 
> Note that when bypass is enabled, no other setting has any meaning, not
> even enable bit.
> 
> This mode of operation is needed to achieve high enough frequency to
> serve as clock source for AC200 chip which is integrated into same
> package as H6 SoC.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++-------------
>  1 file changed, 64 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index ce83d479ba0e..a1d8851b18f0 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -3,6 +3,10 @@
>   * Driver for Allwinner sun4i Pulse Width Modulation Controller
>   *
>   * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
> + *
> + * Limitations:
> + * - When outputing the source clock directly, the PWM logic will be bypassed
> + *   and the currently running period is not guaranteed to be completed
>   */
>  
>  #include <linux/bitops.h>
> @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
>  
>  struct sun4i_pwm_data {
>  	bool has_prescaler_bypass;
> +	bool has_direct_mod_clk_output;
>  	unsigned int npwm;
>  };
>  
> @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>  
>  	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>  
> +	/*
> +	 * PWM chapter in H6 manual has a diagram which explains that if bypass
> +	 * bit is set, no other setting has any meaning. Even more, experiment
> +	 * proved that also enable bit is ignored in this case.
> +	 */
> +	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> +	    sun4i_pwm->data->has_direct_mod_clk_output) {
> +		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> +		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
> +		state->polarity = PWM_POLARITY_NORMAL;
> +		state->enabled = true;
> +		return;
> +	}
> +
>  	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
>  	    sun4i_pwm->data->has_prescaler_bypass)
>  		prescaler = 1;
> @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>  
>  static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
>  			       const struct pwm_state *state,
> -			       u32 *dty, u32 *prd, unsigned int *prsclr)
> +			       u32 *dty, u32 *prd, unsigned int *prsclr,
> +			       bool *bypass)
>  {
>  	u64 clk_rate, div = 0;
>  	unsigned int pval, prescaler = 0;
>  
>  	clk_rate = clk_get_rate(sun4i_pwm->clk);
>  
> +	*bypass = state->enabled &&
> +		  (state->period * clk_rate >= NSEC_PER_SEC) &&
> +		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
> +		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
> +
> +	/* Skip calculation of other parameters if we bypass them */
> +	if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output)
> +		return 0;
> +

Hmm, so if my PWM doesn't support the bypass bit *bypass might still be
true on return of sun4i_pwm_calculate. It doesn't hurt because the value
is only used after another check of has_direct_mod_clk_output, but still
this is a bit confusing.

>  	if (sun4i_pwm->data->has_prescaler_bypass) {
>  		/* First, test without any prescaler when available */
>  		prescaler = PWM_PRESCAL_MASK;
> @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  {
>  	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
>  	struct pwm_state cstate;
> -	u32 ctrl;
> +	u32 ctrl, period, duty, val;
>  	int ret;
> -	unsigned int delay_us;
> +	unsigned int delay_us, prescaler;
>  	unsigned long now;
> +	bool bypass;
>  
>  	pwm_get_state(pwm, &cstate);
>  
> @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  	spin_lock(&sun4i_pwm->ctrl_lock);
>  	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>  
> -	if ((cstate.period != state->period) ||
> -	    (cstate.duty_cycle != state->duty_cycle)) {
> -		u32 period, duty, val;
> -		unsigned int prescaler;
> +	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
> +				  &bypass);
> +	if (ret) {
> +		dev_err(chip->dev, "period exceeds the maximum value\n");
> +		spin_unlock(&sun4i_pwm->ctrl_lock);
> +		if (!cstate.enabled)
> +			clk_disable_unprepare(sun4i_pwm->clk);
> +		return ret;
> +	}
>  
> -		ret = sun4i_pwm_calculate(sun4i_pwm, state,
> -					  &duty, &period, &prescaler);
> -		if (ret) {
> -			dev_err(chip->dev, "period exceeds the maximum value\n");
> -			spin_unlock(&sun4i_pwm->ctrl_lock);
> -			if (!cstate.enabled)
> -				clk_disable_unprepare(sun4i_pwm->clk);
> -			return ret;

This would be a bit easier to review if this commit was split into two
patches. One that drops the check for cstate.period != state->period etc
(which otherwise is nearly empty when ignoring whitespace changes), and
a second that then adds bypass support.


> +	if (sun4i_pwm->data->has_direct_mod_clk_output) {
> +		if (bypass) {
> +			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> +			/* We can skip apply of other parameters */
> +			goto bypass_mode;

I would prefer to use goto only for error handling. Not sure if there is
a nice way to do that.

> +		} else {
> +			ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
>  		}
> +	}

Best regards
Uwe
Clément Péron Nov. 21, 2019, 11:14 a.m. UTC | #5 
Hi Uwe,

On Thu, 21 Nov 2019 at 08:28, Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> Hello Clément,
>
> On Tue, Nov 19, 2019 at 06:53:15PM +0100, Clément Péron wrote:
> > +     /*
> > +      * We're keeping the bus clock on for the sake of simplicity.
> > +      * Actually it only needs to be on for hardware register accesses.
> > +      */
> > +     ret = clk_prepare_enable(pwm->bus_clk);
> > +     if (ret) {
> > +             dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
>
> Maybe add the error code to the message?

Ok I will change it for the reset control deassert if you agree.

Clement

>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-König            |
> Industrial Linux Solutions                 | https://www.pengutronix.de/ |
Clément Péron Nov. 21, 2019, 11:38 a.m. UTC | #6 
Hi Uwe,

On Thu, 21 Nov 2019 at 08:36, Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> Hello Clément,
>
> On Tue, Nov 19, 2019 at 06:53:16PM +0100, Clément Péron wrote:
> > From: Jernej Skrabec <jernej.skrabec@siol.net>
> >
> > PWM core has an option to bypass whole logic and output unchanged source
> > clock as PWM output. This is achieved by enabling bypass bit.
> >
> > Note that when bypass is enabled, no other setting has any meaning, not
> > even enable bit.
> >
> > This mode of operation is needed to achieve high enough frequency to
> > serve as clock source for AC200 chip which is integrated into same
> > package as H6 SoC.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++-------------
> >  1 file changed, 64 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index ce83d479ba0e..a1d8851b18f0 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> > @@ -3,6 +3,10 @@
> >   * Driver for Allwinner sun4i Pulse Width Modulation Controller
> >   *
> >   * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
> > + *
> > + * Limitations:
> > + * - When outputing the source clock directly, the PWM logic will be bypassed
> > + *   and the currently running period is not guaranteed to be completed
> >   */
> >
> >  #include <linux/bitops.h>
> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
> >
> >  struct sun4i_pwm_data {
> >       bool has_prescaler_bypass;
> > +     bool has_direct_mod_clk_output;
> >       unsigned int npwm;
> >  };
> >
> > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> >       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > +     /*
> > +      * PWM chapter in H6 manual has a diagram which explains that if bypass
> > +      * bit is set, no other setting has any meaning. Even more, experiment
> > +      * proved that also enable bit is ignored in this case.
> > +      */
> > +     if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> > +         sun4i_pwm->data->has_direct_mod_clk_output) {
> > +             state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> > +             state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
> > +             state->polarity = PWM_POLARITY_NORMAL;
> > +             state->enabled = true;
> > +             return;
> > +     }
> > +
> >       if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
> >           sun4i_pwm->data->has_prescaler_bypass)
> >               prescaler = 1;
> > @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> >  static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
> >                              const struct pwm_state *state,
> > -                            u32 *dty, u32 *prd, unsigned int *prsclr)
> > +                            u32 *dty, u32 *prd, unsigned int *prsclr,
> > +                            bool *bypass)
> >  {
> >       u64 clk_rate, div = 0;
> >       unsigned int pval, prescaler = 0;
> >
> >       clk_rate = clk_get_rate(sun4i_pwm->clk);
> >
> > +     *bypass = state->enabled &&
> > +               (state->period * clk_rate >= NSEC_PER_SEC) &&
> > +               (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
> > +               (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
> > +
> > +     /* Skip calculation of other parameters if we bypass them */
> > +     if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output)
> > +             return 0;
> > +
>
> Hmm, so if my PWM doesn't support the bypass bit *bypass might still be
> true on return of sun4i_pwm_calculate. It doesn't hurt because the value
> is only used after another check of has_direct_mod_clk_output, but still
> this is a bit confusing.

Ok will change this

>
> >       if (sun4i_pwm->data->has_prescaler_bypass) {
> >               /* First, test without any prescaler when available */
> >               prescaler = PWM_PRESCAL_MASK;
> > @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> >  {
> >       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
> >       struct pwm_state cstate;
> > -     u32 ctrl;
> > +     u32 ctrl, period, duty, val;
> >       int ret;
> > -     unsigned int delay_us;
> > +     unsigned int delay_us, prescaler;
> >       unsigned long now;
> > +     bool bypass;
> >
> >       pwm_get_state(pwm, &cstate);
> >
> > @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> >       spin_lock(&sun4i_pwm->ctrl_lock);
> >       ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > -     if ((cstate.period != state->period) ||
> > -         (cstate.duty_cycle != state->duty_cycle)) {
> > -             u32 period, duty, val;
> > -             unsigned int prescaler;n write the register and return
But
> > +     ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
> > +                               &bypass);
> > +     if (ret) {
> > +             dev_err(chip->dev, "period exceeds the maximum value\n");
> > +             spin_unlock(&sun4i_pwm->ctrl_lock);
> > +             if (!cstate.enabled)
> > +                     clk_disable_unprepare(sun4i_pwm->clk);
> > +             return ret;
> > +     }
> >
> > -             ret = sun4i_pwm_calculate(sun4i_pwm, state,
> > -                                       &duty, &period, &prescaler);
> > -             if (ret) {
> > -                     dev_err(chip->dev, "period exceeds the maximum value\n");
> > -                     spin_unlock(&sun4i_pwm->ctrl_lock);
> > -                     if (!cstate.enabled)
> > -                             clk_disable_unprepare(sun4i_pwm->clk);
> > -                     return ret;
>
> This would be a bit easier to review if this commit was split into two
> patches. One that drops the check for cstate.period != state->period etc
> (which otherwise is nearly empty when ignoring whitespace changes), and
> a second that then adds bypass support.

Ok

>
>
> > +     if (sun4i_pwm->data->has_direct_mod_clk_output) {
> > +             if (bypass) {
> > +                     ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> > +                     /* We can skip apply of other parameters */
> > +                     goto bypass_mode;
>
> I would prefer to use goto only for error handling. Not sure if there is
> a nice way to do that.

As the PWM is necessarily enabled we can write the register and return
but not sure it's more proper.

sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
spin_unlock(&sun4i_pwm->ctrl_lock);
return 0;

Regards,
Clément

>
> > +             } else {
> > +                     ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
> >               }
> > +     }
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-König            |
> Industrial Linux Solutions                 | https://www.pengutronix.de/ |
Rob Herring Dec. 10, 2019, 4:48 p.m. UTC | #7 
On Thu, Nov 21, 2019 at 1:24 AM Maxime Ripard <maxime@cerno.tech> wrote:
>
> On Tue, Nov 19, 2019 at 06:53:11PM +0100, Clément Péron wrote:
> > Hi,
> >
> > This is a rework of Jernej's previous work[1] taking account all the
> > previous remarks.
> >
> > Bindings is still strict but probe in the driver are now optionnals.
> >
> > If someone could confirm that the PWM is not broken, as my board
> > doesn't output it.
> >
> > I didn't add the acked-tags as there are big changes.
>
> Applied 1 and 7 for 5.6, thanks!

I believe patch 7 breaks linux-next:

Error: Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dts:35.37-38
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dt.yaml]
Error 1

Usually that's due to a missing include.

Rob
Clément Péron Dec. 10, 2019, 5:20 p.m. UTC | #8 
Hi Rob,

On Tue, 10 Dec 2019 at 17:48, Rob Herring <robh+dt@kernel.org> wrote:
>
> On Thu, Nov 21, 2019 at 1:24 AM Maxime Ripard <maxime@cerno.tech> wrote:
> >
> > On Tue, Nov 19, 2019 at 06:53:11PM +0100, Clément Péron wrote:
> > > Hi,
> > >
> > > This is a rework of Jernej's previous work[1] taking account all the
> > > previous remarks.
> > >
> > > Bindings is still strict but probe in the driver are now optionnals.
> > >
> > > If someone could confirm that the PWM is not broken, as my board
> > > doesn't output it.
> > >
> > > I didn't add the acked-tags as there are big changes.
> >
> > Applied 1 and 7 for 5.6, thanks!
>
> I believe patch 7 breaks linux-next:

Sorry for that,

>
> Error: Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dts:35.37-38
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dt.yaml]
> Error 1
>
> Usually that's due to a missing include.
Indeed include are missing.

I will send a patch ASAP with a fixes tag.

Thanks for the report,
Clément

>
> Rob