| Message ID | 20191108092824.9773-1-rnayak@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add device tree support for sc7180 | expand |
On 2019-11-08 10:37, Rajendra Nayak wrote: > Remove the sdm845 SoC specific compatible to make the driver > easily reusable across other SoC's with the same IP block. > This will reduce further churn adding any SoC specific > compatibles unless really needed. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Lina Iyer <ilina@codeaurora.org> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > Cc: Marc Zyngier <maz@kernel.org> > --- > drivers/irqchip/qcom-pdc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c > index faa7d61b9d6c..c175333bb646 100644 > --- a/drivers/irqchip/qcom-pdc.c > +++ b/drivers/irqchip/qcom-pdc.c > @@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node > *node, struct device_node *parent) > return ret; > } > > -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); > +IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); Acked-by: Marc Zyngier <marc.zyngier@arm.com> How do you want me get this (and the DT change) merged? I can either take these two patches in the irqchip tree, or you arrange them to be taken by the platform maintainers. Your call. Thanks, M.
On 2019-11-08 10:50, Marc Zyngier wrote: > On 2019-11-08 10:37, Rajendra Nayak wrote: >> Remove the sdm845 SoC specific compatible to make the driver >> easily reusable across other SoC's with the same IP block. >> This will reduce further churn adding any SoC specific >> compatibles unless really needed. >> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> Reviewed-by: Lina Iyer <ilina@codeaurora.org> >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> Cc: Marc Zyngier <maz@kernel.org> >> --- >> drivers/irqchip/qcom-pdc.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c >> index faa7d61b9d6c..c175333bb646 100644 >> --- a/drivers/irqchip/qcom-pdc.c >> +++ b/drivers/irqchip/qcom-pdc.c >> @@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node >> *node, struct device_node *parent) >> return ret; >> } >> >> -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); >> +IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); > > Acked-by: Marc Zyngier <marc.zyngier@arm.com> I need to have my hands fixed. The real tag is: Acked-by: Marc Zyngier <maz@kernel.org> One day, I'll manage that... M.
On 11/8/2019 3:10 PM, Marc Zyngier wrote: > On 2019-11-08 10:37, Rajendra Nayak wrote: >> Remove the sdm845 SoC specific compatible to make the driver >> easily reusable across other SoC's with the same IP block. >> This will reduce further churn adding any SoC specific >> compatibles unless really needed. >> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> Reviewed-by: Lina Iyer <ilina@codeaurora.org> >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> Cc: Marc Zyngier <maz@kernel.org> >> --- >> drivers/irqchip/qcom-pdc.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c >> index faa7d61b9d6c..c175333bb646 100644 >> --- a/drivers/irqchip/qcom-pdc.c >> +++ b/drivers/irqchip/qcom-pdc.c >> @@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node >> *node, struct device_node *parent) >> return ret; >> } >> >> -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); >> +IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); > > Acked-by: Marc Zyngier <marc.zyngier@arm.com> > > How do you want me get this (and the DT change) merged? I can either take > these two patches in the irqchip tree, or you arrange them to be taken > by the platform maintainers. Your call. I think it makes sense for you to take these two via your tree (The driver and binding doc updates) and the DT node addition for pdc to go via Andy/Bjorn. Andy/Bjorn, does that sound fine?
Quoting Rajendra Nayak (2019-11-08 01:28:13) > Add skeletal sc7180 SoC dtsi and idp board dts files. > > Co-developed-by: Taniya Das <tdas@codeaurora.org> > Signed-off-by: Taniya Das <tdas@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-08 01:28:22) > From: Kiran Gunda <kgunda@codeaurora.org> > > Add the rpmh regulators for the sc7180 idp platform. This platform > consists of PMIC PM6150 and PM6150l > > Signed-off-by: Kiran Gunda <kgunda@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
On Fri 08 Nov 01:55 PST 2019, Rajendra Nayak wrote: > > On 11/8/2019 3:10 PM, Marc Zyngier wrote: > > On 2019-11-08 10:37, Rajendra Nayak wrote: > > > Remove the sdm845 SoC specific compatible to make the driver > > > easily reusable across other SoC's with the same IP block. > > > This will reduce further churn adding any SoC specific > > > compatibles unless really needed. > > > > > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > > > Reviewed-by: Lina Iyer <ilina@codeaurora.org> > > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > > Cc: Marc Zyngier <maz@kernel.org> > > > --- > > > drivers/irqchip/qcom-pdc.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c > > > index faa7d61b9d6c..c175333bb646 100644 > > > --- a/drivers/irqchip/qcom-pdc.c > > > +++ b/drivers/irqchip/qcom-pdc.c > > > @@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node > > > *node, struct device_node *parent) > > > return ret; > > > } > > > > > > -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); > > > +IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); > > > > Acked-by: Marc Zyngier <marc.zyngier@arm.com> > > > > How do you want me get this (and the DT change) merged? I can either take > > these two patches in the irqchip tree, or you arrange them to be taken > > by the platform maintainers. Your call. > > I think it makes sense for you to take these two via your tree (The driver > and binding doc updates) and the DT node addition for pdc to go via Andy/Bjorn. > Andy/Bjorn, does that sound fine? > Yes, that sounds good. Regards, Bjorn
On 2019-11-11 08:19, Bjorn Andersson wrote: > On Fri 08 Nov 01:55 PST 2019, Rajendra Nayak wrote: > >> >> On 11/8/2019 3:10 PM, Marc Zyngier wrote: >> > On 2019-11-08 10:37, Rajendra Nayak wrote: >> > > Remove the sdm845 SoC specific compatible to make the driver >> > > easily reusable across other SoC's with the same IP block. >> > > This will reduce further churn adding any SoC specific >> > > compatibles unless really needed. >> > > >> > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> > > Reviewed-by: Lina Iyer <ilina@codeaurora.org> >> > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> > > Cc: Marc Zyngier <maz@kernel.org> >> > > --- >> > > drivers/irqchip/qcom-pdc.c | 2 +- >> > > 1 file changed, 1 insertion(+), 1 deletion(-) >> > > >> > > diff --git a/drivers/irqchip/qcom-pdc.c >> b/drivers/irqchip/qcom-pdc.c >> > > index faa7d61b9d6c..c175333bb646 100644 >> > > --- a/drivers/irqchip/qcom-pdc.c >> > > +++ b/drivers/irqchip/qcom-pdc.c >> > > @@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node >> > > *node, struct device_node *parent) >> > > return ret; >> > > } >> > > >> > > -IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); >> > > +IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); >> > >> > Acked-by: Marc Zyngier <marc.zyngier@arm.com> >> > >> > How do you want me get this (and the DT change) merged? I can >> either take >> > these two patches in the irqchip tree, or you arrange them to be >> taken >> > by the platform maintainers. Your call. >> >> I think it makes sense for you to take these two via your tree (The >> driver >> and binding doc updates) and the DT node addition for pdc to go via >> Andy/Bjorn. >> Andy/Bjorn, does that sound fine? >> > > Yes, that sounds good. Applied to irqchip/next M.
Hi, On Fri, Nov 8, 2019 at 5:29 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: > > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QUP SE instances configuration for sc7180. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > --- > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ > arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ > 2 files changed, 821 insertions(+) Comments below could be done in a follow-up patch if it makes more sense. > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index e1d6278d85f7..666e9b92c7ad 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi At the top of this file, please add aliases for all i2c and spi devices (like sdm845 did). Right now trying to use command line i2c tools is super confusing because busses are super jumbled. > + i2c2: i2c@888000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00888000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c2_default>; > + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi2? > + i2c4: i2c@890000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00890000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c4_default>; > + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi4? > + i2c7: i2c@a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a84000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c7_default>; > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi7? > + i2c9: i2c@a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a8c000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c9_default>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; Where is spi9? > + qup_spi1_default: qup-spi1-default { > + pinmux { > + pins = "gpio0", "gpio1", > + "gpio2", "gpio3", > + "gpio12", "gpio94"; Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this. > + qup_spi6_default: qup-spi6-default { > + pinmux { > + pins = "gpio59", "gpio60", > + "gpio61", "gpio62", > + "gpio68", "gpio72"; Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this. > + qup_spi10_default: qup-spi10-default { > + pinmux { > + pins = "gpio86", "gpio87", > + "gpio88", "gpio89", > + "gpio90", "gpio91"; Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this. -Doug
On 12/6/2019 5:55 PM, Doug Anderson wrote: > Hi, > > On Fri, Nov 8, 2019 at 5:29 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: >> >> From: Roja Rani Yarubandi <rojay@codeaurora.org> >> >> Add QUP SE instances configuration for sc7180. >> >> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> --- >> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ >> arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ >> 2 files changed, 821 insertions(+) > > Comments below could be done in a follow-up patch if it makes more sense. > > >> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> index e1d6278d85f7..666e9b92c7ad 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > At the top of this file, please add aliases for all i2c and spi > devices (like sdm845 did). Right now trying to use command line i2c > tools is super confusing because busses are super jumbled. sure, I'll add it. > > >> + i2c2: i2c@888000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00888000 0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c2_default>; >> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; > > Where is spi2? > > >> + i2c4: i2c@890000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00890000 0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c4_default>; >> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; > > Where is spi4? > > >> + i2c7: i2c@a84000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a84000 0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c7_default>; >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; > > Where is spi7? > > >> + i2c9: i2c@a8c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a8c000 0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c9_default>; >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; > > Where is spi9? so looks like these qup instances (qup2/4/7/9) can only be configured to be used as i2c or uart and not spi since we have only 2 pins for them and spi needs 4. > >> + qup_spi1_default: qup-spi1-default { >> + pinmux { >> + pins = "gpio0", "gpio1", >> + "gpio2", "gpio3", >> + "gpio12", "gpio94"; > > Please just mux one of the chip selects by default. It seems like it > would be _much_ more common to have a single SPI device on the bus and > then every board doesn't have to override this. > > >> + qup_spi6_default: qup-spi6-default { >> + pinmux { >> + pins = "gpio59", "gpio60", >> + "gpio61", "gpio62", >> + "gpio68", "gpio72"; > > Please just mux one of the chip selects by default. It seems like it > would be _much_ more common to have a single SPI device on the bus and > then every board doesn't have to override this. > > >> + qup_spi10_default: qup-spi10-default { >> + pinmux { >> + pins = "gpio86", "gpio87", >> + "gpio88", "gpio89", >> + "gpio90", "gpio91"; > > Please just mux one of the chip selects by default. It seems like it > would be _much_ more common to have a single SPI device on the bus and > then every board doesn't have to override this. yes, i will fix all of them to remove the additional chip select muxes.
Hi, On Tue, Dec 10, 2019 at 2:33 AM Rajendra Nayak <rnayak@codeaurora.org> wrote: > > On 12/6/2019 5:55 PM, Doug Anderson wrote: > > Hi, > > > > On Fri, Nov 8, 2019 at 5:29 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: > >> > >> From: Roja Rani Yarubandi <rojay@codeaurora.org> > >> > >> Add QUP SE instances configuration for sc7180. > >> > >> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> > >> --- > >> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ > >> arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ > >> 2 files changed, 821 insertions(+) > > > > Comments below could be done in a follow-up patch if it makes more sense. Just to note: looks like your patch is now landed in the Qualcomm maintainer tree, so I'll look for the fixes in a follow-up patch. :-) -Doug