| Message ID | CAMZc-bxqUDNb_ggRSPCy5jVi-CUoXbo7mtrFp5vQWc4Eix_8+w@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | Fix unrecognizable insn of pr92865 | expand |
On Tue, Dec 10, 2019 at 01:47:50PM +0800, Hongtao Liu wrote: > This patch is to enable integer mask cmp/cmov under AVX512F even > with TARGET_XOP . > Bootstrap and regression test on i386/x86_64 backend is ok. > > Changelog: > PR target/92865 > * gcc/config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable > integer mask cmov when available even with TARGET_XOP. > * gcc/testsuite/gcc.target/i386/pr92865-1.c: New test. No gcc/ or gcc/testsuite/ prefixes in ChangeLog. > --- a/gcc/config/i386/i386-expand.c > +++ b/gcc/config/i386/i386-expand.c > @@ -3428,7 +3428,7 @@ static bool > ix86_valid_mask_cmp_mode (machine_mode mode) > { > /* XOP has its own vector conditional movement. */ > - if (TARGET_XOP) > + if (TARGET_XOP && !TARGET_AVX512F) > return false; > > /* AVX512F is needed for mask operation. */ We don't know what will AMD CPUs with AVX512* do or what will be optimal for them, there aren't any yet. I guess this is fine for now, so would be your previous && GET_MODE_SIZE (mode) == 16. Jakub
> No gcc/ or gcc/testsuite/ prefixes in ChangeLog.
And 2 different ChangeLogs: ChangeLog and testsuite/ChangeLog.
On Tue, Dec 10, 2019 at 4:11 PM Jakub Jelinek <jakub@redhat.com> wrote: > > On Tue, Dec 10, 2019 at 01:47:50PM +0800, Hongtao Liu wrote: > > This patch is to enable integer mask cmp/cmov under AVX512F even > > with TARGET_XOP . > > Bootstrap and regression test on i386/x86_64 backend is ok. > > > > Changelog: > > PR target/92865 > > * gcc/config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable > > integer mask cmov when available even with TARGET_XOP. > > * gcc/testsuite/gcc.target/i386/pr92865-1.c: New test. > > No gcc/ or gcc/testsuite/ prefixes in ChangeLog. > > > --- a/gcc/config/i386/i386-expand.c > > +++ b/gcc/config/i386/i386-expand.c > > @@ -3428,7 +3428,7 @@ static bool > > ix86_valid_mask_cmp_mode (machine_mode mode) > > { > > /* XOP has its own vector conditional movement. */ > > - if (TARGET_XOP) > > + if (TARGET_XOP && !TARGET_AVX512F) > > return false; > > > > /* AVX512F is needed for mask operation. */ > > We don't know what will AMD CPUs with AVX512* do or what will be optimal for Yes, I'll make it tunable for different processors in another separated patch or in this one? > them, there aren't any yet. I guess this is fine for now, so would be your > previous && GET_MODE_SIZE (mode) == 16. > > Jakub > Updated patch with Changelog ---------------- Changelog gcc/ PR target/92865 * config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable integer mask cmov when available even with TARGET_XOP. gcc/testsuite * gcc/testsuite/gcc.target/i386/pr92865-1.c: New test. ----------------
On Wed, Dec 11, 2019 at 09:55:24AM +0800, Hongtao Liu wrote: > Changelog > gcc/ > PR target/92865 > * config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable > integer mask cmov when available even with TARGET_XOP. > > gcc/testsuite > * gcc/testsuite/gcc.target/i386/pr92865-1.c: New test. Please remove gcc/testsuite/ here too. Ok with that change. Jakub
On Wed, Dec 11, 2019 at 3:54 PM Jakub Jelinek <jakub@redhat.com> wrote: > > On Wed, Dec 11, 2019 at 09:55:24AM +0800, Hongtao Liu wrote: > > Changelog > > gcc/ > > PR target/92865 > > * config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable > > integer mask cmov when available even with TARGET_XOP. > > > > gcc/testsuite > > * gcc/testsuite/gcc.target/i386/pr92865-1.c: New test. > > Please remove gcc/testsuite/ here too. > Ok with that change. Yes, thanks. > > Jakub >
From 2c53eb1ddf876a616c7ee914256e3a27f30cd158 Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Tue, 10 Dec 2019 09:44:18 +0800
Subject: [PATCH] Fix unrecognizable insn of pr92865.
PR target/92865
* gcc/config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable
integer mask cmov when available even with TARGET_XOP.
* gcc/testsuite/gcc.target/i386/pr92865-1.c: New test.
---
gcc/config/i386/i386-expand.c | 2 +-
gcc/testsuite/gcc.target/i386/pr92865-1.c | 67 +++++++++++++++++++++++
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr92865-1.c
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index ff3c24cc5b7..cbf4eb7b487 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -3428,7 +3428,7 @@ static bool
ix86_valid_mask_cmp_mode (machine_mode mode)
{
/* XOP has its own vector conditional movement. */
- if (TARGET_XOP)
+ if (TARGET_XOP && !TARGET_AVX512F)
return false;
/* AVX512F is needed for mask operation. */
diff --git a/gcc/testsuite/gcc.target/i386/pr92865-1.c b/gcc/testsuite/gcc.target/i386/pr92865-1.c
new file mode 100644
index 00000000000..49b5778a067
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr92865-1.c
@@ -0,0 +1,67 @@
+/* PR target/92865 */
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mavx512f -mavx512bw -mxop" } */
+/* { dg-final { scan-assembler-times "vpcmp\[bwdq\]\[\t ]" 4 } } */
+/* { dg-final { scan-assembler-times "vpcmpu\[bwdq\]\[\t ]" 4 } } */
+/* { dg-final { scan-assembler-times "vmovdq\[au\]8\[\t ]" 4 } } */
+/* { dg-final { scan-assembler-times "vmovdq\[au\]16\[\t ]" 4 } } *
+/* { dg-final { scan-assembler-times "vmovdq\[au\]32\[\t ]" 4 } } */
+/* { dg-final { scan-assembler-times "vmovdq\[au\]64\[\t ]" 4 } } */
+
+extern char arraysb[64];
+extern short arraysw[32];
+extern int arraysd[16];
+extern long long arraysq[8];
+
+extern unsigned char arrayub[64];
+extern unsigned short arrayuw[32];
+extern unsigned int arrayud[16];
+extern unsigned long long arrayuq[8];
+
+int f1(char a)
+{
+ for (int i = 0; i < 64; i++)
+ arraysb[i] = arraysb[i] >= a;
+}
+
+int f2(short a)
+{
+ for (int i = 0; i < 32; i++)
+ arraysw[i] = arraysw[i] >= a;
+}
+
+int f3(int a)
+{
+ for (int i = 0; i < 16; i++)
+ arraysd[i] = arraysd[i] >= a;
+}
+
+int f4(long long a)
+{
+ for (int i = 0; i < 8; i++)
+ arraysq[i] = arraysq[i] >= a;
+}
+
+int f5(unsigned char a)
+{
+ for (int i = 0; i < 64; i++)
+ arrayub[i] = arrayub[i] >= a;
+}
+
+int f6(unsigned short a)
+{
+ for (int i = 0; i < 32; i++)
+ arrayuw[i] = arrayuw[i] >= a;
+}
+
+int f7(unsigned int a)
+{
+ for (int i = 0; i < 16; i++)
+ arrayud[i] = arrayud[i] >= a;
+}
+
+int f8(unsigned long long a)
+{
+ for (int i = 0; i < 8; i++)
+ arrayuq[i] = arrayuq[i] >= a;
+}
--
2.18.1
Hi jakub: This patch is to enable integer mask cmp/cmov under AVX512F even with TARGET_XOP . Bootstrap and regression test on i386/x86_64 backend is ok. Changelog: PR target/92865 * gcc/config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable integer mask cmov when available even with TARGET_XOP. * gcc/testsuite/gcc.target/i386/pr92865-1.c: New test.