| Message ID | 20191120082318.3909-5-yangbo.lu@nxp.com |
|---|---|
| State | Accepted |
| Delegated to: | David Miller |
| Headers | show |
| Series | Support PTP clock and hardware timestamping for DSA Felix driver | expand |
> +static const u32 vsc9959_ptp_regmap[] = { > + REG(PTP_PIN_CFG, 0x000000), > + REG(PTP_PIN_TOD_SEC_MSB, 0x000004), > + REG(PTP_PIN_TOD_SEC_LSB, 0x000008), > + REG(PTP_PIN_TOD_NSEC, 0x00000c), > + REG(PTP_CFG_MISC, 0x0000a0), > + REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), > + REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), > +}; > + > + [PTP] = { > + .start = 0x0090000, > + .end = 0x00900cb, > + .name = "ptp", > + }, Seems like an odd end value. Is the last word used for something else? Also, the last regmap register you defined is 0xa8. So could end actually be 900ab? Andrew
Hi Andrew, > -----Original Message----- > From: Andrew Lunn <andrew@lunn.ch> > Sent: Thursday, November 21, 2019 10:49 AM > To: Y.b. Lu <yangbo.lu@nxp.com> > Cc: netdev@vger.kernel.org; Alexandre Belloni > <alexandre.belloni@bootlin.com>; Microchip Linux Driver Support > <UNGLinuxDriver@microchip.com>; David S . Miller <davem@davemloft.net>; > Vladimir Oltean <vladimir.oltean@nxp.com>; Claudiu Manoil > <claudiu.manoil@nxp.com>; Vivien Didelot <vivien.didelot@gmail.com>; > Florian Fainelli <f.fainelli@gmail.com>; Richard Cochran > <richardcochran@gmail.com> > Subject: Re: [PATCH 4/5] net: dsa: ocelot: define PTP registers for > felix_vsc9959 > > > +static const u32 vsc9959_ptp_regmap[] = { > > + REG(PTP_PIN_CFG, 0x000000), > > + REG(PTP_PIN_TOD_SEC_MSB, 0x000004), > > + REG(PTP_PIN_TOD_SEC_LSB, 0x000008), > > + REG(PTP_PIN_TOD_NSEC, 0x00000c), > > + REG(PTP_CFG_MISC, 0x0000a0), > > + REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), > > + REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), > > +}; > > + > > > + [PTP] = { > > + .start = 0x0090000, > > + .end = 0x00900cb, > > + .name = "ptp", > > + }, > > Seems like an odd end value. Is the last word used for something else? > > Also, the last regmap register you defined is 0xa8. So could end actually be > 900ab? [Y.b. Lu] The PTP registers range is from 0x0090000 to 0x00900cb according to reference manual. The patch has only defined the registers which ocelot driver is using now, not all registers in vsc9959_ptp_regmap. In the future, as new features will be added, I think more registers will be added to use. Thanks. > > Andrew
On 11/20/2019 12:23 AM, Yangbo Lu wrote: > This patch is to define PTP registers for felix_vsc9959. > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index d67bd14..b9758b0 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -282,6 +282,16 @@ static const u32 vsc9959_sys_regmap[] = { REG_RESERVED(SYS_CM_DATA), }; +static const u32 vsc9959_ptp_regmap[] = { + REG(PTP_PIN_CFG, 0x000000), + REG(PTP_PIN_TOD_SEC_MSB, 0x000004), + REG(PTP_PIN_TOD_SEC_LSB, 0x000008), + REG(PTP_PIN_TOD_NSEC, 0x00000c), + REG(PTP_CFG_MISC, 0x0000a0), + REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), + REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), +}; + static const u32 vsc9959_gcb_regmap[] = { REG(GCB_SOFT_RST, 0x000004), }; @@ -293,6 +303,7 @@ static const u32 *vsc9959_regmap[] = { [REW] = vsc9959_rew_regmap, [SYS] = vsc9959_sys_regmap, [S2] = vsc9959_s2_regmap, + [PTP] = vsc9959_ptp_regmap, [GCB] = vsc9959_gcb_regmap, }; @@ -330,6 +341,11 @@ static struct resource vsc9959_target_io_res[] = { .end = 0x00603ff, .name = "s2", }, + [PTP] = { + .start = 0x0090000, + .end = 0x00900cb, + .name = "ptp", + }, [GCB] = { .start = 0x0070000, .end = 0x00701ff,
This patch is to define PTP registers for felix_vsc9959. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- drivers/net/dsa/ocelot/felix_vsc9959.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)