| Message ID | 20191029210821.1954-8-suneelglinux@gmail.com |
|---|---|
| State | RFC |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | arm: Introduce Marvell/Cavium OcteonTX | expand |
Hi Suneel, On Tue, 29 Oct 2019 at 14:08, Suneel Garapati <suneelglinux@gmail.com> wrote: > > From: Suneel Garapati <sgarapati@marvell.com> > > If Enhanced Allocation capability is present in bridges, use it > to read the fixed sub-ordinate bus number. > > Signed-off-by: Suneel Garapati <sgarapati@marvell.com> > --- > drivers/pci/pci-uclass.c | 25 +++++++++++++++++++------ > 1 file changed, 19 insertions(+), 6 deletions(-) > Reviewed-by: Simon Glass <sjg@chromium.org> > diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c > index f17e83565c..51f7135723 100644 > --- a/drivers/pci/pci-uclass.c > +++ b/drivers/pci/pci-uclass.c > @@ -599,10 +599,20 @@ int dm_pci_hose_probe_bus(struct udevice *bus) > { > int sub_bus; > int ret; > + int ea_pos; > + u8 reg; > > debug("%s\n", __func__); > > - sub_bus = pci_get_bus_max() + 1; > + ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA); > + > + if (ea_pos) { > + dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8), > + ®); > + sub_bus = reg; > + } else { > + sub_bus = pci_get_bus_max() + 1; > + } > debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); > dm_pciauto_prescan_setup_bridge(bus, sub_bus); > > @@ -612,12 +622,15 @@ int dm_pci_hose_probe_bus(struct udevice *bus) > ret); > return ret; > } > - if (sub_bus != bus->seq) { > - printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", > - __func__, bus->name, bus->seq, sub_bus); > - return -EPIPE; > + > + if (!ea_pos) { > + if (sub_bus != bus->seq) { > + printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", > + __func__, bus->name, bus->seq, sub_bus); Can we change to debug() - for code size? > + return -EPIPE; > + } > + sub_bus = pci_get_bus_max(); > } > - sub_bus = pci_get_bus_max(); > dm_pciauto_postscan_setup_bridge(bus, sub_bus); > > return sub_bus; > -- > 2.23.0 > Regards, Simon
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f17e83565c..51f7135723 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -599,10 +599,20 @@ int dm_pci_hose_probe_bus(struct udevice *bus) { int sub_bus; int ret; + int ea_pos; + u8 reg; debug("%s\n", __func__); - sub_bus = pci_get_bus_max() + 1; + ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA); + + if (ea_pos) { + dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8), + ®); + sub_bus = reg; + } else { + sub_bus = pci_get_bus_max() + 1; + } debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); dm_pciauto_prescan_setup_bridge(bus, sub_bus); @@ -612,12 +622,15 @@ int dm_pci_hose_probe_bus(struct udevice *bus) ret); return ret; } - if (sub_bus != bus->seq) { - printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", - __func__, bus->name, bus->seq, sub_bus); - return -EPIPE; + + if (!ea_pos) { + if (sub_bus != bus->seq) { + printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", + __func__, bus->name, bus->seq, sub_bus); + return -EPIPE; + } + sub_bus = pci_get_bus_max(); } - sub_bus = pci_get_bus_max(); dm_pciauto_postscan_setup_bridge(bus, sub_bus); return sub_bus;