| Message ID | 20191029210821.1954-17-suneelglinux@gmail.com |
|---|---|
| State | RFC |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | arm: Introduce Marvell/Cavium OcteonTX | expand |
On Tue, 29 Oct 2019 at 14:08, Suneel Garapati <suneelglinux@gmail.com> wrote: > > From: Suneel Garapati <sgarapati@marvell.com> > > For platforms that support 64bit physical address, fill upper 32bit > of buffer address in scatter-gather descriptor. This is needed for > platforms with more than 4GB DRAM. > > Signed-off-by: Suneel Garapati <sgarapati@marvell.com> > --- > drivers/ata/ahci.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c > index ca075b58bc..5f929700c0 100644 > --- a/drivers/ata/ahci.c > +++ b/drivers/ata/ahci.c > @@ -506,6 +506,11 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, > ahci_sg->addr = > cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); > ahci_sg->addr_hi = 0; > +#ifdef CONFIG_PHYS_64BIT > + ahci_sg->addr_hi = > + cpu_to_le32((u32)(((u64)(buf + i * MAX_DATA_BYTE_COUNT) > + >> 16) >> 16)); How about something like: ulong addr = (ulong)buf + i * MAX_DATA_BYTE_COUNT; ahci_sg->addr = cpu_to_le32(addr); ahci_sg->addr_hi = 0; #ifdef CONFIG_PHYS_64BIT ahci_sg->addr_hi = addr >> 32ULL; #endif Regards, Simon
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index ca075b58bc..5f929700c0 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -506,6 +506,11 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, ahci_sg->addr = cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; +#ifdef CONFIG_PHYS_64BIT + ahci_sg->addr_hi = + cpu_to_le32((u32)(((u64)(buf + i * MAX_DATA_BYTE_COUNT) + >> 16) >> 16)); +#endif ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < MAX_DATA_BYTE_COUNT ? (buf_len - 1)