Message ID | 20191112112839.10960-4-yangbo.lu@nxp.com |
---|---|
State | Accepted |
Commit | d3eb317ea50ef763a5a1ef5ff4e2bc19498542d1 |
Delegated to: | Peng Fan |
Headers | show |
Series | Drop redundant code for eSDHC clock getting | expand |
>-----Original Message----- >From: Yangbo Lu <yangbo.lu@nxp.com> >Sent: Tuesday, November 12, 2019 4:59 PM >To: u-boot@lists.denx.de >Cc: Peng Fan <peng.fan@nxp.com>; Feng Li <feng.li_2@nxp.com>; Alison >Wang <alison.wang@nxp.com>; Sumit Garg <sumit.garg@nxp.com>; Priyanka >Jain <priyanka.jain@nxp.com>; Mario Six <mario.six@gdsys.cc>; Y.b. Lu ><yangbo.lu@nxp.com> >Subject: [PATCH 3/4] arm: drop eSDHC clock getting in mxc_get_clock() for >layerscape > >Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, >eSDHC clock getting do not have to use it. It uses global data >gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more >than one eSDHC controllers on SoC, they use same reference clock. > >Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> >--- > arch/arm/cpu/armv7/ls102xa/clock.c | 2 -- > arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 15 --------------- >arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 15 --------------- > arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 -- > arch/arm/include/asm/arch-ls102xa/clock.h | 1 - > 5 files changed, 35 deletions(-) > >diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c >b/arch/arm/cpu/armv7/ls102xa/clock.c >index 30c7b37..7a1053c 100644 >--- a/arch/arm/cpu/armv7/ls102xa/clock.c >+++ b/arch/arm/cpu/armv7/ls102xa/clock.c >@@ -109,8 +109,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) > switch (clk) { > case MXC_I2C_CLK: > return get_bus_freq(0) / 2; >- case MXC_ESDHC_CLK: >- return get_bus_freq(0); > case MXC_DSPI_CLK: > return get_bus_freq(0) / 2; > case MXC_UART_CLK: >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c >b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c >index df4df9a..6d82cfe 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c >+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c >@@ -227,16 +227,6 @@ ulong get_ddr_freq(ulong dummy) > return gd->mem_clk; > } > >-#ifdef CONFIG_FSL_ESDHC >-int get_sdhc_freq(ulong dummy) >-{ >- if (!gd->arch.sdhc_clk) >- get_clocks(); >- >- return gd->arch.sdhc_clk; >-} >-#endif >- > int get_serial_clock(void) > { > return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ - >264,11 +254,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) > switch (clk) { > case MXC_I2C_CLK: > return get_i2c_freq(0); >-#if defined(CONFIG_FSL_ESDHC) >- case MXC_ESDHC_CLK: >- case MXC_ESDHC2_CLK: >- return get_sdhc_freq(0); >-#endif > case MXC_DSPI_CLK: > return get_dspi_freq(0); > #ifdef CONFIG_FSL_LPUART >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >index b3e6732..1f8289d 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c >@@ -236,16 +236,6 @@ int get_dspi_freq(ulong dummy) > return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } > >-#ifdef CONFIG_FSL_ESDHC >-int get_sdhc_freq(ulong dummy) >-{ >- if (!gd->arch.sdhc_clk) >- get_clocks(); >- >- return gd->arch.sdhc_clk; >-} >-#endif >- > int get_serial_clock(void) > { > return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ - >256,11 +246,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) > switch (clk) { > case MXC_I2C_CLK: > return get_i2c_freq(0); >-#if defined(CONFIG_FSL_ESDHC) >- case MXC_ESDHC_CLK: >- case MXC_ESDHC2_CLK: >- return get_sdhc_freq(0); >-#endif > case MXC_DSPI_CLK: > return get_dspi_freq(0); > default: >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h >b/arch/arm/include/asm/arch-fsl-layerscape/clock.h >index b37a08d..95d6156 100644 >--- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h >+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h >@@ -14,8 +14,6 @@ enum mxc_clock { > MXC_ARM_CLK = 0, > MXC_BUS_CLK, > MXC_UART_CLK, >- MXC_ESDHC_CLK, >- MXC_ESDHC2_CLK, > MXC_I2C_CLK, > MXC_DSPI_CLK, > }; >diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h >b/arch/arm/include/asm/arch-ls102xa/clock.h >index bf67df5..e66e57f 100644 >--- a/arch/arm/include/asm/arch-ls102xa/clock.h >+++ b/arch/arm/include/asm/arch-ls102xa/clock.h >@@ -12,7 +12,6 @@ > enum mxc_clock { > MXC_ARM_CLK = 0, > MXC_UART_CLK, >- MXC_ESDHC_CLK, > MXC_I2C_CLK, > MXC_DSPI_CLK, > }; >-- >2.7.4 Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 30c7b37..7a1053c 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -109,8 +109,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_bus_freq(0) / 2; - case MXC_ESDHC_CLK: - return get_bus_freq(0); case MXC_DSPI_CLK: return get_bus_freq(0) / 2; case MXC_UART_CLK: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index df4df9a..6d82cfe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -227,16 +227,6 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; } -#ifdef CONFIG_FSL_ESDHC -int get_sdhc_freq(ulong dummy) -{ - if (!gd->arch.sdhc_clk) - get_clocks(); - - return gd->arch.sdhc_clk; -} -#endif - int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -264,11 +254,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); -#if defined(CONFIG_FSL_ESDHC) - case MXC_ESDHC_CLK: - case MXC_ESDHC2_CLK: - return get_sdhc_freq(0); -#endif case MXC_DSPI_CLK: return get_dspi_freq(0); #ifdef CONFIG_FSL_LPUART diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index b3e6732..1f8289d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -236,16 +236,6 @@ int get_dspi_freq(ulong dummy) return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } -#ifdef CONFIG_FSL_ESDHC -int get_sdhc_freq(ulong dummy) -{ - if (!gd->arch.sdhc_clk) - get_clocks(); - - return gd->arch.sdhc_clk; -} -#endif - int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -256,11 +246,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); -#if defined(CONFIG_FSL_ESDHC) - case MXC_ESDHC_CLK: - case MXC_ESDHC2_CLK: - return get_sdhc_freq(0); -#endif case MXC_DSPI_CLK: return get_dspi_freq(0); default: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index b37a08d..95d6156 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -14,8 +14,6 @@ enum mxc_clock { MXC_ARM_CLK = 0, MXC_BUS_CLK, MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h index bf67df5..e66e57f 100644 --- a/arch/arm/include/asm/arch-ls102xa/clock.h +++ b/arch/arm/include/asm/arch-ls102xa/clock.h @@ -12,7 +12,6 @@ enum mxc_clock { MXC_ARM_CLK = 0, MXC_UART_CLK, - MXC_ESDHC_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, };
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- arch/arm/cpu/armv7/ls102xa/clock.c | 2 -- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 15 --------------- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 15 --------------- arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 -- arch/arm/include/asm/arch-ls102xa/clock.h | 1 - 5 files changed, 35 deletions(-)