Message ID | 20191108084517.21617-1-peron.clem@gmail.com |
---|---|
Headers | show |
Series | Add support for H6 PWM | expand |
On Fri, Nov 08, 2019 at 09:45:12AM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > H6 PWM core needs deasserted reset line in order to work. > > Add an optional probe for it. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Thanks Uwe
On Fri, Nov 08, 2019 at 09:45:13AM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > H6 PWM core needs bus clock to be enabled in order to work. > > Add an optional probe for it and a fallback for previous > bindings without name on module clock. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 48 +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 46 insertions(+), 2 deletions(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index 2b9a2a78591f..a10022d6c0fd 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -78,6 +78,7 @@ struct sun4i_pwm_data { > > struct sun4i_pwm_chip { > struct pwm_chip chip; > + struct clk *bus_clk; > struct clk *clk; > struct reset_control *rst; > void __iomem *base; > @@ -363,9 +364,38 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > if (IS_ERR(pwm->base)) > return PTR_ERR(pwm->base); > > - pwm->clk = devm_clk_get(&pdev->dev, NULL); > - if (IS_ERR(pwm->clk)) > + /* Get all clocks and reset line */ > + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); > + if (IS_ERR(pwm->clk)) { > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > + dev_err(&pdev->dev, "get clock failed %pe\n", > + pwm->clk); > return PTR_ERR(pwm->clk); > + } > + > + /* > + * Fallback for old dtbs with a single clock and no name. > + * If a parent has a clock-name called "mod" whereas the > + * current node is unnamed the clock reference will be > + * incorrectly obtained and will not go into this fallback. For me "old dtbs" suggests that today a device tree should have a "mod" clock. Is this true also for machines other than H6? And I'd put the comment before the acquisition of the "mod" clock. Something like: /* * A clock called "mod" is only required on H6 (for now) and on * other SoCs we expect an unnamed clock. So we request "mod" * first (and ignore the corner case that a parent provides a * "mod" clock) and if this is not found we fall back to the * first clock of the PWM. */ > + */ > + if (!pwm->clk) { > + pwm->clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(pwm->clk)) { > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > + dev_err(&pdev->dev, "get clock failed %pe\n", > + pwm->clk); > + return PTR_ERR(pwm->clk); > + } > + } > + > + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); > + if (IS_ERR(pwm->bus_clk)) { > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > + dev_err(&pdev->dev, "get bus_clock failed %pe\n", > + pwm->bus_clk); > + return PTR_ERR(pwm->bus_clk); > + } > > pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > if (IS_ERR(pwm->rst)) { > @@ -382,6 +412,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > return ret; > } > > + /* > + * We're keeping the bus clock on for the sake of simplicity. > + * Actually it only needs to be on for hardware register > + * accesses. > + */ > + ret = clk_prepare_enable(pwm->bus_clk); > + if (ret) { > + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); > + goto err_bus; > + } > + Would it make sense to split this patch into "Prefer "mod" clock to (unnamed) clock" and "Introduce optional bus clock"? Best regards Uwe
On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. > > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. > > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip which is integrated into same > package as H6 SoC. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index a10022d6c0fd..9cc928ab47bc 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be bypassed > + * and the currently running period is not guaranteed to be completed > */ > > #include <linux/bitops.h> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + sun4i_pwm->data->has_direct_mod_clk_output) { > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); I first thought you're losing precision here by reusing state->period here, but with a divisor of 2 everything is fine. > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = true; > + return; > + } > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler = 1; > @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > u32 ctrl; > + bool bypass = false; > int ret; > unsigned int delay_us; > unsigned long now; > @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > } > } > > + /* > + * Although it would make much more sense to check for bypass in > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". I don't understand this reasoning. sun4i_pwm_calculate knows about .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just add a bool *bypass as parameter and move the logic there? > + */ > + if (state->enabled) { > + u32 clk_rate = clk_get_rate(sun4i_pwm->clk); > + bypass = (state->period * clk_rate >= NSEC_PER_SEC) && > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); > + } > + This looks right now. Best regards Uwe
On Fri, Nov 08, 2019 at 09:45:15AM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > Now that sun4i PWM driver supports deasserting reset line and enabling > bus clock, support for H6 PWM can be added. > > Note that while H6 PWM has two channels, only first one is wired to > output pin. Second channel is used as a clock source to companion AC200 > chip which is bundled into same package. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Very minor nitpick: The order here is wrong, your S-o-b should be the last thing here. Best regards Uwe
Hi Uwe, On Wed, 13 Nov 2019 at 09:35, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > On Fri, Nov 08, 2019 at 09:45:13AM +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > H6 PWM core needs bus clock to be enabled in order to work. > > > > Add an optional probe for it and a fallback for previous > > bindings without name on module clock. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > drivers/pwm/pwm-sun4i.c | 48 +++++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 46 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 2b9a2a78591f..a10022d6c0fd 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -78,6 +78,7 @@ struct sun4i_pwm_data { > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > + struct clk *bus_clk; > > struct clk *clk; > > struct reset_control *rst; > > void __iomem *base; > > @@ -363,9 +364,38 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > if (IS_ERR(pwm->base)) > > return PTR_ERR(pwm->base); > > > > - pwm->clk = devm_clk_get(&pdev->dev, NULL); > > - if (IS_ERR(pwm->clk)) > > + /* Get all clocks and reset line */ > > + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); > > + if (IS_ERR(pwm->clk)) { > > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > > + dev_err(&pdev->dev, "get clock failed %pe\n", > > + pwm->clk); > > return PTR_ERR(pwm->clk); > > + } > > + > > + /* > > + * Fallback for old dtbs with a single clock and no name. > > + * If a parent has a clock-name called "mod" whereas the > > + * current node is unnamed the clock reference will be > > + * incorrectly obtained and will not go into this fallback. > > For me "old dtbs" suggests that today a device tree should have a "mod" > clock. Is this true also for machines other than H6? And I'd put the > comment before the acquisition of the "mod" clock. Something like: Agree to remove the "old dtbs" but specifying the SoC instead of the reason is less clear for me. I would prefer to have something like this: A clock is explicitly called "mod" when several clocks are referenced. However, when only one clock is declared this one is unamed. So we request "mod" first (and ignore the corner case that a parent provides a "mod" clock) and if this is not found we fall back to the first clock of the PWM. What do you think? > > /* > * A clock called "mod" is only required on H6 (for now) and on > * other SoCs we expect an unnamed clock. So we request "mod" > * first (and ignore the corner case that a parent provides a > * "mod" clock) and if this is not found we fall back to the > * first clock of the PWM. > */ > > > + */ > > + if (!pwm->clk) { > > + pwm->clk = devm_clk_get(&pdev->dev, NULL); > > + if (IS_ERR(pwm->clk)) { > > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > > + dev_err(&pdev->dev, "get clock failed %pe\n", > > + pwm->clk); > > + return PTR_ERR(pwm->clk); > > + } > > + } > > + > > + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); > > + if (IS_ERR(pwm->bus_clk)) { > > + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) > > + dev_err(&pdev->dev, "get bus_clock failed %pe\n", > > + pwm->bus_clk); > > + return PTR_ERR(pwm->bus_clk); > > + } > > > > pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > > if (IS_ERR(pwm->rst)) { > > @@ -382,6 +412,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > return ret; > > } > > > > + /* > > + * We're keeping the bus clock on for the sake of simplicity. > > + * Actually it only needs to be on for hardware register > > + * accesses. > > + */ > > + ret = clk_prepare_enable(pwm->bus_clk); > > + if (ret) { > > + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); > > + goto err_bus; > > + } > > + > > Would it make sense to split this patch into "Prefer "mod" clock to > (unnamed) clock" and "Introduce optional bus clock"? Yes I will do in v5, Regards, Clément > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | https://www.pengutronix.de/ |
Hi Uwe, On Wed, 13 Nov 2019 at 09:58, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > PWM core has an option to bypass whole logic and output unchanged source > > clock as PWM output. This is achieved by enabling bypass bit. > > > > Note that when bypass is enabled, no other setting has any meaning, not > > even enable bit. > > > > This mode of operation is needed to achieve high enough frequency to > > serve as clock source for AC200 chip which is integrated into same > > package as H6 SoC. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 44 insertions(+) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index a10022d6c0fd..9cc928ab47bc 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -3,6 +3,10 @@ > > * Driver for Allwinner sun4i Pulse Width Modulation Controller > > * > > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > > + * > > + * Limitations: > > + * - When outputing the source clock directly, the PWM logic will be bypassed > > + * and the currently running period is not guaranteed to be completed > > */ > > > > #include <linux/bitops.h> > > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_direct_mod_clk_output; > > unsigned int npwm; > > }; > > > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > + /* > > + * PWM chapter in H6 manual has a diagram which explains that if bypass > > + * bit is set, no other setting has any meaning. Even more, experiment > > + * proved that also enable bit is ignored in this case. > > + */ > > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > > + sun4i_pwm->data->has_direct_mod_clk_output) { > > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); > > I first thought you're losing precision here by reusing state->period > here, but with a divisor of 2 everything is fine. > > > + state->polarity = PWM_POLARITY_NORMAL; > > + state->enabled = true; > > + return; > > + } > > + > > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > > sun4i_pwm->data->has_prescaler_bypass) > > prescaler = 1; > > @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > > struct pwm_state cstate; > > u32 ctrl; > > + bool bypass = false; > > int ret; > > unsigned int delay_us; > > unsigned long now; > > @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > } > > } > > > > + /* > > + * Although it would make much more sense to check for bypass in > > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > > I don't understand this reasoning. sun4i_pwm_calculate knows about > .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just > add a bool *bypass as parameter and move the logic there? I asked myself the same question, however the sun4i_pwm_calculate is only called when period or duty_cycle is updated not when state is toggled between disabled / enabled. Should we also call it when the state is switched to enabled ? Regards, Clément > > > + */ > > + if (state->enabled) { > > + u32 clk_rate = clk_get_rate(sun4i_pwm->clk); > > + bypass = (state->period * clk_rate >= NSEC_PER_SEC) && > > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); > > + } > > + > > This looks right now. > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | https://www.pengutronix.de/ |
Hello Clément, On Thu, Nov 14, 2019 at 11:36:16PM +0100, Clément Péron wrote: > On Wed, 13 Nov 2019 at 09:35, Uwe Kleine-König > <u.kleine-koenig@pengutronix.de> wrote: > > On Fri, Nov 08, 2019 at 09:45:13AM +0100, Clément Péron wrote: > > > + /* > > > + * Fallback for old dtbs with a single clock and no name. > > > + * If a parent has a clock-name called "mod" whereas the > > > + * current node is unnamed the clock reference will be > > > + * incorrectly obtained and will not go into this fallback. > > > > For me "old dtbs" suggests that today a device tree should have a "mod" > > clock. Is this true also for machines other than H6? And I'd put the > > comment before the acquisition of the "mod" clock. Something like: > > Agree to remove the "old dtbs" but specifying the SoC instead > of the reason is less clear for me. > > I would prefer to have something like this: > > A clock is explicitly called "mod" when several clocks are referenced. > However, when only one clock is declared this one is unamed. > So we request "mod" first (and ignore the corner case that a parent > provides a "mod" clock) > and if this is not found we fall back to the first clock of the PWM. It gets better. What about also describing shortly the purpose of this clock (assuming this is the source clock of the PWM that is then divided): All hardware variants need a source clock that is divided and then feeds the counter that defines the output wave form. In the device tree this clock is either unnamed or called "mod". Some variants (e.g. H6) need another clock to access the hardware registers; this is called "bus". So we request "mod" first (and ignore the corner case that a parent provides a "mod" clock while the right one would be the unnamed one of the PWM device) and if this is not found we fall back to the first clock of the PWM. Best regards Uwe
Hello Clément, On Thu, Nov 14, 2019 at 11:47:00PM +0100, Clément Péron wrote: > On Wed, 13 Nov 2019 at 09:58, Uwe Kleine-König > <u.kleine-koenig@pengutronix.de> wrote: > > On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote: > > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > + /* > > > + * Although it would make much more sense to check for bypass in > > > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > > > > I don't understand this reasoning. sun4i_pwm_calculate knows about > > .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just > > add a bool *bypass as parameter and move the logic there? > > I asked myself the same question, however the sun4i_pwm_calculate is > only called when period or duty_cycle is updated not when state is > toggled between disabled / enabled. > > Should we also call it when the state is switched to enabled ? Given that the check if ((cstate.period != state->period) || (cstate.duty_cycle != state->duty_cycle)) { is not perfect anyhow (because if I toggle between pwm_apply_state(pwm, { .period = 50000001, .duty_cycle = 25000000, .enabled = true }); and pwm_apply_state(pwm, { .period = 50000000, .duty_cycle = 25000000, .enabled = true }); the code recalculates every parameter while it (probably) doesn't make a difference.) And also given that cstate is filled by pwm_get_state which might change its semantic slightly in the future I would say calculating the needed parameter always is also cleaner. (But I'm aware this isn't objective enough to overrule different opinions.) While I'm a fan of avoid unneeded calculations, I think having a simple driver is more important. (And apart from that I don't like lowlevel drivers calling the pwm API that is designed for consumers.) Best regards Uwe