| Message ID | 20191108051945.7109-1-joel@jms.id.au |
|---|---|
| Headers | show |
| Series | fsi: Patches for 5.5 | expand |
Support for the new paths has been added to our user space tools as well so it shouldn't change anything there. Acked-by: Alistair Popple <alistair@popple.id.au> On Friday, 8 November 2019 4:19:35 PM AEDT Joel Stanley wrote: > From: Jeremy Kerr <jk@ozlabs.org> > > This change adds a device class for FSI masters, allowing access under > /sys/class/fsi-master/, and easier udev rules. > > Signed-off-by: Jeremy Kerr <jk@ozlabs.org> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > drivers/fsi/fsi-core.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c > index 1f76740f33b6..0861f6097b33 100644 > --- a/drivers/fsi/fsi-core.c > +++ b/drivers/fsi/fsi-core.c > @@ -1241,6 +1241,10 @@ static ssize_t master_break_store(struct device *dev, > > static DEVICE_ATTR(break, 0200, NULL, master_break_store); > > +struct class fsi_master_class = { > + .name = "fsi-master", > +}; > + > int fsi_master_register(struct fsi_master *master) > { > int rc; > @@ -1249,6 +1253,7 @@ int fsi_master_register(struct fsi_master *master) > mutex_init(&master->scan_lock); > master->idx = ida_simple_get(&master_ida, 0, INT_MAX, GFP_KERNEL); > dev_set_name(&master->dev, "fsi%d", master->idx); > + master->dev.class = &fsi_master_class; > > rc = device_register(&master->dev); > if (rc) { > @@ -1350,8 +1355,15 @@ static int __init fsi_init(void) > rc = bus_register(&fsi_bus_type); > if (rc) > goto fail_bus; > + > + rc = class_register(&fsi_master_class); > + if (rc) > + goto fail_class; > + > return 0; > > + fail_class: > + bus_unregister(&fsi_bus_type); > fail_bus: > unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); > return rc; > @@ -1360,6 +1372,7 @@ postcore_initcall(fsi_init); > > static void fsi_exit(void) > { > + class_unregister(&fsi_master_class); > bus_unregister(&fsi_bus_type); > unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); > ida_destroy(&fsi_minor_ida); >
Acked-by: Alistair Popple <alistair@popple.id.au> On Friday, 8 November 2019 4:19:36 PM AEDT Joel Stanley wrote: > From: Jeremy Kerr <jk@ozlabs.org> > > Populate fsi_master_class->dev_attrs with the existing attribute > definitions, so we don't need to explicitly register. > > Signed-off-by: Jeremy Kerr <jk@ozlabs.org> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > drivers/fsi/fsi-core.c | 23 +++++++++-------------- > 1 file changed, 9 insertions(+), 14 deletions(-) > > diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c > index 0861f6097b33..c773c65a5058 100644 > --- a/drivers/fsi/fsi-core.c > +++ b/drivers/fsi/fsi-core.c > @@ -1241,8 +1241,17 @@ static ssize_t master_break_store(struct device *dev, > > static DEVICE_ATTR(break, 0200, NULL, master_break_store); > > +static struct attribute *master_attrs[] = { > + &dev_attr_break.attr, > + &dev_attr_rescan.attr, > + NULL > +}; > + > +ATTRIBUTE_GROUPS(master); > + > struct class fsi_master_class = { > .name = "fsi-master", > + .dev_groups = master_groups, > }; > > int fsi_master_register(struct fsi_master *master) > @@ -1261,20 +1270,6 @@ int fsi_master_register(struct fsi_master *master) > return rc; > } > > - rc = device_create_file(&master->dev, &dev_attr_rescan); > - if (rc) { > - device_del(&master->dev); > - ida_simple_remove(&master_ida, master->idx); > - return rc; > - } > - > - rc = device_create_file(&master->dev, &dev_attr_break); > - if (rc) { > - device_del(&master->dev); > - ida_simple_remove(&master_ida, master->idx); > - return rc; > - } > - > np = dev_of_node(&master->dev); > if (!of_property_read_bool(np, "no-scan-on-init")) { > mutex_lock(&master->scan_lock); >
Acked-by: Alistair Popple <alistair@popple.id.au> On Friday, 8 November 2019 4:19:38 PM AEDT Joel Stanley wrote: > From: Andrew Jeffery <andrew@aj.id.au> > > Due to other bugs I observed a spurious -1 transfer size. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > include/trace/events/fsi.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h > index 92e5e89e52ed..9832cb8e0eb0 100644 > --- a/include/trace/events/fsi.h > +++ b/include/trace/events/fsi.h > @@ -26,7 +26,7 @@ TRACE_EVENT(fsi_master_read, > __entry->addr = addr; > __entry->size = size; > ), > - TP_printk("fsi%d:%02d:%02d %08x[%zd]", > + TP_printk("fsi%d:%02d:%02d %08x[%zu]", > __entry->master_idx, > __entry->link, > __entry->id, > @@ -56,7 +56,7 @@ TRACE_EVENT(fsi_master_write, > __entry->data = 0; > memcpy(&__entry->data, data, size); > ), > - TP_printk("fsi%d:%02d:%02d %08x[%zd] <= {%*ph}", > + TP_printk("fsi%d:%02d:%02d %08x[%zu] <= {%*ph}", > __entry->master_idx, > __entry->link, > __entry->id, > @@ -93,7 +93,7 @@ TRACE_EVENT(fsi_master_rw_result, > if (__entry->write || !__entry->ret) > memcpy(&__entry->data, data, size); > ), > - TP_printk("fsi%d:%02d:%02d %08x[%zd] %s {%*ph} ret %d", > + TP_printk("fsi%d:%02d:%02d %08x[%zu] %s {%*ph} ret %d", > __entry->master_idx, > __entry->link, > __entry->id, >
On Friday, 8 November 2019 4:19:37 PM AEDT Joel Stanley wrote: > The paths added back in 4.13 weren't quite correct. The in reality the Minor nit-pick, it should read "In reality the...". Otherwise looks reasonable. Acked-by: Alistair Popple <alistair@popple.id.au> > files documented lived under > > /sys/devices/../fsi0/rescan > /sys/devices/../fsi0/break > /sys/devices/../fsi0/slave@00:00/term > /sys/devices/../fsi0/slave@00:00/raw > > In 5.5 with the addition of the FSI class they move to > > /sys/devices/../fsi-master/fsi0/rescan > /sys/devices/../fsi-master/fsi0/break > /sys/devices/../fsi-master/fsi0/slave@00:00/term > /sys/devices/../fsi-master/fsi0/slave@00:00/raw > > This is closer to how the (incorrect) documentation described them. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > Documentation/ABI/testing/sysfs-bus-fsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/Documentation/ABI/testing/sysfs-bus-fsi b/Documentation/ABI/testing/sysfs-bus-fsi > index 57c806350d6c..320697bdf41d 100644 > --- a/Documentation/ABI/testing/sysfs-bus-fsi > +++ b/Documentation/ABI/testing/sysfs-bus-fsi > @@ -1,25 +1,25 @@ > -What: /sys/bus/platform/devices/fsi-master/rescan > +What: /sys/bus/platform/devices/../fsi-master/fsi0/rescan > Date: May 2017 > KernelVersion: 4.12 > -Contact: cbostic@linux.vnet.ibm.com > +Contact: linux-fsi@lists.ozlabs.org > Description: > Initiates a FSI master scan for all connected slave devices > on its links. > > -What: /sys/bus/platform/devices/fsi-master/break > +What: /sys/bus/platform/devices/../fsi-master/fsi0/break > Date: May 2017 > KernelVersion: 4.12 > -Contact: cbostic@linux.vnet.ibm.com > +Contact: linux-fsi@lists.ozlabs.org > Description: > Sends an FSI BREAK command on a master's communication > link to any connnected slaves. A BREAK resets connected > device's logic and preps it to receive further commands > from the master. > > -What: /sys/bus/platform/devices/fsi-master/slave@00:00/term > +What: /sys/bus/platform/devices/../fsi-master/fsi0/slave@00:00/term > Date: May 2017 > KernelVersion: 4.12 > -Contact: cbostic@linux.vnet.ibm.com > +Contact: linux-fsi@lists.ozlabs.org > Description: > Sends an FSI terminate command from the master to its > connected slave. A terminate resets the slave's state machines > @@ -29,10 +29,10 @@ Description: > ongoing operation in case of an expired 'Master Time Out' > timer. > > -What: /sys/bus/platform/devices/fsi-master/slave@00:00/raw > +What: /sys/bus/platform/devices/../fsi-master/fsi0/slave@00:00/raw > Date: May 2017 > KernelVersion: 4.12 > -Contact: cbostic@linux.vnet.ibm.com > +Contact: linux-fsi@lists.ozlabs.org > Description: > Provides a means of reading/writing a 32 bit value from/to a > specified FSI bus address. >
Having a hardware master should make things quicker. Acked-by: Alistair Popple <alistair@popple.id.au> On Friday, 8 November 2019 4:19:43 PM AEDT Joel Stanley wrote: > The ast2600 BMC has a pair of FSI masters in it, behind an AHB to OPB > bridge. > > The master driver supports reads and writes of full words, half word and > byte accesses to remote CFAMs. It can perform very basic error recovery > through resetting of the FSI port when an error is detected, and the > issuing of breaks and terms. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > -- > v2: > - remove debugging > - squash in fixes > --- > drivers/fsi/Kconfig | 8 + > drivers/fsi/Makefile | 1 + > drivers/fsi/fsi-master-aspeed.c | 522 ++++++++++++++++++++++++++++++++ > 3 files changed, 531 insertions(+) > create mode 100644 drivers/fsi/fsi-master-aspeed.c > > diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig > index c612db7a914a..92ce6d85802c 100644 > --- a/drivers/fsi/Kconfig > +++ b/drivers/fsi/Kconfig > @@ -53,6 +53,14 @@ config FSI_MASTER_AST_CF > lines driven by the internal ColdFire coprocessor. This requires > the corresponding machine specific ColdFire firmware to be available. > > +config FSI_MASTER_ASPEED > + tristate "FSI ASPEED master" > + help > + This option enables a FSI master that is present behind an OPB bridge > + in the AST2600. > + > + Enable it for your BMC kernel in an OpenPower or IBM Power system. > + > config FSI_SCOM > tristate "SCOM FSI client device driver" > ---help--- > diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile > index e4a2ff043c32..da218a1ad8e1 100644 > --- a/drivers/fsi/Makefile > +++ b/drivers/fsi/Makefile > @@ -2,6 +2,7 @@ > > obj-$(CONFIG_FSI) += fsi-core.o > obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o > +obj-$(CONFIG_FSI_MASTER_ASPEED) += fsi-master-aspeed.o > obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o > obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o > obj-$(CONFIG_FSI_SCOM) += fsi-scom.o > diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c > new file mode 100644 > index 000000000000..d1b83f035483 > --- /dev/null > +++ b/drivers/fsi/fsi-master-aspeed.c > @@ -0,0 +1,522 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +// Copyright (C) IBM Corporation 2018 > +// FSI master driver for AST2600 > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/fsi.h> > +#include <linux/io.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/slab.h> > +#include <linux/iopoll.h> > + > +#include "fsi-master.h" > + > +struct fsi_master_aspeed { > + struct fsi_master master; > + struct device *dev; > + void __iomem *base; > + struct clk *clk; > +}; > + > +#define to_fsi_master_aspeed(m) \ > + container_of(m, struct fsi_master_aspeed, master) > + > +/* Control register (size 0x400) */ > +static const u32 ctrl_base = 0x80000000; > + > +static const u32 fsi_base = 0xa0000000; > + > +#define OPB_FSI_VER 0x00 > +#define OPB_TRIGGER 0x04 > +#define OPB_CTRL_BASE 0x08 > +#define OPB_FSI_BASE 0x0c > +#define OPB_CLK_SYNC 0x3c > +#define OPB_IRQ_CLEAR 0x40 > +#define OPB_IRQ_MASK 0x44 > +#define OPB_IRQ_STATUS 0x48 > + > +#define OPB0_SELECT 0x10 > +#define OPB0_RW 0x14 > +#define OPB0_XFER_SIZE 0x18 > +#define OPB0_FSI_ADDR 0x1c > +#define OPB0_FSI_DATA_W 0x20 > +#define OPB0_STATUS 0x80 > +#define OPB0_FSI_DATA_R 0x84 > + > +#define OPB0_WRITE_ORDER1 0x4c > +#define OPB0_WRITE_ORDER2 0x50 > +#define OPB1_WRITE_ORDER1 0x54 > +#define OPB1_WRITE_ORDER2 0x58 > +#define OPB0_READ_ORDER1 0x5c > +#define OPB1_READ_ORDER2 0x60 > + > +#define OPB_RETRY_COUNTER 0x64 > + > +/* OPBn_STATUS */ > +#define STATUS_HALFWORD_ACK BIT(0) > +#define STATUS_FULLWORD_ACK BIT(1) > +#define STATUS_ERR_ACK BIT(2) > +#define STATUS_RETRY BIT(3) > +#define STATUS_TIMEOUT BIT(4) > + > +/* OPB_IRQ_MASK */ > +#define OPB1_XFER_ACK_EN BIT(17) > +#define OPB0_XFER_ACK_EN BIT(16) > + > +/* OPB_RW */ > +#define CMD_READ BIT(0) > +#define CMD_WRITE 0 > + > +/* OPBx_XFER_SIZE */ > +#define XFER_FULLWORD (BIT(1) | BIT(0)) > +#define XFER_HALFWORD (BIT(0)) > +#define XFER_BYTE (0) > + > +#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ > + > +#define DEFAULT_DIVISOR 14 > +#define OPB_POLL_TIMEOUT 10000 > + > +static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, > + u32 val, u32 transfer_size) > +{ > + void __iomem *base = aspeed->base; > + u32 reg, status; > + int ret; > + > + writel(CMD_WRITE, base + OPB0_RW); > + writel(transfer_size, base + OPB0_XFER_SIZE); > + writel(addr, base + OPB0_FSI_ADDR); > + writel(val, base + OPB0_FSI_DATA_W); > + writel(0x1, base + OPB_IRQ_CLEAR); > + writel(0x1, base + OPB_TRIGGER); > + > + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, > + (reg & OPB0_XFER_ACK_EN) != 0, > + 0, OPB_POLL_TIMEOUT); > + > + status = readl(base + OPB0_STATUS); > + > + /* Return error when poll timed out */ > + if (ret) > + return ret; > + > + /* Command failed, master will reset */ > + if (status & STATUS_ERR_ACK) > + return -EIO; > + > + return 0; > +} > + > +static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val) > +{ > + return __opb_write(aspeed, addr, val, XFER_BYTE); > +} > + > +static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val) > +{ > + return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD); > +} > + > +static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val) > +{ > + return __opb_write(aspeed, addr, (__force u32)val, XFER_FULLWORD); > +} > + > +static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, > + u32 transfer_size, void *out) > +{ > + void __iomem *base = aspeed->base; > + u32 result, reg; > + int status, ret; > + > + writel(CMD_READ, base + OPB0_RW); > + writel(transfer_size, base + OPB0_XFER_SIZE); > + writel(addr, base + OPB0_FSI_ADDR); > + writel(0x1, base + OPB_IRQ_CLEAR); > + writel(0x1, base + OPB_TRIGGER); > + > + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, > + (reg & OPB0_XFER_ACK_EN) != 0, > + 0, OPB_POLL_TIMEOUT); > + > + status = readl(base + OPB0_STATUS); > + > + result = readl(base + OPB0_FSI_DATA_R); > + > + /* Return error when poll timed out */ > + if (ret) > + return ret; > + > + /* Command failed, master will reset */ > + if (status & STATUS_ERR_ACK) > + return -EIO; > + > + if (out) { > + switch (transfer_size) { > + case XFER_BYTE: > + *(u8 *)out = result; > + break; > + case XFER_HALFWORD: > + *(u16 *)out = result; > + break; > + case XFER_FULLWORD: > + *(u32 *)out = result; > + break; > + default: > + return -EINVAL; > + } > + > + } > + > + return 0; > +} > + > +static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out) > +{ > + return __opb_read(aspeed, addr, XFER_FULLWORD, out); > +} > + > +static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out) > +{ > + return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out); > +} > + > +static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out) > +{ > + return __opb_read(aspeed, addr, XFER_BYTE, (void *)out); > +} > + > +static int check_errors(struct fsi_master_aspeed *aspeed, int err) > +{ > + int ret; > + > + if (err == -EIO) { > + /* Check MAEB (0x70) ? */ > + > + /* Then clear errors in master */ > + ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, > + cpu_to_be32(FSI_MRESP_RST_ALL_MASTER)); > + if (ret) { > + /* TODO: log? return different code? */ > + return ret; > + } > + /* TODO: confirm that 0x70 was okay */ > + } > + > + /* This will pass through timeout errors */ > + return err; > +} > + > +static int aspeed_master_read(struct fsi_master *master, int link, > + uint8_t id, uint32_t addr, void *val, size_t size) > +{ > + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); > + int ret; > + > + if (id != 0) > + return -EINVAL; > + > + addr += link * FSI_HUB_LINK_SIZE; > + > + switch (size) { > + case 1: > + ret = opb_readb(aspeed, fsi_base + addr, val); > + break; > + case 2: > + ret = opb_readw(aspeed, fsi_base + addr, val); > + break; > + case 4: > + ret = opb_readl(aspeed, fsi_base + addr, val); > + break; > + default: > + return -EINVAL; > + } > + > + ret = check_errors(aspeed, ret); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int aspeed_master_write(struct fsi_master *master, int link, > + uint8_t id, uint32_t addr, const void *val, size_t size) > +{ > + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); > + int ret; > + > + if (id != 0) > + return -EINVAL; > + > + addr += link * FSI_HUB_LINK_SIZE; > + > + switch (size) { > + case 1: > + ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val); > + break; > + case 2: > + ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val); > + break; > + case 4: > + ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val); > + break; > + default: > + return -EINVAL; > + } > + > + ret = check_errors(aspeed, ret); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int aspeed_master_link_enable(struct fsi_master *master, int link) > +{ > + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); > + int idx, bit, ret; > + __be32 reg, result; > + > + idx = link / 32; > + bit = link % 32; > + > + reg = cpu_to_be32(0x80000000 >> bit); > + > + ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg); > + if (ret) > + return ret; > + > + mdelay(FSI_LINK_ENABLE_SETUP_TIME); > + > + ret = opb_readl(aspeed, ctrl_base + FSI_MENP0 + (4 * idx), &result); > + if (ret) > + return ret; > + > + if (result != reg) { > + dev_err(aspeed->dev, "%s failed: %08x\n", __func__, result); > + return -EIO; > + } > + > + return 0; > +} > + > +static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id) > +{ > + uint32_t addr; > + __be32 cmd; > + > + addr = 0x4; > + cmd = cpu_to_be32(0xecc00000); > + > + return aspeed_master_write(master, link, id, addr, &cmd, 4); > +} > + > +static int aspeed_master_break(struct fsi_master *master, int link) > +{ > + uint32_t addr; > + __be32 cmd; > + > + addr = 0x0; > + cmd = cpu_to_be32(0xc0de0000); > + > + return aspeed_master_write(master, link, 0, addr, &cmd, 4); > +} > + > +static void aspeed_master_release(struct device *dev) > +{ > + struct fsi_master_aspeed *aspeed = > + to_fsi_master_aspeed(dev_to_fsi_master(dev)); > + > + kfree(aspeed); > +} > + > +/* mmode encoders */ > +static inline u32 fsi_mmode_crs0(u32 x) > +{ > + return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; > +} > + > +static inline u32 fsi_mmode_crs1(u32 x) > +{ > + return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; > +} > + > +static int aspeed_master_init(struct fsi_master_aspeed *aspeed) > +{ > + __be32 reg; > + > + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK > + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); > + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); > + > + /* Initialize the MFSI (hub master) engine */ > + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK > + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); > + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); > + > + reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); > + opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); > + > + reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA > + | fsi_mmode_crs0(DEFAULT_DIVISOR) > + | fsi_mmode_crs1(DEFAULT_DIVISOR) > + | FSI_MMODE_P8_TO_LSB); > + opb_writel(aspeed, ctrl_base + FSI_MMODE, reg); > + > + reg = cpu_to_be32(0xffff0000); > + opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg); > + > + reg = cpu_to_be32(~0); > + opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg); > + > + /* Leave enabled long enough for master logic to set up */ > + mdelay(FSI_LINK_ENABLE_SETUP_TIME); > + > + opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg); > + > + opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL); > + > + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); > + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); > + > + opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL); > + > + /* Reset the master bridge */ > + reg = cpu_to_be32(FSI_MRESB_RST_GEN); > + opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); > + > + reg = cpu_to_be32(FSI_MRESB_RST_ERR); > + opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); > + > + return 0; > +} > + > +static int fsi_master_aspeed_probe(struct platform_device *pdev) > +{ > + struct fsi_master_aspeed *aspeed; > + struct resource *res; > + int rc, links, reg; > + __be32 raw; > + > + aspeed = devm_kzalloc(&pdev->dev, sizeof(*aspeed), GFP_KERNEL); > + if (!aspeed) > + return -ENOMEM; > + > + aspeed->dev = &pdev->dev; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + aspeed->base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(aspeed->base)) > + return PTR_ERR(aspeed->base); > + > + aspeed->clk = devm_clk_get(aspeed->dev, NULL); > + if (IS_ERR(aspeed->clk)) { > + dev_err(aspeed->dev, "couldn't get clock\n"); > + return PTR_ERR(aspeed->clk); > + } > + rc = clk_prepare_enable(aspeed->clk); > + if (rc) { > + dev_err(aspeed->dev, "couldn't enable clock\n"); > + return rc; > + } > + > + writel(0x1, aspeed->base + OPB_CLK_SYNC); > + writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN, > + aspeed->base + OPB_IRQ_MASK); > + > + /* TODO: determine an appropriate value */ > + writel(0x10, aspeed->base + OPB_RETRY_COUNTER); > + > + writel(ctrl_base, aspeed->base + OPB_CTRL_BASE); > + writel(fsi_base, aspeed->base + OPB_FSI_BASE); > + > + /* Set read data order */ > + writel(0x0011bb1b, aspeed->base + OPB0_READ_ORDER1); > + > + /* Set write data order */ > + writel(0x0011bb1b, aspeed->base + OPB0_WRITE_ORDER1); > + writel(0xffaa5500, aspeed->base + OPB0_WRITE_ORDER2); > + > + /* > + * Select OPB0 for all operations. > + * Will need to be reworked when enabling DMA or anything that uses > + * OPB1. > + */ > + writel(0x1, aspeed->base + OPB0_SELECT); > + > + rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw); > + if (rc) { > + dev_err(&pdev->dev, "failed to read hub version\n"); > + return rc; > + } > + > + reg = be32_to_cpu(raw); > + links = (reg >> 8) & 0xff; > + dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links); > + > + aspeed->master.dev.parent = &pdev->dev; > + aspeed->master.dev.release = aspeed_master_release; > + aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev)); > + > + aspeed->master.n_links = links; > + aspeed->master.read = aspeed_master_read; > + aspeed->master.write = aspeed_master_write; > + aspeed->master.send_break = aspeed_master_break; > + aspeed->master.term = aspeed_master_term; > + aspeed->master.link_enable = aspeed_master_link_enable; > + > + dev_set_drvdata(&pdev->dev, aspeed); > + > + aspeed_master_init(aspeed); > + > + rc = fsi_master_register(&aspeed->master); > + if (rc) > + goto err_release; > + > + /* At this point, fsi_master_register performs the device_initialize(), > + * and holds the sole reference on master.dev. This means the device > + * will be freed (via ->release) during any subsequent call to > + * fsi_master_unregister. We add our own reference to it here, so we > + * can perform cleanup (in _remove()) without it being freed before > + * we're ready. > + */ > + get_device(&aspeed->master.dev); > + return 0; > + > +err_release: > + clk_disable_unprepare(aspeed->clk); > + return rc; > +} > + > +static int fsi_master_aspeed_remove(struct platform_device *pdev) > +{ > + struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev); > + > + fsi_master_unregister(&aspeed->master); > + clk_disable_unprepare(aspeed->clk); > + > + return 0; > +} > + > +static const struct of_device_id fsi_master_aspeed_match[] = { > + { .compatible = "aspeed,ast2600-fsi-master" }, > + { }, > +}; > + > +static struct platform_driver fsi_master_aspeed_driver = { > + .driver = { > + .name = "fsi-master-aspeed", > + .of_match_table = fsi_master_aspeed_match, > + }, > + .probe = fsi_master_aspeed_probe, > + .remove = fsi_master_aspeed_remove, > +}; > + > +module_platform_driver(fsi_master_aspeed_driver); > +MODULE_LICENSE("GPL"); >
OPB data mirroring is pretty special, glad someone has figured it out and made some artwork in the process. Acked-by: Alistair Popple <alistair@popple.id.au> On Friday, 8 November 2019 4:19:45 PM AEDT Joel Stanley wrote: > From: Andrew Jeffery <andrew@aj.id.au> > > The data byte order selection registers in the APB2OPB primarily expose some > internal plumbing necessary to get correct write accesses onto the OPB. > OPB write cycles require "data mirroring" across the 32-bit data bus to > support variable data width slaves that don't implement "byte enables". > For slaves that do implement byte enables the master can signal which > bytes on the data bus the slave should consider valid. > > The data mirroring behaviour is specified by the following table: > > +-----------------+----------+-----------------------------------+ > | | | 32-bit Data Bus | > +---------+-------+----------+---------+---------+-------+-------+ > | | | | | | | | > | ABus | Mn_BE | Request | Dbus | Dbus | Dbus | Dbus | > | (30:31) | (0:3) | Transfer | 0:7 | 8:15 | 16:23 | 24:31 | > | | | Size | byte0 | byte1 | byte2 | byte3 | > +---------+-------+----------+---------+---------+-------+-------+ > | 00 | 1111 | fullword | byte0 | byte1 | byte2 | byte3 | > +---------+-------+----------+---------+---------+-------+-------+ > | 00 | 1110 | halfword | byte0 | byte1 | byte2 | | > +---------+-------+----------+---------+---------+-------+-------+ > | 01 | 0111 | byte | _byte1_ | byte1 | byte2 | byte3 | > +---------+-------+----------+---------+---------+-------+-------+ > | 00 | 1100 | halfword | byte0 | byte1 | | | > +---------+-------+----------+---------+---------+-------+-------+ > | 01 | 0110 | byte | _byte1_ | byte1 | byte2 | | > +---------+-------+----------+---------+---------+-------+-------+ > | 10 | 0011 | halfword | _byte2_ | _byte3_ | byte2 | byte3 | > +---------+-------+----------+---------+---------+-------+-------+ > | 00 | 1000 | byte | byte0 | | | | > +---------+-------+----------+---------+---------+-------+-------+ > | 01 | 0100 | byte | _byte1_ | byte1 | | | > +---------+-------+----------+---------+---------+-------+-------+ > | 10 | 0010 | byte | _byte2_ | | byte2 | | > +---------+-------+----------+---------+---------+-------+-------+ > | 11 | 0001 | byte | _byte3_ | _byte3_ | | byte3 | > +---------+-------+----------+---------+---------+-------+-------+ > > Mirrored data values are highlighted by underscores in the Dbus columns. > The values in the ABus and Request Transfer Size columns correspond to > values in the field names listed in the write data order select register > descriptions. > > Similar configuration registers are exposed for reads which enables the > secondary purpose of configuring hardware endian conversions. It appears the > data bus byte order is switched around in hardware so set the registers such > that we can access the correct values for all widths. The values were > determined by experimentation on hardware against fixed CFAM register > values to configure the read data order, then in combination with the > table above and the register layout documentation in the AST2600 > datasheet performing write/read cycles to configure the write data order > registers. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > drivers/fsi/fsi-master-aspeed.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master- aspeed.c > index 95e226ac78b9..f49742b310c2 100644 > --- a/drivers/fsi/fsi-master-aspeed.c > +++ b/drivers/fsi/fsi-master-aspeed.c > @@ -459,11 +459,11 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) > writel(fsi_base, aspeed->base + OPB_FSI_BASE); > > /* Set read data order */ > - writel(0x0011bb1b, aspeed->base + OPB0_READ_ORDER1); > + writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1); > > /* Set write data order */ > - writel(0x0011bb1b, aspeed->base + OPB0_WRITE_ORDER1); > - writel(0xffaa5500, aspeed->base + OPB0_WRITE_ORDER2); > + writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1); > + writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2); > > /* > * Select OPB0 for all operations. >