| Message ID | 20191106065017.22144-1-rnayak@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add device tree support for sc7180 | expand |
On Wed, Nov 06 2019 at 23:52 -0700, Rajendra Nayak wrote: >Remove the sdm845 SoC specific compatible to make the driver >easily reusable across other SoC's with the same IP block. >This will reduce further churn adding any SoC specific >compatibles unless really needed. > >Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >Cc: Lina Iyer <ilina@codeaurora.org> >Cc: Marc Zyngier <maz@kernel.org> Reviewed-by: Lina Iyer <ilina@codeaurora.org> >--- > drivers/irqchip/qcom-pdc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c >index faa7d61b9d6c..c175333bb646 100644 >--- a/drivers/irqchip/qcom-pdc.c >+++ b/drivers/irqchip/qcom-pdviewed-by: Lina Iyer <ilina@codeaurora.org> >@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) > return ret; > } > >-IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); >+IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); >-- >QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member >of Code Aurora Forum, hosted by The Linux Foundation >
Quoting Rajendra Nayak (2019-11-05 22:50:10) > Remove the sdm845 SoC specific compatible to make the driver > easily reusable across other SoC's with the same IP block. > This will reduce further churn adding any SoC specific > compatibles unless really needed. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Cc: Lina Iyer <ilina@codeaurora.org> > Cc: Marc Zyngier <maz@kernel.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:12) > From: Maulik Shah <mkshah@codeaurora.org> > > Add pdc interrupt controller for sc7180 > > Signed-off-by: Maulik Shah <mkshah@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:05) > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > new file mode 100644 > index 000000000000..17870dd67390 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -0,0 +1,299 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * SC7180 SoC device tree source > + * > + * Copyright (c) 2019, The Linux Foundation. All rights reserved. > + */ > + > +#include <dt-bindings/clock/qcom,gcc-sc7180.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + clock-frequency = <38400000>; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32764>; > + clock-output-names = "sleep_clk"; Remove this one too? > + #clock-cells = <0>; > + }; > + }; > + [...] > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + soc: soc { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; > + > + gcc: clock-controller@100000 { > + compatible = "qcom,gcc-sc7180"; > + reg = <0 0x00100000 0 0x1f0000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0 0x00ac0000 0 0x6000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart8: serial@a88000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0 0x00a88000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart8_default>; > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + }; > + > + tlmm: pinctrl@3500000 { > + compatible = "qcom,sc7180-pinctrl"; > + reg = <0 0x03500000 0 0x300000>, > + <0 0x03900000 0 0x300000>, > + <0 0x03d00000 0 0x300000>; > + reg-names = "west", "north", "south"; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 120>; > + > + qup_uart8_default: qup-uart8-default { > + pinmux { > + pins = "gpio44", "gpio45"; > + function = "qup12"; That looks weird to have qup12 function on uart8. It's right? > + }; > + }; > + }; > +
Quoting Rajendra Nayak (2019-11-05 22:50:07) > From: Vivek Gautam <vivek.gautam@codeaurora.org> > > Adding device node for APPS SMMU that is connected to > devices such as display, video, usb, mmc, etc. on SC7180 > chipset. > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:08) > From: Maulik Shah <mkshah@codeaurora.org> > > Command_db provides mapping for resource key and address managed > by remote processor. Add cmd_db reserved memory area. > > Signed-off-by: Maulik Shah <mkshah@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:09) > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 61250560c7ef..98c8ab7d613c 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -387,6 +388,24 @@ > status = "disabled"; > }; > }; > + > + apps_rsc: rsc@18200000 { The node name is non-standard. This has been a problem since sdm845 though so it would be nice if we can invent some new name for this that is standard at some point in the future. > + label = "apps_rsc"; Can we remove this property? The value seems minimal given that we can use the dev_name() and get the address in there instead of using a label.
Quoting Rajendra Nayak (2019-11-05 22:50:09) > From: Maulik Shah <mkshah@codeaurora.org> > > Add device bindings for the application processor's rsc. The rsc > contains the TCS that are used for communicating with the hardened > resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs. > > Signed-off-by: Maulik Shah <mkshah@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:13) > From: Kiran Gunda <kgunda@codeaurora.org> > > Add SPMI PMIC arbiter device to communicate with PMICs > attached to SPMI bus. > > Signed-off-by: Kiran Gunda <kgunda@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:14) > From: Kiran Gunda <kgunda@codeaurora.org> > > Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other > PMIC infra modules. > > Signed-off-by: Kiran Gunda <kgunda@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:16) > From: Taniya Das <tdas@codeaurora.org> > > Add node for rpmhcc clock driver. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2019-11-05 22:50:17) > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QUP SE instances configuration for sc7180. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> It has the weird qup numbering too, but I guess it's correct somehow.
On 11/7/2019 11:16 PM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2019-11-05 22:50:05) >> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> new file mode 100644 >> index 000000000000..17870dd67390 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> @@ -0,0 +1,299 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * SC7180 SoC device tree source >> + * >> + * Copyright (c) 2019, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include <dt-bindings/clock/qcom,gcc-sc7180.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + interrupt-parent = <&intc>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + chosen { }; >> + >> + clocks { >> + xo_board: xo-board { >> + compatible = "fixed-clock"; >> + clock-frequency = <38400000>; >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <32764>; >> + clock-output-names = "sleep_clk"; > > Remove this one too? ah, yes. Not sure how I missed that :/ > >> + #clock-cells = <0>; >> + }; >> + }; >> + > [...] >> + memory@80000000 { >> + device_type = "memory"; >> + /* We expect the bootloader to fill in the size */ >> + reg = <0 0x80000000 0 0>; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + }; >> + >> + soc: soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0 0 0 0 0x10 0>; >> + dma-ranges = <0 0 0 0 0x10 0>; >> + compatible = "simple-bus"; >> + >> + gcc: clock-controller@100000 { >> + compatible = "qcom,gcc-sc7180"; >> + reg = <0 0x00100000 0 0x1f0000>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + qupv3_id_1: geniqup@ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0 0x00ac0000 0 0x6000>; >> + clock-names = "m-ahb", "s-ahb"; >> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + uart8: serial@a88000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0 0x00a88000 0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart8_default>; >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + }; >> + >> + tlmm: pinctrl@3500000 { >> + compatible = "qcom,sc7180-pinctrl"; >> + reg = <0 0x03500000 0 0x300000>, >> + <0 0x03900000 0 0x300000>, >> + <0 0x03d00000 0 0x300000>; >> + reg-names = "west", "north", "south"; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + gpio-ranges = <&tlmm 0 0 120>; >> + >> + qup_uart8_default: qup-uart8-default { >> + pinmux { >> + pins = "gpio44", "gpio45"; >> + function = "qup12"; > > That looks weird to have qup12 function on uart8. It's right? So we have 2 qup instances each with 6 SEs on sc7180. So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup and 6 to 11 in the next. The pinctrl functions however have it named qup0 to 5 for first and qup10 to 15 for the next which is weird. Now all data in the pinctrl driver is autogenerated using hw description so its coming from that. Just for comparison, on sdm845 we had 2 qup instances with 8 SE's and the function names were qup0 to 8 for first and 9 to 15 for the second.
On 11/7/2019 11:23 PM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2019-11-05 22:50:09) >> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> index 61250560c7ef..98c8ab7d613c 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> @@ -387,6 +388,24 @@ >> status = "disabled"; >> }; >> }; >> + >> + apps_rsc: rsc@18200000 { > > The node name is non-standard. This has been a problem since sdm845 > though so it would be nice if we can invent some new name for this that > is standard at some point in the future. > >> + label = "apps_rsc"; > > Can we remove this property? The value seems minimal given that we can > use the dev_name() and get the address in there instead of using a label. Sure, i'll remove it.
On 11/8/2019 12:22 AM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2019-11-05 22:50:17) >> From: Roja Rani Yarubandi <rojay@codeaurora.org> >> >> Add QUP SE instances configuration for sc7180. >> >> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> --- > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > It has the weird qup numbering too, but I guess it's correct somehow. I responded to PATCH 2/14 as to why its weird.
Quoting Rajendra Nayak (2019-11-07 19:48:57) > > On 11/7/2019 11:16 PM, Stephen Boyd wrote: > > Quoting Rajendra Nayak (2019-11-05 22:50:05) > >> + qup_uart8_default: qup-uart8-default { > >> + pinmux { > >> + pins = "gpio44", "gpio45"; > >> + function = "qup12"; > > > > That looks weird to have qup12 function on uart8. It's right? > > So we have 2 qup instances each with 6 SEs on sc7180. > So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup > and 6 to 11 in the next. > The pinctrl functions however have it named qup0 to 5 for first and > qup10 to 15 for the next which is weird. Now all data in the pinctrl > driver is autogenerated using hw description so its coming from that. > > Just for comparison, on sdm845 we had 2 qup instances with 8 SE's > and the function names were qup0 to 8 for first and 9 to 15 for the > second. > Alright. Good to know the hardware description is all messed up.