| Message ID | 20191029210821.1954-1-suneelglinux@gmail.com |
|---|---|
| Headers | show |
| Series | arm: Introduce Marvell/Cavium OcteonTX | expand |
On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > This series will add support for OcteonTX and OcteonTX2 processsor based > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > support for CN96XX and CN95XX. > These SoC's have peripheral drivers based on PCI ECAM. > > Patches > [1 -10] Add requied changes to PCI framework > - [6] Add support for multi-memory region range > - [7] EA in bridges > - [8] SR-IOV > [12] Add driver model support for RTC DS1337 driver > [15 - 17] AHCI changes > [18 - 27] Add OcteonTX drivers > [28 - 29] Add OcteonTX/TX2 board files and configurations > Suneel, Thanks for submitting this series! I've applied and built this and am testing on the Gateworks Newport boards with the CN802x/CN803x (octeontx_81xx) and this is what I've found: - I get hung in the smc_call from smc_dram_size which your calling with the function id of 0xc2000301. The older U-Boot from the Cavium OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there a difference in our ATF version? - configs/octeontx_81xx_defconfig - I have several changes I want to make here, but perhaps some of these would warrant a custom config for my boards - you assume there is only a SPI NOR flash for env which we personally don't use. The env system supports multiple env types so we could just enable MMC as well as SPI but then I find all the hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has defined a way for these to come from device-tree? - you set loadaddr=040080000 which only makes sense for systems with over 1GiB of DRAM... perhaps we should lower that to loadaddr=020080000 for 1GiB systems (I don't think you can have less than 1GiB?) - I use DISTRO_DEFAULTS for a standard distro-friendly boot env... I'm not sure why any board wouldn't do this these days and I think that should be added I was able to functionally test mmc/i2c/gpio/pci/nic(BGX/RGX) and they were all functioning well. When I enable SATA I find that it crashes on init: GW6300-D1> sata info Target spinup took 0 ms. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst "Synchronous Abort" handler, esr 0x96000006 elr: 000000000052c240 lr : 00000000005101bc (reloc) elr: 000000003fecb240 lr : 000000003feaf1bc x0 : 000000003be91380 x1 : 0000000000000000 x2 : 0000000000000000 x3 : 000000003be9c100 x4 : 0000000000000120 x5 : 000000003be9b800 x6 : 0000000000000001 x7 : 0000000000000000 x8 : 000000003ff46998 x9 : 0000000000000008 x10: 000000003ff2e8c4 x11: 000000003ff2e8ca x12: 000000003ff2e8cf x13: 000000003ff2e8d5 x14: 000000003ff2e8da x15: 000000003ff2e8e0 x16: 000000003ff2e8e6 x17: 000000003ff43362 x18: 000000003be8ede0 x19: 0000000000000000 x20: 000000003be9ab30 x21: 0000000000000002 x22: 000000003be9ab30 x23: 0000000000000002 x24: 000000003ff63aa4 x25: 000000003be9ab90 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 000000003be881f0 Code: 928004a0 d65f03c0 f9400007 f94034e7 (f94008e7) Resetting CPU ... I don't have NAND or SPI flash so can't test those. Best Regards, Tim
Hi Tim, I think I can answer some of your questions. On Wednesday, October 30, 2019 10:06:41 AM PDT Tim Harvey wrote: > External Email > > ---------------------------------------------------------------------- > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > This series will add support for OcteonTX and OcteonTX2 processsor based > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs > > include support for CN96XX and CN95XX. > > These SoC's have peripheral drivers based on PCI ECAM. > > > > Patches > > [1 -10] Add requied changes to PCI framework > > > > - [6] Add support for multi-memory region range > > - [7] EA in bridges > > - [8] SR-IOV > > > > [12] Add driver model support for RTC DS1337 driver > > [15 - 17] AHCI changes > > [18 - 27] Add OcteonTX drivers > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > Suneel, > > Thanks for submitting this series! > > I've applied and built this and am testing on the Gateworks Newport > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > found: > - I get hung in the smc_call from smc_dram_size which your calling > with the function id of 0xc2000301. The older U-Boot from the Cavium > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > a difference in our ATF version? ATF has indeed changed significantly. The current U-Boot requires an up-to- date ATF. I recall this was one of the changes we made with regards to getting the size of memory. > - configs/octeontx_81xx_defconfig - I have several changes I want to > make here, but perhaps some of these would warrant a custom config for > my boards > - you assume there is only a SPI NOR flash for env which we > personally don't use. The env system supports multiple env types so we > could just enable MMC as well as SPI but then I find all the > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > defined a way for these to come from device-tree? We have not tested loading the environment from eMMC. It would be nice if the environment location could come from the device tree. > - you set loadaddr=040080000 which only makes sense for systems with > over 1GiB of DRAM... perhaps we should lower that to > loadaddr=020080000 for 1GiB systems (I don't think you can have less > than 1GiB?) > - I use DISTRO_DEFAULTS for a standard distro-friendly boot env... > I'm not sure why any board wouldn't do this these days and I think > that should be added > > I was able to functionally test mmc/i2c/gpio/pci/nic(BGX/RGX) and they > were all functioning well. > > When I enable SATA I find that it crashes on init: > GW6300-D1> sata info > Target spinup took 0 ms. > AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode > flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst > "Synchronous Abort" handler, esr 0x96000006 > elr: 000000000052c240 lr : 00000000005101bc (reloc) > elr: 000000003fecb240 lr : 000000003feaf1bc > x0 : 000000003be91380 x1 : 0000000000000000 > x2 : 0000000000000000 x3 : 000000003be9c100 > x4 : 0000000000000120 x5 : 000000003be9b800 > x6 : 0000000000000001 x7 : 0000000000000000 > x8 : 000000003ff46998 x9 : 0000000000000008 > x10: 000000003ff2e8c4 x11: 000000003ff2e8ca > x12: 000000003ff2e8cf x13: 000000003ff2e8d5 > x14: 000000003ff2e8da x15: 000000003ff2e8e0 > x16: 000000003ff2e8e6 x17: 000000003ff43362 > x18: 000000003be8ede0 x19: 0000000000000000 > x20: 000000003be9ab30 x21: 0000000000000002 > x22: 000000003be9ab30 x23: 0000000000000002 > x24: 000000003ff63aa4 x25: 000000003be9ab90 > x26: 0000000000000000 x27: 0000000000000000 > x28: 0000000000000000 x29: 000000003be881f0 > > Code: 928004a0 d65f03c0 f9400007 f94034e7 (f94008e7) > Resetting CPU ... > > I don't have NAND or SPI flash so can't test those. > > Best Regards, > > Tim NAND is not very common any more. Most boards use SPI flash, however. -Aaron
On Wed, Oct 30, 2019 at 5:04 PM Aaron Williams <awilliams@marvell.com> wrote: > > Hi Tim, > > I think I can answer some of your questions. > > On Wednesday, October 30, 2019 10:06:41 AM PDT Tim Harvey wrote: > > External Email > > > > ---------------------------------------------------------------------- > > > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> > wrote: > > > This series will add support for OcteonTX and OcteonTX2 processsor based > > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs > > > include support for CN96XX and CN95XX. > > > These SoC's have peripheral drivers based on PCI ECAM. > > > > > > Patches > > > [1 -10] Add requied changes to PCI framework > > > > > > - [6] Add support for multi-memory region range > > > - [7] EA in bridges > > > - [8] SR-IOV > > > > > > [12] Add driver model support for RTC DS1337 driver > > > [15 - 17] AHCI changes > > > [18 - 27] Add OcteonTX drivers > > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > Suneel, > > > > Thanks for submitting this series! > > > > I've applied and built this and am testing on the Gateworks Newport > > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > > found: > > - I get hung in the smc_call from smc_dram_size which your calling > > with the function id of 0xc2000301. The older U-Boot from the Cavium > > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > > a difference in our ATF version? > > ATF has indeed changed significantly. The current U-Boot requires an up-to- > date ATF. I recall this was one of the changes we made with regards to getting > the size of memory. What ATF should I be using? Is Marvell merging patches to the ATF required for OcteonTX? > > > - configs/octeontx_81xx_defconfig - I have several changes I want to > > make here, but perhaps some of these would warrant a custom config for > > my boards > > - you assume there is only a SPI NOR flash for env which we > > personally don't use. The env system supports multiple env types so we > > could just enable MMC as well as SPI but then I find all the > > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > > defined a way for these to come from device-tree? > > We have not tested loading the environment from eMMC. It would be nice if the > environment location could come from the device tree. I tested it and it works fine. The mmc-env partition, offset, and offset-redundant can be set via dts (doc/device-tree-bindings/config.txt and env/mmc.c) and I am setting these in my dts. I'll look into expanding this if necessary so that the defconfigs could just enable both SPI and MMC env and the dt will be able to dictate the details. Does the 'Octeon' support your working on overlap with 'OcteonTX'? Regards, Tim
Tim, You have to get the remaining parts of firmware from Marvell support site, there are no plans of upstream any other software. Aaron will add MIPS support to the code that is in the mainline, this will take some time. Chandra
Hi Tim, Thanks for testing the series. On Wed, Oct 30, 2019 at 10:06 AM Tim Harvey <tharvey@gateworks.com> wrote: > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > > > This series will add support for OcteonTX and OcteonTX2 processsor based > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > > support for CN96XX and CN95XX. > > These SoC's have peripheral drivers based on PCI ECAM. > > > > Patches > > [1 -10] Add requied changes to PCI framework > > - [6] Add support for multi-memory region range > > - [7] EA in bridges > > - [8] SR-IOV > > [12] Add driver model support for RTC DS1337 driver > > [15 - 17] AHCI changes > > [18 - 27] Add OcteonTX drivers > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > Suneel, > > Thanks for submitting this series! > > I've applied and built this and am testing on the Gateworks Newport > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > found: > - I get hung in the smc_call from smc_dram_size which your calling > with the function id of 0xc2000301. The older U-Boot from the Cavium > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > a difference in our ATF version? Yes, difference of ID values in latest ATF. > - configs/octeontx_81xx_defconfig - I have several changes I want to > make here, but perhaps some of these would warrant a custom config for > my boards > - you assume there is only a SPI NOR flash for env which we > personally don't use. The env system supports multiple env types so we > could just enable MMC as well as SPI but then I find all the > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > defined a way for these to come from device-tree? All of these can go into custom defconfig of gateway_xx_config. octeontx_81xx config targets base board. > - you set loadaddr=040080000 which only makes sense for systems with > over 1GiB of DRAM... perhaps we should lower that to > loadaddr=020080000 for 1GiB systems (I don't think you can have less > than 1GiB?) Will update this variable. > - I use DISTRO_DEFAULTS for a standard distro-friendly boot env... > I'm not sure why any board wouldn't do this these days and I think > that should be added Again this can go in custom config while I check internally if this can be added in default ocetontx_81xx. > > I was able to functionally test mmc/i2c/gpio/pci/nic(BGX/RGX) and they > were all functioning well. > > When I enable SATA I find that it crashes on init: > GW6300-D1> sata info > Target spinup took 0 ms. > AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode > flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst > "Synchronous Abort" handler, esr 0x96000006 > elr: 000000000052c240 lr : 00000000005101bc (reloc) > elr: 000000003fecb240 lr : 000000003feaf1bc > x0 : 000000003be91380 x1 : 0000000000000000 > x2 : 0000000000000000 x3 : 000000003be9c100 > x4 : 0000000000000120 x5 : 000000003be9b800 > x6 : 0000000000000001 x7 : 0000000000000000 > x8 : 000000003ff46998 x9 : 0000000000000008 > x10: 000000003ff2e8c4 x11: 000000003ff2e8ca > x12: 000000003ff2e8cf x13: 000000003ff2e8d5 > x14: 000000003ff2e8da x15: 000000003ff2e8e0 > x16: 000000003ff2e8e6 x17: 000000003ff43362 > x18: 000000003be8ede0 x19: 0000000000000000 > x20: 000000003be9ab30 x21: 0000000000000002 > x22: 000000003be9ab30 x23: 0000000000000002 > x24: 000000003ff63aa4 x25: 000000003be9ab90 > x26: 0000000000000000 x27: 0000000000000000 > x28: 0000000000000000 x29: 000000003be881f0 > > Code: 928004a0 d65f03c0 f9400007 f94034e7 (f94008e7) > Resetting CPU ... sata command is not enabled in octeontx_81xx, do you have custom changes? I re-checked scsi command on 81xx and did not see this issue. Regards, Suneel > > I don't have NAND or SPI flash so can't test those. > > Best Regards, > > Tim
On Thu, Oct 31, 2019 at 12:47 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > Hi Tim, > > Thanks for testing the series. > > On Wed, Oct 30, 2019 at 10:06 AM Tim Harvey <tharvey@gateworks.com> wrote: > > > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > > > > > This series will add support for OcteonTX and OcteonTX2 processsor based > > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > > > support for CN96XX and CN95XX. > > > These SoC's have peripheral drivers based on PCI ECAM. > > > > > > Patches > > > [1 -10] Add requied changes to PCI framework > > > - [6] Add support for multi-memory region range > > > - [7] EA in bridges > > > - [8] SR-IOV > > > [12] Add driver model support for RTC DS1337 driver > > > [15 - 17] AHCI changes > > > [18 - 27] Add OcteonTX drivers > > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > > > > Suneel, > > > > Thanks for submitting this series! > > > > I've applied and built this and am testing on the Gateworks Newport > > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > > found: > > - I get hung in the smc_call from smc_dram_size which your calling > > with the function id of 0xc2000301. The older U-Boot from the Cavium > > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > > a difference in our ATF version? > > Yes, difference of ID values in latest ATF. I'm told SDK-6-2.0-p3 is out of date so I'll work on finding the update and test again. > > > - configs/octeontx_81xx_defconfig - I have several changes I want to > > make here, but perhaps some of these would warrant a custom config for > > my boards > > - you assume there is only a SPI NOR flash for env which we > > personally don't use. The env system supports multiple env types so we > > could just enable MMC as well as SPI but then I find all the > > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > > defined a way for these to come from device-tree? > > All of these can go into custom defconfig of gateway_xx_config. > octeontx_81xx config targets base board. Correct these things could be put in a board-specific defconfig, but because 'octeontx_81xx' isn't a 'board' itself (it is a SoC platform) and it supports dt, a good goal would be to have it enable everything supported by the SoC and allow the details to come from dt. I'll help make that happen once we get basic support accepted. Really the only things I need to tweak for this defconfig to work on our boards is the location and details of the env and the configuration of the RGMII tx delay both of which I can submit patches for after your base support is accepted. > > > - you set loadaddr=040080000 which only makes sense for systems with > > over 1GiB of DRAM... perhaps we should lower that to > > loadaddr=020080000 for 1GiB systems (I don't think you can have less > > than 1GiB?) > Will update this variable. > > > - I use DISTRO_DEFAULTS for a standard distro-friendly boot env... > > I'm not sure why any board wouldn't do this these days and I think > > that should be added > > Again this can go in custom config while I check internally if this > can be added > in default ocetontx_81xx. > again, I don't see any reason to require a whole bunch of configs/octeontx_81xx_defconfig variants for a platform that relies on dt. Yes, it can easily be added to your patch with the following which allows easily booting distros like SUSE for example without mucking with your boot env: diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index 39c9fbc..076ca03 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -9,8 +9,10 @@ CONFIG_DEBUG_UART_BASE=0x87e028000000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 46134bb..b930e41 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -8,11 +8,19 @@ #ifndef __OCTEONTX_COMMON_H__ #define __OCTEONTX_COMMON_H__ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(SATA, sata, 0) + +#include <config_distro_bootcmd.h> +#endif + /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ -#define CONFIG_SUPPORT_RAW_INITRD - /** Maximum size of image supported for bootm (and bootable FIT images) */ #define CONFIG_SYS_BOOTM_LEN (256 << 20) @@ -60,8 +68,12 @@ /** Extra environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=040080000\0" \ - "autoload=0\0" + "loadaddr=020080000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x03000000\0" \ + "scriptaddr=0x04000000\0" \ + "autoload=0\0" \ + BOOTENV /** Environment defines */ #define CONFIG_ENV_SIZE 0x8000 Generic distro config was created to provide a specified set of bootloader env parameters and a well defined method for searching for bootscripts so that custom env's didn't need to be created for each board. See doc/README.distro for details > > > > > I was able to functionally test mmc/i2c/gpio/pci/nic(BGX/RGX) and they > > were all functioning well. > > > > When I enable SATA I find that it crashes on init: > > GW6300-D1> sata info > > Target spinup took 0 ms. > > AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode > > flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst > > "Synchronous Abort" handler, esr 0x96000006 > > elr: 000000000052c240 lr : 00000000005101bc (reloc) > > elr: 000000003fecb240 lr : 000000003feaf1bc > > x0 : 000000003be91380 x1 : 0000000000000000 > > x2 : 0000000000000000 x3 : 000000003be9c100 > > x4 : 0000000000000120 x5 : 000000003be9b800 > > x6 : 0000000000000001 x7 : 0000000000000000 > > x8 : 000000003ff46998 x9 : 0000000000000008 > > x10: 000000003ff2e8c4 x11: 000000003ff2e8ca > > x12: 000000003ff2e8cf x13: 000000003ff2e8d5 > > x14: 000000003ff2e8da x15: 000000003ff2e8e0 > > x16: 000000003ff2e8e6 x17: 000000003ff43362 > > x18: 000000003be8ede0 x19: 0000000000000000 > > x20: 000000003be9ab30 x21: 0000000000000002 > > x22: 000000003be9ab30 x23: 0000000000000002 > > x24: 000000003ff63aa4 x25: 000000003be9ab90 > > x26: 0000000000000000 x27: 0000000000000000 > > x28: 0000000000000000 x29: 000000003be881f0 > > > > Code: 928004a0 d65f03c0 f9400007 f94034e7 (f94008e7) > > Resetting CPU ... > sata command is not enabled in octeontx_81xx, do you have custom changes? > I re-checked scsi command on 81xx and did not see this issue. > Right, but AHCI is enabled and supported by the SoC and you include the driver for it in your patch series, thus you should enable using it (and thus be able to test it): diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index 39c9fbc..b2c2212 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y CONFIG_CMD_SF=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y Please enable it and see if you find the reason for the crash. Regards, Tim
Hi Tim, On Thu, Oct 31, 2019 at 3:14 PM Tim Harvey <tharvey@gateworks.com> wrote: > > On Thu, Oct 31, 2019 at 12:47 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > > > Hi Tim, > > > > Thanks for testing the series. > > > > On Wed, Oct 30, 2019 at 10:06 AM Tim Harvey <tharvey@gateworks.com> wrote: > > > > > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > > > > > > > This series will add support for OcteonTX and OcteonTX2 processsor based > > > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > > > > support for CN96XX and CN95XX. > > > > These SoC's have peripheral drivers based on PCI ECAM. > > > > > > > > Patches > > > > [1 -10] Add requied changes to PCI framework > > > > - [6] Add support for multi-memory region range > > > > - [7] EA in bridges > > > > - [8] SR-IOV > > > > [12] Add driver model support for RTC DS1337 driver > > > > [15 - 17] AHCI changes > > > > [18 - 27] Add OcteonTX drivers > > > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > > > > > > > Suneel, > > > > > > Thanks for submitting this series! > > > > > > I've applied and built this and am testing on the Gateworks Newport > > > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > > > found: > > > - I get hung in the smc_call from smc_dram_size which your calling > > > with the function id of 0xc2000301. The older U-Boot from the Cavium > > > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > > > a difference in our ATF version? > > > > Yes, difference of ID values in latest ATF. > > I'm told SDK-6-2.0-p3 is out of date so I'll work on finding the > update and test again. > > > > > > - configs/octeontx_81xx_defconfig - I have several changes I want to > > > make here, but perhaps some of these would warrant a custom config for > > > my boards > > > - you assume there is only a SPI NOR flash for env which we > > > personally don't use. The env system supports multiple env types so we > > > could just enable MMC as well as SPI but then I find all the > > > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > > > defined a way for these to come from device-tree? > > > > All of these can go into custom defconfig of gateway_xx_config. > > octeontx_81xx config targets base board. > > Correct these things could be put in a board-specific defconfig, but > because 'octeontx_81xx' isn't a 'board' itself (it is a SoC platform) > and it supports dt, a good goal would be to have it enable everything > supported by the SoC and allow the details to come from dt. > > I'll help make that happen once we get basic support accepted. Really > the only things I need to tweak for this defconfig to work on our > boards is the location and details of the env and the configuration of > the RGMII tx delay both of which I can submit patches for after your > base support is accepted. > > > > > > - you set loadaddr=040080000 which only makes sense for systems with > > > over 1GiB of DRAM... perhaps we should lower that to > > > loadaddr=020080000 for 1GiB systems (I don't think you can have less > > > than 1GiB?) > > Will update this variable. > > > > > - I use DISTRO_DEFAULTS for a standard distro-friendly boot env... > > > I'm not sure why any board wouldn't do this these days and I think > > > that should be added > > > > Again this can go in custom config while I check internally if this > > can be added > > in default ocetontx_81xx. > > > > again, I don't see any reason to require a whole bunch of > configs/octeontx_81xx_defconfig variants for a platform that relies on > dt. > > Yes, it can easily be added to your patch with the following which > allows easily booting distros like SUSE for example without mucking > with your boot env: > > diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig > index 39c9fbc..076ca03 100644 > --- a/configs/octeontx_81xx_defconfig > +++ b/configs/octeontx_81xx_defconfig > @@ -9,8 +9,10 @@ CONFIG_DEBUG_UART_BASE=0x87e028000000 > CONFIG_DEBUG_UART_CLOCK=24000000 > CONFIG_DEBUG_UART=y > CONFIG_AHCI=y > +CONFIG_DISTRO_DEFAULTS=y > CONFIG_FIT=y > CONFIG_FIT_SIGNATURE=y > +CONFIG_LEGACY_IMAGE_FORMAT=y > CONFIG_OF_BOARD_SETUP=y > CONFIG_BOOTDELAY=5 > CONFIG_USE_BOOTARGS=y > diff --git a/include/configs/octeontx_common.h > b/include/configs/octeontx_common.h > index 46134bb..b930e41 100644 > --- a/include/configs/octeontx_common.h > +++ b/include/configs/octeontx_common.h > @@ -8,11 +8,19 @@ > #ifndef __OCTEONTX_COMMON_H__ > #define __OCTEONTX_COMMON_H__ > > +#ifndef CONFIG_SPL_BUILD > +#define BOOT_TARGET_DEVICES(func) \ > + func(MMC, mmc, 0) \ > + func(MMC, mmc, 1) \ > + func(USB, usb, 0) \ > + func(SATA, sata, 0) > + > +#include <config_distro_bootcmd.h> > +#endif > + > /* Generic Timer Definitions */ > #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ > > -#define CONFIG_SUPPORT_RAW_INITRD > - > /** Maximum size of image supported for bootm (and bootable FIT images) */ > #define CONFIG_SYS_BOOTM_LEN (256 << 20) > > @@ -60,8 +68,12 @@ > > /** Extra environment settings */ > #define CONFIG_EXTRA_ENV_SETTINGS \ > - "loadaddr=040080000\0" \ > - "autoload=0\0" > + "loadaddr=020080000\0" \ > + "kernel_addr_r=0x02000000\0" \ > + "ramdisk_addr_r=0x03000000\0" \ > + "scriptaddr=0x04000000\0" \ > + "autoload=0\0" \ > + BOOTENV > > /** Environment defines */ > #define CONFIG_ENV_SIZE 0x8000 > > Generic distro config was created to provide a specified set of > bootloader env parameters and a well defined method for searching for > bootscripts so that custom env's didn't need to be created for each > board. > > See doc/README.distro for details > > > > > > > > > I was able to functionally test mmc/i2c/gpio/pci/nic(BGX/RGX) and they > > > were all functioning well. > > > > > > When I enable SATA I find that it crashes on init: > > > GW6300-D1> sata info > > > Target spinup took 0 ms. > > > AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode > > > flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst > > > "Synchronous Abort" handler, esr 0x96000006 > > > elr: 000000000052c240 lr : 00000000005101bc (reloc) > > > elr: 000000003fecb240 lr : 000000003feaf1bc > > > x0 : 000000003be91380 x1 : 0000000000000000 > > > x2 : 0000000000000000 x3 : 000000003be9c100 > > > x4 : 0000000000000120 x5 : 000000003be9b800 > > > x6 : 0000000000000001 x7 : 0000000000000000 > > > x8 : 000000003ff46998 x9 : 0000000000000008 > > > x10: 000000003ff2e8c4 x11: 000000003ff2e8ca > > > x12: 000000003ff2e8cf x13: 000000003ff2e8d5 > > > x14: 000000003ff2e8da x15: 000000003ff2e8e0 > > > x16: 000000003ff2e8e6 x17: 000000003ff43362 > > > x18: 000000003be8ede0 x19: 0000000000000000 > > > x20: 000000003be9ab30 x21: 0000000000000002 > > > x22: 000000003be9ab30 x23: 0000000000000002 > > > x24: 000000003ff63aa4 x25: 000000003be9ab90 > > > x26: 0000000000000000 x27: 0000000000000000 > > > x28: 0000000000000000 x29: 000000003be881f0 > > > > > > Code: 928004a0 d65f03c0 f9400007 f94034e7 (f94008e7) > > > Resetting CPU ... > > sata command is not enabled in octeontx_81xx, do you have custom changes? > > I re-checked scsi command on 81xx and did not see this issue. > > > > Right, but AHCI is enabled and supported by the SoC and you include > the driver for it in your patch series, thus you should enable using > it (and thus be able to test it): If you check 'dm tree' dump, ahci_pci/scsi are in use and not native ahci [relate to sata]. Hence scsi commands only will work. And this is correct as 81xx has AHCI on PCI. Regards, Suneel > > diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig > index 39c9fbc..b2c2212 100644 > --- a/configs/octeontx_81xx_defconfig > +++ b/configs/octeontx_81xx_defconfig > @@ -34,6 +34,7 @@ CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > CONFIG_CMD_PART=y > CONFIG_CMD_PCI=y > +CONFIG_CMD_SATA=y > CONFIG_CMD_SF=y > CONFIG_CMD_SF_TEST=y > CONFIG_CMD_USB=y > > Please enable it and see if you find the reason for the crash. > > Regards, > > Tim
On Thu, Oct 31, 2019 at 3:42 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > <snip> > > > > > > > > > > > I was able to functionally test mmc/i2c/gpio/pci/nic(BGX/RGX) and they > > > > were all functioning well. > > > > > > > > When I enable SATA I find that it crashes on init: > > > > GW6300-D1> sata info > > > > Target spinup took 0 ms. > > > > AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode > > > > flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst > > > > "Synchronous Abort" handler, esr 0x96000006 > > > > elr: 000000000052c240 lr : 00000000005101bc (reloc) > > > > elr: 000000003fecb240 lr : 000000003feaf1bc > > > > x0 : 000000003be91380 x1 : 0000000000000000 > > > > x2 : 0000000000000000 x3 : 000000003be9c100 > > > > x4 : 0000000000000120 x5 : 000000003be9b800 > > > > x6 : 0000000000000001 x7 : 0000000000000000 > > > > x8 : 000000003ff46998 x9 : 0000000000000008 > > > > x10: 000000003ff2e8c4 x11: 000000003ff2e8ca > > > > x12: 000000003ff2e8cf x13: 000000003ff2e8d5 > > > > x14: 000000003ff2e8da x15: 000000003ff2e8e0 > > > > x16: 000000003ff2e8e6 x17: 000000003ff43362 > > > > x18: 000000003be8ede0 x19: 0000000000000000 > > > > x20: 000000003be9ab30 x21: 0000000000000002 > > > > x22: 000000003be9ab30 x23: 0000000000000002 > > > > x24: 000000003ff63aa4 x25: 000000003be9ab90 > > > > x26: 0000000000000000 x27: 0000000000000000 > > > > x28: 0000000000000000 x29: 000000003be881f0 > > > > > > > > Code: 928004a0 d65f03c0 f9400007 f94034e7 (f94008e7) > > > > Resetting CPU ... > > > sata command is not enabled in octeontx_81xx, do you have custom changes? > > > I re-checked scsi command on 81xx and did not see this issue. > > > > > > > Right, but AHCI is enabled and supported by the SoC and you include > > the driver for it in your patch series, thus you should enable using > > it (and thus be able to test it): > > If you check 'dm tree' dump, ahci_pci/scsi are in use and not native > ahci [relate to sata]. > Hence scsi commands only will work. And this is correct as 81xx has AHCI on PCI. > Suneel, Thanks for the explanation. I tested and using the scsi command works great. I must admit I've been very confused as to why scsi here is used instead of sata. I understand SATA actually talks SCSI but why is dm enumerating it as scsi and not sata? Regards, Tim
Hi Tim, On Thursday, October 31, 2019 12:12:34 PM PST Tim Harvey wrote: > On Wed, Oct 30, 2019 at 5:04 PM Aaron Williams <awilliams@marvell.com> wrote: > > Hi Tim, > > > > I think I can answer some of your questions. > > > > On Wednesday, October 30, 2019 10:06:41 AM PDT Tim Harvey wrote: > > > External Email > > > > > > ---------------------------------------------------------------------- > > > > > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> > > > > wrote: > > > > This series will add support for OcteonTX and OcteonTX2 processsor > > > > based > > > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs > > > > include support for CN96XX and CN95XX. > > > > These SoC's have peripheral drivers based on PCI ECAM. > > > > > > > > Patches > > > > [1 -10] Add requied changes to PCI framework > > > > > > > > - [6] Add support for multi-memory region range > > > > - [7] EA in bridges > > > > - [8] SR-IOV > > > > > > > > [12] Add driver model support for RTC DS1337 driver > > > > [15 - 17] AHCI changes > > > > [18 - 27] Add OcteonTX drivers > > > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > > > Suneel, > > > > > > Thanks for submitting this series! > > > > > > I've applied and built this and am testing on the Gateworks Newport > > > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > > > found: > > > - I get hung in the smc_call from smc_dram_size which your calling > > > with the function id of 0xc2000301. The older U-Boot from the Cavium > > > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > > > a difference in our ATF version? > > > > ATF has indeed changed significantly. The current U-Boot requires an > > up-to- > > date ATF. I recall this was one of the changes we made with regards to > > getting the size of memory. > > What ATF should I be using? Is Marvell merging patches to the ATF > required for OcteonTX? > > > > - configs/octeontx_81xx_defconfig - I have several changes I want to > > > make here, but perhaps some of these would warrant a custom config for > > > my boards > > > > > > - you assume there is only a SPI NOR flash for env which we > > > > > > personally don't use. The env system supports multiple env types so we > > > could just enable MMC as well as SPI but then I find all the > > > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > > > defined a way for these to come from device-tree? > > > > We have not tested loading the environment from eMMC. It would be nice if > > the environment location could come from the device tree. > > I tested it and it works fine. > > The mmc-env partition, offset, and offset-redundant can be set via dts > (doc/device-tree-bindings/config.txt and env/mmc.c) and I am setting > these in my dts. I'll look into expanding this if necessary so that > the defconfigs could just enable both SPI and MMC env and the dt will > be able to dictate the details. > > Does the 'Octeon' support your working on overlap with 'OcteonTX'? Some of the Octeon support will leverage OcteonTX since some of the drivers are mostly compatible, such as eMMC, SPI and I2C. There is also a lot in Octeon that in the case of OcteonTX is handled by ATF and our BDK bootloader. In these cases there is no overlap. > > Regards, > > Tim Regards, Aaron
On Mon, Nov 4, 2019 at 5:09 PM Aaron Williams <awilliams@marvell.com> wrote: > > Hi Tim, > > On Thursday, October 31, 2019 12:12:34 PM PST Tim Harvey wrote: > > On Wed, Oct 30, 2019 at 5:04 PM Aaron Williams <awilliams@marvell.com> > wrote: > > > Hi Tim, > > > > > > I think I can answer some of your questions. > > > > > > On Wednesday, October 30, 2019 10:06:41 AM PDT Tim Harvey wrote: > > > > External Email > > > > > > > > ---------------------------------------------------------------------- > > > > > > > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> > > > > > > wrote: > > > > > This series will add support for OcteonTX and OcteonTX2 processsor > > > > > based > > > > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > > > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs > > > > > include support for CN96XX and CN95XX. > > > > > These SoC's have peripheral drivers based on PCI ECAM. > > > > > > > > > > Patches > > > > > [1 -10] Add requied changes to PCI framework > > > > > > > > > > - [6] Add support for multi-memory region range > > > > > - [7] EA in bridges > > > > > - [8] SR-IOV > > > > > > > > > > [12] Add driver model support for RTC DS1337 driver > > > > > [15 - 17] AHCI changes > > > > > [18 - 27] Add OcteonTX drivers > > > > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > > > > > Suneel, > > > > > > > > Thanks for submitting this series! > > > > > > > > I've applied and built this and am testing on the Gateworks Newport > > > > boards with the CN802x/CN803x (octeontx_81xx) and this is what I've > > > > found: > > > > - I get hung in the smc_call from smc_dram_size which your calling > > > > with the function id of 0xc2000301. The older U-Boot from the Cavium > > > > OcteonTX SDK-6.2.0-p3 used 0x43000301 and this works for me. Is there > > > > a difference in our ATF version? > > > > > > ATF has indeed changed significantly. The current U-Boot requires an > > > up-to- > > > date ATF. I recall this was one of the changes we made with regards to > > > getting the size of memory. > > > > What ATF should I be using? Is Marvell merging patches to the ATF > > required for OcteonTX? > > > > > > - configs/octeontx_81xx_defconfig - I have several changes I want to > > > > make here, but perhaps some of these would warrant a custom config for > > > > my boards > > > > > > > > - you assume there is only a SPI NOR flash for env which we > > > > > > > > personally don't use. The env system supports multiple env types so we > > > > could just enable MMC as well as SPI but then I find all the > > > > hard-coded CONFIG_ENV_* defines restrictive. I wonder if anyone has > > > > defined a way for these to come from device-tree? > > > > > > We have not tested loading the environment from eMMC. It would be nice if > > > the environment location could come from the device tree. > > > > I tested it and it works fine. > > > > The mmc-env partition, offset, and offset-redundant can be set via dts > > (doc/device-tree-bindings/config.txt and env/mmc.c) and I am setting > > these in my dts. I'll look into expanding this if necessary so that > > the defconfigs could just enable both SPI and MMC env and the dt will > > be able to dictate the details. > > > > Does the 'Octeon' support your working on overlap with 'OcteonTX'? > > Some of the Octeon support will leverage OcteonTX since some of the drivers > are mostly compatible, such as eMMC, SPI and I2C. There is also a lot in > Octeon that in the case of OcteonTX is handled by ATF and our BDK bootloader. > In these cases there is no overlap. > Aaron, Thanks for the clarification. It sounds like you are working on SPL for Octeon which I was hoping could perhaps also support OcteonTX at some point. I had high hopes of adding SPL support for OcteonTX for our boards but ended up not having the time to work through it and in the end just used the BDK. This makes for an extremely long boot time (about 10 seconds just to get to U-Boot unfortunately). Regards, Tim
On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > This series will add support for OcteonTX and OcteonTX2 processsor based > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > support for CN96XX and CN95XX. > These SoC's have peripheral drivers based on PCI ECAM. > > Patches > [1 -10] Add requied changes to PCI framework > - [6] Add support for multi-memory region range > - [7] EA in bridges > - [8] SR-IOV > [12] Add driver model support for RTC DS1337 driver > [15 - 17] AHCI changes > [18 - 27] Add OcteonTX drivers > [28 - 29] Add OcteonTX/TX2 board files and configurations > > Suneel Garapati (29): > include: pci_ids: add vendor ID for Cavium > include: pci: Increase max pci region limit > fdtdec: add API to read pci bus-range property > drivers: pci-uclass: fix incorrect argument in map_sysmem > drivers: pci-uclass: make DT subnode parse optional > drivers: pci-uclass: add multi entry support for pci regions > drivers: pci-uclass: add support for Enhanced Allocation in Bridges > drivers: pci-uclass: add support for Single-Root I/O Virtualizaiton > drivers: pci-uclass: add VF map_bar support for Enhanced Allocation > drivers: pci-uclass: Add support for Alternate-RoutingID capability > include: arm: asm: io: add 64bit clrbits and setbits helpers > drivers: rtc: ds1337: add driver model support > arch: include: octeontx: add headers for OcteonTX > arch: include: octeontx2: add headers for OcteonTX2 > drivers: ata: ahci: update max id if it is more than available ports > drivers: ata: ahci: fill upper 32bit buffer address in sg descriptor > drivers: ata: ahci: add BAR index quirk for OcteonTX > drivers: pci: add PCI controller driver for OcteonTX > drivers: gpio: add GPIO controller driver for OcteonTX > drivers: i2c: add I2C controller driver for OcteonTX > drivers: spi: add SPI controller driver for OcteonTX > drivers: mmc: remove static qualifier on mmc_power_init > drivers: mmc: add MMC controller driver for OcteonTX > drivers: mtd: nand: add NAND controller driver for OcteonTX > drivers: net: add NIC controller driver for OcteonTX > drivers: net: add NIC controller driver for OcteonTX2 > drivers: watchdog: add reset support for OcteonTX > octeontx: Add support for OcteonTX SoC platforms > octeontx2: Add support for OcteonTX2 SoC platforms > > arch/arm/Kconfig | 22 + > arch/arm/Makefile | 2 + > arch/arm/include/asm/arch-octeontx/board.h | 121 + > arch/arm/include/asm/arch-octeontx/clock.h | 25 + > .../asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 ++ > .../include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 + > arch/arm/include/asm/arch-octeontx/gpio.h | 6 + > arch/arm/include/asm/arch-octeontx/smc.h | 20 + > arch/arm/include/asm/arch-octeontx/soc.h | 31 + > arch/arm/include/asm/arch-octeontx2/board.h | 123 + > arch/arm/include/asm/arch-octeontx2/clock.h | 24 + > .../asm/arch-octeontx2/csrs/csrs-cgx.h | 7835 ++++++++++++ > .../asm/arch-octeontx2/csrs/csrs-lmt.h | 60 + > .../asm/arch-octeontx2/csrs/csrs-mio_emm.h | 1193 ++ > .../asm/arch-octeontx2/csrs/csrs-nix.h | 10482 ++++++++++++++++ > .../asm/arch-octeontx2/csrs/csrs-npa.h | 2296 ++++ > .../asm/arch-octeontx2/csrs/csrs-npc.h | 1930 +++ > .../asm/arch-octeontx2/csrs/csrs-rvu.h | 2430 ++++ > arch/arm/include/asm/arch-octeontx2/gpio.h | 6 + > arch/arm/include/asm/arch-octeontx2/smc-id.h | 32 + > arch/arm/include/asm/arch-octeontx2/smc.h | 18 + > arch/arm/include/asm/arch-octeontx2/soc.h | 31 + > arch/arm/include/asm/io.h | 8 + > arch/arm/mach-octeontx/Kconfig | 23 + > arch/arm/mach-octeontx/Makefile | 9 + > arch/arm/mach-octeontx/clock.c | 35 + > arch/arm/mach-octeontx/cpu.c | 76 + > arch/arm/mach-octeontx/lowlevel_init.S | 33 + > arch/arm/mach-octeontx2/Kconfig | 23 + > arch/arm/mach-octeontx2/Makefile | 9 + > arch/arm/mach-octeontx2/clock.c | 35 + > arch/arm/mach-octeontx2/config.mk | 4 + > arch/arm/mach-octeontx2/cpu.c | 72 + > arch/arm/mach-octeontx2/lowlevel_init.S | 33 + > board/Marvell/octeontx/Kconfig | 14 + > board/Marvell/octeontx/MAINTAINERS | 9 + > board/Marvell/octeontx/Makefile | 9 + > board/Marvell/octeontx/board-fdt.c | 271 + > board/Marvell/octeontx/board.c | 137 + > board/Marvell/octeontx/smc.c | 30 + > board/Marvell/octeontx/soc-utils.c | 53 + > board/Marvell/octeontx2/Kconfig | 15 + > board/Marvell/octeontx2/MAINTAINERS | 9 + > board/Marvell/octeontx2/Makefile | 9 + > board/Marvell/octeontx2/board-fdt.c | 155 + > board/Marvell/octeontx2/board.c | 232 + > board/Marvell/octeontx2/smc.c | 62 + > board/Marvell/octeontx2/soc-utils.c | 49 + > configs/octeontx2_95xx_defconfig | 105 + > configs/octeontx2_96xx_defconfig | 131 + > configs/octeontx_81xx_defconfig | 133 + > configs/octeontx_83xx_defconfig | 130 + > drivers/ata/ahci.c | 15 + > drivers/gpio/Kconfig | 7 + > drivers/gpio/Makefile | 1 + > drivers/gpio/octeontx_gpio.c | 218 + > drivers/i2c/Kconfig | 7 + > drivers/i2c/Makefile | 1 + > drivers/i2c/octeontx_i2c.c | 968 ++ > drivers/mmc/Kconfig | 9 + > drivers/mmc/Makefile | 1 + > drivers/mmc/mmc.c | 2 +- > drivers/mmc/octeontx_hsmmc.c | 3233 +++++ > drivers/mmc/octeontx_hsmmc.h | 191 + > drivers/mtd/nand/raw/Kconfig | 16 + > drivers/mtd/nand/raw/Makefile | 2 + > drivers/mtd/nand/raw/octeontx_bch.c | 424 + > drivers/mtd/nand/raw/octeontx_bch.h | 142 + > drivers/mtd/nand/raw/octeontx_bch_regs.h | 169 + > drivers/mtd/nand/raw/octeontx_nand.c | 2261 ++++ > drivers/net/Kconfig | 29 + > drivers/net/Makefile | 4 + > drivers/net/octeontx/Makefile | 9 + > drivers/net/octeontx/bgx.c | 1546 +++ > drivers/net/octeontx/bgx.h | 259 + > drivers/net/octeontx/nic.h | 518 + > drivers/net/octeontx/nic_main.c | 777 ++ > drivers/net/octeontx/nic_reg.h | 252 + > drivers/net/octeontx/nicvf_main.c | 575 + > drivers/net/octeontx/nicvf_queues.c | 1141 ++ > drivers/net/octeontx/nicvf_queues.h | 355 + > drivers/net/octeontx/q_struct.h | 697 + > drivers/net/octeontx/smi.c | 382 + > drivers/net/octeontx/xcv.c | 129 + > drivers/net/octeontx2/Makefile | 11 + > drivers/net/octeontx2/cgx.c | 297 + > drivers/net/octeontx2/cgx.h | 105 + > drivers/net/octeontx2/cgx_intf.c | 421 + > drivers/net/octeontx2/cgx_intf.h | 370 + > drivers/net/octeontx2/lmt.h | 51 + > drivers/net/octeontx2/nix.c | 824 ++ > drivers/net/octeontx2/nix.h | 355 + > drivers/net/octeontx2/nix_af.c | 1103 ++ > drivers/net/octeontx2/npc.h | 92 + > drivers/net/octeontx2/rvu.h | 127 + > drivers/net/octeontx2/rvu_af.c | 172 + > drivers/net/octeontx2/rvu_common.c | 74 + > drivers/net/octeontx2/rvu_pf.c | 118 + > drivers/pci/Kconfig | 17 + > drivers/pci/Makefile | 1 + > drivers/pci/pci-uclass.c | 211 +- > drivers/pci/pci_octeontx.c | 538 + > drivers/rtc/Kconfig | 7 + > drivers/rtc/ds1337.c | 170 + > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/octeontx_spi.c | 750 ++ > drivers/watchdog/Kconfig | 10 + > drivers/watchdog/Makefile | 1 + > drivers/watchdog/octeontx_wdt.c | 76 + > include/configs/octeontx2_95xx.h | 80 + > include/configs/octeontx2_96xx.h | 90 + > include/configs/octeontx_common.h | 98 + > include/fdtdec.h | 12 + > include/mmc.h | 1 + > include/pci.h | 23 +- > include/pci_ids.h | 2 + > lib/fdtdec.c | 16 + > 118 files changed, 50774 insertions(+), 17 deletions(-) > create mode 100644 arch/arm/include/asm/arch-octeontx/board.h > create mode 100644 arch/arm/include/asm/arch-octeontx/clock.h > create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h > create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h > create mode 100644 arch/arm/include/asm/arch-octeontx/gpio.h > create mode 100644 arch/arm/include/asm/arch-octeontx/smc.h > create mode 100644 arch/arm/include/asm/arch-octeontx/soc.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/board.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/clock.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/gpio.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/smc-id.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/smc.h > create mode 100644 arch/arm/include/asm/arch-octeontx2/soc.h > create mode 100644 arch/arm/mach-octeontx/Kconfig > create mode 100644 arch/arm/mach-octeontx/Makefile > create mode 100644 arch/arm/mach-octeontx/clock.c > create mode 100644 arch/arm/mach-octeontx/cpu.c > create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S > create mode 100644 arch/arm/mach-octeontx2/Kconfig > create mode 100644 arch/arm/mach-octeontx2/Makefile > create mode 100644 arch/arm/mach-octeontx2/clock.c > create mode 100644 arch/arm/mach-octeontx2/config.mk > create mode 100644 arch/arm/mach-octeontx2/cpu.c > create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S > create mode 100644 board/Marvell/octeontx/Kconfig > create mode 100644 board/Marvell/octeontx/MAINTAINERS > create mode 100644 board/Marvell/octeontx/Makefile > create mode 100644 board/Marvell/octeontx/board-fdt.c > create mode 100644 board/Marvell/octeontx/board.c > create mode 100644 board/Marvell/octeontx/smc.c > create mode 100644 board/Marvell/octeontx/soc-utils.c > create mode 100644 board/Marvell/octeontx2/Kconfig > create mode 100644 board/Marvell/octeontx2/MAINTAINERS > create mode 100644 board/Marvell/octeontx2/Makefile > create mode 100644 board/Marvell/octeontx2/board-fdt.c > create mode 100644 board/Marvell/octeontx2/board.c > create mode 100644 board/Marvell/octeontx2/smc.c > create mode 100644 board/Marvell/octeontx2/soc-utils.c > create mode 100644 configs/octeontx2_95xx_defconfig > create mode 100644 configs/octeontx2_96xx_defconfig > create mode 100644 configs/octeontx_81xx_defconfig > create mode 100644 configs/octeontx_83xx_defconfig > create mode 100644 drivers/gpio/octeontx_gpio.c > create mode 100644 drivers/i2c/octeontx_i2c.c > create mode 100644 drivers/mmc/octeontx_hsmmc.c > create mode 100644 drivers/mmc/octeontx_hsmmc.h > create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c > create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h > create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h > create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c > create mode 100644 drivers/net/octeontx/Makefile > create mode 100644 drivers/net/octeontx/bgx.c > create mode 100644 drivers/net/octeontx/bgx.h > create mode 100644 drivers/net/octeontx/nic.h > create mode 100644 drivers/net/octeontx/nic_main.c > create mode 100644 drivers/net/octeontx/nic_reg.h > create mode 100644 drivers/net/octeontx/nicvf_main.c > create mode 100644 drivers/net/octeontx/nicvf_queues.c > create mode 100644 drivers/net/octeontx/nicvf_queues.h > create mode 100644 drivers/net/octeontx/q_struct.h > create mode 100644 drivers/net/octeontx/smi.c > create mode 100644 drivers/net/octeontx/xcv.c > create mode 100644 drivers/net/octeontx2/Makefile > create mode 100644 drivers/net/octeontx2/cgx.c > create mode 100644 drivers/net/octeontx2/cgx.h > create mode 100644 drivers/net/octeontx2/cgx_intf.c > create mode 100644 drivers/net/octeontx2/cgx_intf.h > create mode 100644 drivers/net/octeontx2/lmt.h > create mode 100644 drivers/net/octeontx2/nix.c > create mode 100644 drivers/net/octeontx2/nix.h > create mode 100644 drivers/net/octeontx2/nix_af.c > create mode 100644 drivers/net/octeontx2/npc.h > create mode 100644 drivers/net/octeontx2/rvu.h > create mode 100644 drivers/net/octeontx2/rvu_af.c > create mode 100644 drivers/net/octeontx2/rvu_common.c > create mode 100644 drivers/net/octeontx2/rvu_pf.c > create mode 100644 drivers/pci/pci_octeontx.c > create mode 100644 drivers/spi/octeontx_spi.c > create mode 100644 drivers/watchdog/octeontx_wdt.c > create mode 100644 include/configs/octeontx2_95xx.h > create mode 100644 include/configs/octeontx2_96xx.h > create mode 100644 include/configs/octeontx_common.h > > -- > 2.23.0 > Tom, I haven't seen any reviews or comments of any of Suneel's patch series here other than the testing I performed. What are the next steps in being able to get this code merged? The patches to pci-uclass are perhaps the only ones that would even affect other boards as pretty much everything else is adding a new driver. Regards, Tim
Hi Tim, On Tue, 19 Nov 2019 at 10:55, Tim Harvey <tharvey@gateworks.com> wrote: > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > > > This series will add support for OcteonTX and OcteonTX2 processsor based > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > > support for CN96XX and CN95XX. > > These SoC's have peripheral drivers based on PCI ECAM. > > > > Patches > > [1 -10] Add requied changes to PCI framework > > - [6] Add support for multi-memory region range > > - [7] EA in bridges > > - [8] SR-IOV > > [12] Add driver model support for RTC DS1337 driver > > [15 - 17] AHCI changes > > [18 - 27] Add OcteonTX drivers > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > Suneel Garapati (29): > > include: pci_ids: add vendor ID for Cavium > > include: pci: Increase max pci region limit > > fdtdec: add API to read pci bus-range property > > drivers: pci-uclass: fix incorrect argument in map_sysmem > > drivers: pci-uclass: make DT subnode parse optional > > drivers: pci-uclass: add multi entry support for pci regions > > drivers: pci-uclass: add support for Enhanced Allocation in Bridges > > drivers: pci-uclass: add support for Single-Root I/O Virtualizaiton > > drivers: pci-uclass: add VF map_bar support for Enhanced Allocation > > drivers: pci-uclass: Add support for Alternate-RoutingID capability > > include: arm: asm: io: add 64bit clrbits and setbits helpers > > drivers: rtc: ds1337: add driver model support > > arch: include: octeontx: add headers for OcteonTX > > arch: include: octeontx2: add headers for OcteonTX2 > > drivers: ata: ahci: update max id if it is more than available ports > > drivers: ata: ahci: fill upper 32bit buffer address in sg descriptor > > drivers: ata: ahci: add BAR index quirk for OcteonTX > > drivers: pci: add PCI controller driver for OcteonTX > > drivers: gpio: add GPIO controller driver for OcteonTX > > drivers: i2c: add I2C controller driver for OcteonTX > > drivers: spi: add SPI controller driver for OcteonTX > > drivers: mmc: remove static qualifier on mmc_power_init > > drivers: mmc: add MMC controller driver for OcteonTX > > drivers: mtd: nand: add NAND controller driver for OcteonTX > > drivers: net: add NIC controller driver for OcteonTX > > drivers: net: add NIC controller driver for OcteonTX2 > > drivers: watchdog: add reset support for OcteonTX > > octeontx: Add support for OcteonTX SoC platforms > > octeontx2: Add support for OcteonTX2 SoC platforms > > > > arch/arm/Kconfig | 22 + > > arch/arm/Makefile | 2 + > > arch/arm/include/asm/arch-octeontx/board.h | 121 + > > arch/arm/include/asm/arch-octeontx/clock.h | 25 + > > .../asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 ++ > > .../include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 + > > arch/arm/include/asm/arch-octeontx/gpio.h | 6 + > > arch/arm/include/asm/arch-octeontx/smc.h | 20 + > > arch/arm/include/asm/arch-octeontx/soc.h | 31 + > > arch/arm/include/asm/arch-octeontx2/board.h | 123 + > > arch/arm/include/asm/arch-octeontx2/clock.h | 24 + > > .../asm/arch-octeontx2/csrs/csrs-cgx.h | 7835 ++++++++++++ > > .../asm/arch-octeontx2/csrs/csrs-lmt.h | 60 + > > .../asm/arch-octeontx2/csrs/csrs-mio_emm.h | 1193 ++ > > .../asm/arch-octeontx2/csrs/csrs-nix.h | 10482 ++++++++++++++++ > > .../asm/arch-octeontx2/csrs/csrs-npa.h | 2296 ++++ > > .../asm/arch-octeontx2/csrs/csrs-npc.h | 1930 +++ > > .../asm/arch-octeontx2/csrs/csrs-rvu.h | 2430 ++++ > > arch/arm/include/asm/arch-octeontx2/gpio.h | 6 + > > arch/arm/include/asm/arch-octeontx2/smc-id.h | 32 + > > arch/arm/include/asm/arch-octeontx2/smc.h | 18 + > > arch/arm/include/asm/arch-octeontx2/soc.h | 31 + > > arch/arm/include/asm/io.h | 8 + > > arch/arm/mach-octeontx/Kconfig | 23 + > > arch/arm/mach-octeontx/Makefile | 9 + > > arch/arm/mach-octeontx/clock.c | 35 + > > arch/arm/mach-octeontx/cpu.c | 76 + > > arch/arm/mach-octeontx/lowlevel_init.S | 33 + > > arch/arm/mach-octeontx2/Kconfig | 23 + > > arch/arm/mach-octeontx2/Makefile | 9 + > > arch/arm/mach-octeontx2/clock.c | 35 + > > arch/arm/mach-octeontx2/config.mk | 4 + > > arch/arm/mach-octeontx2/cpu.c | 72 + > > arch/arm/mach-octeontx2/lowlevel_init.S | 33 + > > board/Marvell/octeontx/Kconfig | 14 + > > board/Marvell/octeontx/MAINTAINERS | 9 + > > board/Marvell/octeontx/Makefile | 9 + > > board/Marvell/octeontx/board-fdt.c | 271 + > > board/Marvell/octeontx/board.c | 137 + > > board/Marvell/octeontx/smc.c | 30 + > > board/Marvell/octeontx/soc-utils.c | 53 + > > board/Marvell/octeontx2/Kconfig | 15 + > > board/Marvell/octeontx2/MAINTAINERS | 9 + > > board/Marvell/octeontx2/Makefile | 9 + > > board/Marvell/octeontx2/board-fdt.c | 155 + > > board/Marvell/octeontx2/board.c | 232 + > > board/Marvell/octeontx2/smc.c | 62 + > > board/Marvell/octeontx2/soc-utils.c | 49 + > > configs/octeontx2_95xx_defconfig | 105 + > > configs/octeontx2_96xx_defconfig | 131 + > > configs/octeontx_81xx_defconfig | 133 + > > configs/octeontx_83xx_defconfig | 130 + > > drivers/ata/ahci.c | 15 + > > drivers/gpio/Kconfig | 7 + > > drivers/gpio/Makefile | 1 + > > drivers/gpio/octeontx_gpio.c | 218 + > > drivers/i2c/Kconfig | 7 + > > drivers/i2c/Makefile | 1 + > > drivers/i2c/octeontx_i2c.c | 968 ++ > > drivers/mmc/Kconfig | 9 + > > drivers/mmc/Makefile | 1 + > > drivers/mmc/mmc.c | 2 +- > > drivers/mmc/octeontx_hsmmc.c | 3233 +++++ > > drivers/mmc/octeontx_hsmmc.h | 191 + > > drivers/mtd/nand/raw/Kconfig | 16 + > > drivers/mtd/nand/raw/Makefile | 2 + > > drivers/mtd/nand/raw/octeontx_bch.c | 424 + > > drivers/mtd/nand/raw/octeontx_bch.h | 142 + > > drivers/mtd/nand/raw/octeontx_bch_regs.h | 169 + > > drivers/mtd/nand/raw/octeontx_nand.c | 2261 ++++ > > drivers/net/Kconfig | 29 + > > drivers/net/Makefile | 4 + > > drivers/net/octeontx/Makefile | 9 + > > drivers/net/octeontx/bgx.c | 1546 +++ > > drivers/net/octeontx/bgx.h | 259 + > > drivers/net/octeontx/nic.h | 518 + > > drivers/net/octeontx/nic_main.c | 777 ++ > > drivers/net/octeontx/nic_reg.h | 252 + > > drivers/net/octeontx/nicvf_main.c | 575 + > > drivers/net/octeontx/nicvf_queues.c | 1141 ++ > > drivers/net/octeontx/nicvf_queues.h | 355 + > > drivers/net/octeontx/q_struct.h | 697 + > > drivers/net/octeontx/smi.c | 382 + > > drivers/net/octeontx/xcv.c | 129 + > > drivers/net/octeontx2/Makefile | 11 + > > drivers/net/octeontx2/cgx.c | 297 + > > drivers/net/octeontx2/cgx.h | 105 + > > drivers/net/octeontx2/cgx_intf.c | 421 + > > drivers/net/octeontx2/cgx_intf.h | 370 + > > drivers/net/octeontx2/lmt.h | 51 + > > drivers/net/octeontx2/nix.c | 824 ++ > > drivers/net/octeontx2/nix.h | 355 + > > drivers/net/octeontx2/nix_af.c | 1103 ++ > > drivers/net/octeontx2/npc.h | 92 + > > drivers/net/octeontx2/rvu.h | 127 + > > drivers/net/octeontx2/rvu_af.c | 172 + > > drivers/net/octeontx2/rvu_common.c | 74 + > > drivers/net/octeontx2/rvu_pf.c | 118 + > > drivers/pci/Kconfig | 17 + > > drivers/pci/Makefile | 1 + > > drivers/pci/pci-uclass.c | 211 +- > > drivers/pci/pci_octeontx.c | 538 + > > drivers/rtc/Kconfig | 7 + > > drivers/rtc/ds1337.c | 170 + > > drivers/spi/Kconfig | 6 + > > drivers/spi/Makefile | 1 + > > drivers/spi/octeontx_spi.c | 750 ++ > > drivers/watchdog/Kconfig | 10 + > > drivers/watchdog/Makefile | 1 + > > drivers/watchdog/octeontx_wdt.c | 76 + > > include/configs/octeontx2_95xx.h | 80 + > > include/configs/octeontx2_96xx.h | 90 + > > include/configs/octeontx_common.h | 98 + > > include/fdtdec.h | 12 + > > include/mmc.h | 1 + > > include/pci.h | 23 +- > > include/pci_ids.h | 2 + > > lib/fdtdec.c | 16 + > > 118 files changed, 50774 insertions(+), 17 deletions(-) > > create mode 100644 arch/arm/include/asm/arch-octeontx/board.h > > create mode 100644 arch/arm/include/asm/arch-octeontx/clock.h > > create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h > > create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h > > create mode 100644 arch/arm/include/asm/arch-octeontx/gpio.h > > create mode 100644 arch/arm/include/asm/arch-octeontx/smc.h > > create mode 100644 arch/arm/include/asm/arch-octeontx/soc.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/board.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/clock.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/gpio.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/smc-id.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/smc.h > > create mode 100644 arch/arm/include/asm/arch-octeontx2/soc.h > > create mode 100644 arch/arm/mach-octeontx/Kconfig > > create mode 100644 arch/arm/mach-octeontx/Makefile > > create mode 100644 arch/arm/mach-octeontx/clock.c > > create mode 100644 arch/arm/mach-octeontx/cpu.c > > create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S > > create mode 100644 arch/arm/mach-octeontx2/Kconfig > > create mode 100644 arch/arm/mach-octeontx2/Makefile > > create mode 100644 arch/arm/mach-octeontx2/clock.c > > create mode 100644 arch/arm/mach-octeontx2/config.mk > > create mode 100644 arch/arm/mach-octeontx2/cpu.c > > create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S > > create mode 100644 board/Marvell/octeontx/Kconfig > > create mode 100644 board/Marvell/octeontx/MAINTAINERS > > create mode 100644 board/Marvell/octeontx/Makefile > > create mode 100644 board/Marvell/octeontx/board-fdt.c > > create mode 100644 board/Marvell/octeontx/board.c > > create mode 100644 board/Marvell/octeontx/smc.c > > create mode 100644 board/Marvell/octeontx/soc-utils.c > > create mode 100644 board/Marvell/octeontx2/Kconfig > > create mode 100644 board/Marvell/octeontx2/MAINTAINERS > > create mode 100644 board/Marvell/octeontx2/Makefile > > create mode 100644 board/Marvell/octeontx2/board-fdt.c > > create mode 100644 board/Marvell/octeontx2/board.c > > create mode 100644 board/Marvell/octeontx2/smc.c > > create mode 100644 board/Marvell/octeontx2/soc-utils.c > > create mode 100644 configs/octeontx2_95xx_defconfig > > create mode 100644 configs/octeontx2_96xx_defconfig > > create mode 100644 configs/octeontx_81xx_defconfig > > create mode 100644 configs/octeontx_83xx_defconfig > > create mode 100644 drivers/gpio/octeontx_gpio.c > > create mode 100644 drivers/i2c/octeontx_i2c.c > > create mode 100644 drivers/mmc/octeontx_hsmmc.c > > create mode 100644 drivers/mmc/octeontx_hsmmc.h > > create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c > > create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h > > create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h > > create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c > > create mode 100644 drivers/net/octeontx/Makefile > > create mode 100644 drivers/net/octeontx/bgx.c > > create mode 100644 drivers/net/octeontx/bgx.h > > create mode 100644 drivers/net/octeontx/nic.h > > create mode 100644 drivers/net/octeontx/nic_main.c > > create mode 100644 drivers/net/octeontx/nic_reg.h > > create mode 100644 drivers/net/octeontx/nicvf_main.c > > create mode 100644 drivers/net/octeontx/nicvf_queues.c > > create mode 100644 drivers/net/octeontx/nicvf_queues.h > > create mode 100644 drivers/net/octeontx/q_struct.h > > create mode 100644 drivers/net/octeontx/smi.c > > create mode 100644 drivers/net/octeontx/xcv.c > > create mode 100644 drivers/net/octeontx2/Makefile > > create mode 100644 drivers/net/octeontx2/cgx.c > > create mode 100644 drivers/net/octeontx2/cgx.h > > create mode 100644 drivers/net/octeontx2/cgx_intf.c > > create mode 100644 drivers/net/octeontx2/cgx_intf.h > > create mode 100644 drivers/net/octeontx2/lmt.h > > create mode 100644 drivers/net/octeontx2/nix.c > > create mode 100644 drivers/net/octeontx2/nix.h > > create mode 100644 drivers/net/octeontx2/nix_af.c > > create mode 100644 drivers/net/octeontx2/npc.h > > create mode 100644 drivers/net/octeontx2/rvu.h > > create mode 100644 drivers/net/octeontx2/rvu_af.c > > create mode 100644 drivers/net/octeontx2/rvu_common.c > > create mode 100644 drivers/net/octeontx2/rvu_pf.c > > create mode 100644 drivers/pci/pci_octeontx.c > > create mode 100644 drivers/spi/octeontx_spi.c > > create mode 100644 drivers/watchdog/octeontx_wdt.c > > create mode 100644 include/configs/octeontx2_95xx.h > > create mode 100644 include/configs/octeontx2_96xx.h > > create mode 100644 include/configs/octeontx_common.h > > > > -- > > 2.23.0 > > > > Tom, > > I haven't seen any reviews or comments of any of Suneel's patch series > here other than the testing I performed. > > What are the next steps in being able to get this code merged? The > patches to pci-uclass are perhaps the only ones that would even affect > other boards as pretty much everything else is adding a new driver. I've spent a bit of time looking at these. Some are OK but some need a little work. Regards, Simon
On Tue, Nov 19, 2019 at 07:00:58PM -0800, Simon Glass wrote: > Hi Tim, > > On Tue, 19 Nov 2019 at 10:55, Tim Harvey <tharvey@gateworks.com> wrote: > > > > On Tue, Oct 29, 2019 at 2:08 PM Suneel Garapati <suneelglinux@gmail.com> wrote: > > > > > > This series will add support for OcteonTX and OcteonTX2 processsor based > > > platforms. The Marvell/Cavium Octeon-TX 64-bit ARM based SoCs include > > > the CN80XX, CN81XX and CN83XX while Octeon-TX2 64-bit ARM based SoCs include > > > support for CN96XX and CN95XX. > > > These SoC's have peripheral drivers based on PCI ECAM. > > > > > > Patches > > > [1 -10] Add requied changes to PCI framework > > > - [6] Add support for multi-memory region range > > > - [7] EA in bridges > > > - [8] SR-IOV > > > [12] Add driver model support for RTC DS1337 driver > > > [15 - 17] AHCI changes > > > [18 - 27] Add OcteonTX drivers > > > [28 - 29] Add OcteonTX/TX2 board files and configurations > > > > > > Suneel Garapati (29): > > > include: pci_ids: add vendor ID for Cavium > > > include: pci: Increase max pci region limit > > > fdtdec: add API to read pci bus-range property > > > drivers: pci-uclass: fix incorrect argument in map_sysmem > > > drivers: pci-uclass: make DT subnode parse optional > > > drivers: pci-uclass: add multi entry support for pci regions > > > drivers: pci-uclass: add support for Enhanced Allocation in Bridges > > > drivers: pci-uclass: add support for Single-Root I/O Virtualizaiton > > > drivers: pci-uclass: add VF map_bar support for Enhanced Allocation > > > drivers: pci-uclass: Add support for Alternate-RoutingID capability > > > include: arm: asm: io: add 64bit clrbits and setbits helpers > > > drivers: rtc: ds1337: add driver model support > > > arch: include: octeontx: add headers for OcteonTX > > > arch: include: octeontx2: add headers for OcteonTX2 > > > drivers: ata: ahci: update max id if it is more than available ports > > > drivers: ata: ahci: fill upper 32bit buffer address in sg descriptor > > > drivers: ata: ahci: add BAR index quirk for OcteonTX > > > drivers: pci: add PCI controller driver for OcteonTX > > > drivers: gpio: add GPIO controller driver for OcteonTX > > > drivers: i2c: add I2C controller driver for OcteonTX > > > drivers: spi: add SPI controller driver for OcteonTX > > > drivers: mmc: remove static qualifier on mmc_power_init > > > drivers: mmc: add MMC controller driver for OcteonTX > > > drivers: mtd: nand: add NAND controller driver for OcteonTX > > > drivers: net: add NIC controller driver for OcteonTX > > > drivers: net: add NIC controller driver for OcteonTX2 > > > drivers: watchdog: add reset support for OcteonTX > > > octeontx: Add support for OcteonTX SoC platforms > > > octeontx2: Add support for OcteonTX2 SoC platforms > > > > > > arch/arm/Kconfig | 22 + > > > arch/arm/Makefile | 2 + > > > arch/arm/include/asm/arch-octeontx/board.h | 121 + > > > arch/arm/include/asm/arch-octeontx/clock.h | 25 + > > > .../asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 ++ > > > .../include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 + > > > arch/arm/include/asm/arch-octeontx/gpio.h | 6 + > > > arch/arm/include/asm/arch-octeontx/smc.h | 20 + > > > arch/arm/include/asm/arch-octeontx/soc.h | 31 + > > > arch/arm/include/asm/arch-octeontx2/board.h | 123 + > > > arch/arm/include/asm/arch-octeontx2/clock.h | 24 + > > > .../asm/arch-octeontx2/csrs/csrs-cgx.h | 7835 ++++++++++++ > > > .../asm/arch-octeontx2/csrs/csrs-lmt.h | 60 + > > > .../asm/arch-octeontx2/csrs/csrs-mio_emm.h | 1193 ++ > > > .../asm/arch-octeontx2/csrs/csrs-nix.h | 10482 ++++++++++++++++ > > > .../asm/arch-octeontx2/csrs/csrs-npa.h | 2296 ++++ > > > .../asm/arch-octeontx2/csrs/csrs-npc.h | 1930 +++ > > > .../asm/arch-octeontx2/csrs/csrs-rvu.h | 2430 ++++ > > > arch/arm/include/asm/arch-octeontx2/gpio.h | 6 + > > > arch/arm/include/asm/arch-octeontx2/smc-id.h | 32 + > > > arch/arm/include/asm/arch-octeontx2/smc.h | 18 + > > > arch/arm/include/asm/arch-octeontx2/soc.h | 31 + > > > arch/arm/include/asm/io.h | 8 + > > > arch/arm/mach-octeontx/Kconfig | 23 + > > > arch/arm/mach-octeontx/Makefile | 9 + > > > arch/arm/mach-octeontx/clock.c | 35 + > > > arch/arm/mach-octeontx/cpu.c | 76 + > > > arch/arm/mach-octeontx/lowlevel_init.S | 33 + > > > arch/arm/mach-octeontx2/Kconfig | 23 + > > > arch/arm/mach-octeontx2/Makefile | 9 + > > > arch/arm/mach-octeontx2/clock.c | 35 + > > > arch/arm/mach-octeontx2/config.mk | 4 + > > > arch/arm/mach-octeontx2/cpu.c | 72 + > > > arch/arm/mach-octeontx2/lowlevel_init.S | 33 + > > > board/Marvell/octeontx/Kconfig | 14 + > > > board/Marvell/octeontx/MAINTAINERS | 9 + > > > board/Marvell/octeontx/Makefile | 9 + > > > board/Marvell/octeontx/board-fdt.c | 271 + > > > board/Marvell/octeontx/board.c | 137 + > > > board/Marvell/octeontx/smc.c | 30 + > > > board/Marvell/octeontx/soc-utils.c | 53 + > > > board/Marvell/octeontx2/Kconfig | 15 + > > > board/Marvell/octeontx2/MAINTAINERS | 9 + > > > board/Marvell/octeontx2/Makefile | 9 + > > > board/Marvell/octeontx2/board-fdt.c | 155 + > > > board/Marvell/octeontx2/board.c | 232 + > > > board/Marvell/octeontx2/smc.c | 62 + > > > board/Marvell/octeontx2/soc-utils.c | 49 + > > > configs/octeontx2_95xx_defconfig | 105 + > > > configs/octeontx2_96xx_defconfig | 131 + > > > configs/octeontx_81xx_defconfig | 133 + > > > configs/octeontx_83xx_defconfig | 130 + > > > drivers/ata/ahci.c | 15 + > > > drivers/gpio/Kconfig | 7 + > > > drivers/gpio/Makefile | 1 + > > > drivers/gpio/octeontx_gpio.c | 218 + > > > drivers/i2c/Kconfig | 7 + > > > drivers/i2c/Makefile | 1 + > > > drivers/i2c/octeontx_i2c.c | 968 ++ > > > drivers/mmc/Kconfig | 9 + > > > drivers/mmc/Makefile | 1 + > > > drivers/mmc/mmc.c | 2 +- > > > drivers/mmc/octeontx_hsmmc.c | 3233 +++++ > > > drivers/mmc/octeontx_hsmmc.h | 191 + > > > drivers/mtd/nand/raw/Kconfig | 16 + > > > drivers/mtd/nand/raw/Makefile | 2 + > > > drivers/mtd/nand/raw/octeontx_bch.c | 424 + > > > drivers/mtd/nand/raw/octeontx_bch.h | 142 + > > > drivers/mtd/nand/raw/octeontx_bch_regs.h | 169 + > > > drivers/mtd/nand/raw/octeontx_nand.c | 2261 ++++ > > > drivers/net/Kconfig | 29 + > > > drivers/net/Makefile | 4 + > > > drivers/net/octeontx/Makefile | 9 + > > > drivers/net/octeontx/bgx.c | 1546 +++ > > > drivers/net/octeontx/bgx.h | 259 + > > > drivers/net/octeontx/nic.h | 518 + > > > drivers/net/octeontx/nic_main.c | 777 ++ > > > drivers/net/octeontx/nic_reg.h | 252 + > > > drivers/net/octeontx/nicvf_main.c | 575 + > > > drivers/net/octeontx/nicvf_queues.c | 1141 ++ > > > drivers/net/octeontx/nicvf_queues.h | 355 + > > > drivers/net/octeontx/q_struct.h | 697 + > > > drivers/net/octeontx/smi.c | 382 + > > > drivers/net/octeontx/xcv.c | 129 + > > > drivers/net/octeontx2/Makefile | 11 + > > > drivers/net/octeontx2/cgx.c | 297 + > > > drivers/net/octeontx2/cgx.h | 105 + > > > drivers/net/octeontx2/cgx_intf.c | 421 + > > > drivers/net/octeontx2/cgx_intf.h | 370 + > > > drivers/net/octeontx2/lmt.h | 51 + > > > drivers/net/octeontx2/nix.c | 824 ++ > > > drivers/net/octeontx2/nix.h | 355 + > > > drivers/net/octeontx2/nix_af.c | 1103 ++ > > > drivers/net/octeontx2/npc.h | 92 + > > > drivers/net/octeontx2/rvu.h | 127 + > > > drivers/net/octeontx2/rvu_af.c | 172 + > > > drivers/net/octeontx2/rvu_common.c | 74 + > > > drivers/net/octeontx2/rvu_pf.c | 118 + > > > drivers/pci/Kconfig | 17 + > > > drivers/pci/Makefile | 1 + > > > drivers/pci/pci-uclass.c | 211 +- > > > drivers/pci/pci_octeontx.c | 538 + > > > drivers/rtc/Kconfig | 7 + > > > drivers/rtc/ds1337.c | 170 + > > > drivers/spi/Kconfig | 6 + > > > drivers/spi/Makefile | 1 + > > > drivers/spi/octeontx_spi.c | 750 ++ > > > drivers/watchdog/Kconfig | 10 + > > > drivers/watchdog/Makefile | 1 + > > > drivers/watchdog/octeontx_wdt.c | 76 + > > > include/configs/octeontx2_95xx.h | 80 + > > > include/configs/octeontx2_96xx.h | 90 + > > > include/configs/octeontx_common.h | 98 + > > > include/fdtdec.h | 12 + > > > include/mmc.h | 1 + > > > include/pci.h | 23 +- > > > include/pci_ids.h | 2 + > > > lib/fdtdec.c | 16 + > > > 118 files changed, 50774 insertions(+), 17 deletions(-) > > > create mode 100644 arch/arm/include/asm/arch-octeontx/board.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx/clock.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx/gpio.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx/smc.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx/soc.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/board.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/clock.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-cgx.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-lmt.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-mio_emm.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-nix.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npa.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-npc.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/csrs/csrs-rvu.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/gpio.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/smc-id.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/smc.h > > > create mode 100644 arch/arm/include/asm/arch-octeontx2/soc.h > > > create mode 100644 arch/arm/mach-octeontx/Kconfig > > > create mode 100644 arch/arm/mach-octeontx/Makefile > > > create mode 100644 arch/arm/mach-octeontx/clock.c > > > create mode 100644 arch/arm/mach-octeontx/cpu.c > > > create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S > > > create mode 100644 arch/arm/mach-octeontx2/Kconfig > > > create mode 100644 arch/arm/mach-octeontx2/Makefile > > > create mode 100644 arch/arm/mach-octeontx2/clock.c > > > create mode 100644 arch/arm/mach-octeontx2/config.mk > > > create mode 100644 arch/arm/mach-octeontx2/cpu.c > > > create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S > > > create mode 100644 board/Marvell/octeontx/Kconfig > > > create mode 100644 board/Marvell/octeontx/MAINTAINERS > > > create mode 100644 board/Marvell/octeontx/Makefile > > > create mode 100644 board/Marvell/octeontx/board-fdt.c > > > create mode 100644 board/Marvell/octeontx/board.c > > > create mode 100644 board/Marvell/octeontx/smc.c > > > create mode 100644 board/Marvell/octeontx/soc-utils.c > > > create mode 100644 board/Marvell/octeontx2/Kconfig > > > create mode 100644 board/Marvell/octeontx2/MAINTAINERS > > > create mode 100644 board/Marvell/octeontx2/Makefile > > > create mode 100644 board/Marvell/octeontx2/board-fdt.c > > > create mode 100644 board/Marvell/octeontx2/board.c > > > create mode 100644 board/Marvell/octeontx2/smc.c > > > create mode 100644 board/Marvell/octeontx2/soc-utils.c > > > create mode 100644 configs/octeontx2_95xx_defconfig > > > create mode 100644 configs/octeontx2_96xx_defconfig > > > create mode 100644 configs/octeontx_81xx_defconfig > > > create mode 100644 configs/octeontx_83xx_defconfig > > > create mode 100644 drivers/gpio/octeontx_gpio.c > > > create mode 100644 drivers/i2c/octeontx_i2c.c > > > create mode 100644 drivers/mmc/octeontx_hsmmc.c > > > create mode 100644 drivers/mmc/octeontx_hsmmc.h > > > create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c > > > create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h > > > create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h > > > create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c > > > create mode 100644 drivers/net/octeontx/Makefile > > > create mode 100644 drivers/net/octeontx/bgx.c > > > create mode 100644 drivers/net/octeontx/bgx.h > > > create mode 100644 drivers/net/octeontx/nic.h > > > create mode 100644 drivers/net/octeontx/nic_main.c > > > create mode 100644 drivers/net/octeontx/nic_reg.h > > > create mode 100644 drivers/net/octeontx/nicvf_main.c > > > create mode 100644 drivers/net/octeontx/nicvf_queues.c > > > create mode 100644 drivers/net/octeontx/nicvf_queues.h > > > create mode 100644 drivers/net/octeontx/q_struct.h > > > create mode 100644 drivers/net/octeontx/smi.c > > > create mode 100644 drivers/net/octeontx/xcv.c > > > create mode 100644 drivers/net/octeontx2/Makefile > > > create mode 100644 drivers/net/octeontx2/cgx.c > > > create mode 100644 drivers/net/octeontx2/cgx.h > > > create mode 100644 drivers/net/octeontx2/cgx_intf.c > > > create mode 100644 drivers/net/octeontx2/cgx_intf.h > > > create mode 100644 drivers/net/octeontx2/lmt.h > > > create mode 100644 drivers/net/octeontx2/nix.c > > > create mode 100644 drivers/net/octeontx2/nix.h > > > create mode 100644 drivers/net/octeontx2/nix_af.c > > > create mode 100644 drivers/net/octeontx2/npc.h > > > create mode 100644 drivers/net/octeontx2/rvu.h > > > create mode 100644 drivers/net/octeontx2/rvu_af.c > > > create mode 100644 drivers/net/octeontx2/rvu_common.c > > > create mode 100644 drivers/net/octeontx2/rvu_pf.c > > > create mode 100644 drivers/pci/pci_octeontx.c > > > create mode 100644 drivers/spi/octeontx_spi.c > > > create mode 100644 drivers/watchdog/octeontx_wdt.c > > > create mode 100644 include/configs/octeontx2_95xx.h > > > create mode 100644 include/configs/octeontx2_96xx.h > > > create mode 100644 include/configs/octeontx_common.h > > > > > > -- > > > 2.23.0 > > > > > > > Tom, > > > > I haven't seen any reviews or comments of any of Suneel's patch series > > here other than the testing I performed. > > > > What are the next steps in being able to get this code merged? The > > patches to pci-uclass are perhaps the only ones that would even affect > > other boards as pretty much everything else is adding a new driver. > > I've spent a bit of time looking at these. Some are OK but some need a > little work. Thanks Simon. Part of the answer is that I was hoping for someone to have a chance to chime in and look. Otherwise, as a new platform this is going to wait until after v2020.01 is released, JFYI.