===================================================================
@@ -109,9 +109,6 @@
sh port Oleg Endo <olegendo@gcc.gnu.org>
sparc port David S. Miller <davem@redhat.com>
sparc port Eric Botcazou <ebotcazou@libertysurf.fr>
-spu port Trevor Smigiel <trevor_smigiel@playstation.sony.com>
-spu port David Edelsohn <dje.gcc@gmail.com>
-spu port Ulrich Weigand <uweigand@de.ibm.com>
tilegx port Walter Lee <walt@tilera.com>
tilepro port Walter Lee <walt@tilera.com>
v850 port Nick Clifton <nickc@redhat.com>
===================================================================
@@ -34,7 +34,7 @@
sh_opts='-m3 -m3e -m4 -m4a -m4al -m4/-mieee -m1 -m1/-mno-cbranchdi -m2a -m2a/-mieee -m2e -m2e/-mieee'
sparc_opts='-mcpu=v8/-m32 -mcpu=v9/-m32 -m64'
-all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sparc spu v850 vax xstormy16 xtensa' # e500
+all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sparc v850 vax xstormy16 xtensa' # e500
test_one_file ()
{
===================================================================
@@ -90,7 +90,7 @@
sparc-leon3-linux-gnuOPT-enable-target=all sparc-netbsdelf \
sparc64-sun-solaris2.11OPT-with-gnu-ldOPT-with-gnu-asOPT-enable-threads=posix \
sparc-wrs-vxworks sparc64-elf sparc64-rtems sparc64-linux sparc64-freebsd6 \
- sparc64-netbsd sparc64-openbsd spu-elf \
+ sparc64-netbsd sparc64-openbsd \
tilegx-linux-gnu tilegxbe-linux-gnu tilepro-linux-gnu \
v850e-elf v850-elf v850-rtems vax-linux-gnu \
vax-netbsdelf vax-openbsd visium-elf x86_64-apple-darwin \
===================================================================
@@ -203,7 +203,7 @@
these targets. They are also known to the tool. When building targets it
will check those targets before the rest.
This coverage can be achieved by building config-list.mk with :
- LIST="aarch64-linux-gnu arm-netbsdelf c6x-elf epiphany-elf hppa2.0-hpux10.1 i686-mingw32crt i686-pc-msdosdjgpp mipsel-elf powerpc-eabisimaltivec rs6000-ibm-aix5.1.0 sh-superh-elf sparc64-elf spu-elf"
+ LIST="aarch64-linux-gnu arm-netbsdelf c6x-elf epiphany-elf hppa2.0-hpux10.1 i686-mingw32crt i686-pc-msdosdjgpp mipsel-elf powerpc-eabisimaltivec rs6000-ibm-aix5.1.0 sh-superh-elf sparc64-elf"
-b specifies the native bootstrapped build root directory
-t specifies a target build root directory that config-list.mk was run from
===================================================================
@@ -32,8 +32,7 @@
"powerpc-eabisimaltivec",
"rs6000-ibm-aix5.1.0",
"sh-superh-elf",
- "sparc64-elf",
- "spu-elf"
+ "sparc64-elf"
]
===================================================================
@@ -12971,10 +12971,8 @@
# simply assume that if we have mman.h, we have mmap.
have_mmap=yes
case "${host}" in
- spu-*-*|*-*-msdosdjgpp)
- # The SPU does not have mmap, but it has a sys/mman.h header file
- # containing "mmap_eaddr" and the mmap flags, confusing the test.
- # DJGPP also has sys/man.h, but no mmap
+ *-*-msdosdjgpp)
+ # DJGPP has sys/man.h, but no mmap
have_mmap=no ;;
esac
else
@@ -13115,7 +13113,6 @@
if test -n "${with_target_subdir}"; then
case "${host}" in
*-*-mingw*) have_fcntl=no ;;
- spu-*-*) have_fcntl=no ;;
*) have_fcntl=yes ;;
esac
else
===================================================================
@@ -293,10 +293,8 @@
# simply assume that if we have mman.h, we have mmap.
have_mmap=yes
case "${host}" in
- spu-*-*|*-*-msdosdjgpp)
- # The SPU does not have mmap, but it has a sys/mman.h header file
- # containing "mmap_eaddr" and the mmap flags, confusing the test.
- # DJGPP also has sys/man.h, but no mmap
+ *-*-msdosdjgpp)
+ # DJGPP has sys/man.h, but no mmap
have_mmap=no ;;
esac
else
@@ -364,7 +362,6 @@
if test -n "${with_target_subdir}"; then
case "${host}" in
*-*-mingw*) have_fcntl=no ;;
- spu-*-*) have_fcntl=no ;;
*) have_fcntl=yes ;;
esac
else
===================================================================
@@ -1952,9 +1952,9 @@
if (node)
{
/* Do not treat conditional macros as being defined. This is due to
- the powerpc and spu ports using conditional macros for 'vector',
- 'bool', and 'pixel' to act as conditional keywords. This messes
- up tests like #ifndef bool. */
+ the powerpc port using conditional macros for 'vector', 'bool',
+ and 'pixel' to act as conditional keywords. This messes up tests
+ like #ifndef bool. */
skip = !cpp_macro_p (node) || (node->flags & NODE_CONDITIONAL);
_cpp_mark_macro_used (node);
_cpp_maybe_notify_macro_use (pfile, node);
@@ -1981,9 +1981,9 @@
if (node)
{
/* Do not treat conditional macros as being defined. This is due to
- the powerpc and spu ports using conditional macros for 'vector',
- 'bool', and 'pixel' to act as conditional keywords. This messes
- up tests like #ifndef bool. */
+ the powerpc port using conditional macros for 'vector', 'bool',
+ and 'pixel' to act as conditional keywords. This messes up tests
+ like #ifndef bool. */
skip = (cpp_macro_p (node)
&& !(node->flags & NODE_CONDITIONAL));
_cpp_mark_macro_used (node);
===================================================================
@@ -1075,8 +1075,8 @@
pfile->state.prevent_expansion--;
/* Do not treat conditional macros as being defined. This is due to the
- powerpc and spu ports using conditional macros for 'vector', 'bool', and
- 'pixel' to act as conditional keywords. This messes up tests like #ifndef
+ powerpc port using conditional macros for 'vector', 'bool', and 'pixel'
+ to act as conditional keywords. This messes up tests like #ifndef
bool. */
result.unsignedp = false;
result.high = 0;
===================================================================
@@ -189,9 +189,6 @@
sparc*-*-*)
cpu_type=sparc
;;
-spu*-*-*)
- cpu_type=spu
- ;;
s390*-*-*)
cpu_type=s390
;;
@@ -1369,13 +1366,6 @@
;;
sparc64-*-netbsd*)
;;
-spu-*-elf*)
- tmake_file="$tmake_file spu/t-elf t-libgcc-pic t-fdpbit"
- extra_parts="$extra_parts \
- libgcc_cachemgr.a libgcc_cachemgr_nonatomic.a \
- libgcc_cache8k.a libgcc_cache16k.a libgcc_cache32k.a \
- libgcc_cache64k.a libgcc_cache128k.a"
- ;;
tic6x-*-uclinux)
tmake_file="${tmake_file} t-softfp-sfdf t-softfp-excl t-softfp \
c6x/t-elf c6x/t-uclinux t-crtstuff-pic t-libgcc-pic \
===================================================================
@@ -247,8 +247,7 @@
# Obsolete configurations.
case ${target} in
- spu*-*-* \
- | tile*-*-* \
+ tile*-*-* \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
@@ -280,6 +279,7 @@
| powerpc*-*-linux*paired* \
| powerpc*-*-*spe* \
| sparc-hal-solaris2* \
+ | spu*-*-* \
| thumb-*-* \
| *-*-freebsd[12] | *-*-freebsd[1234].* \
| *-*-freebsd*aout* \
@@ -535,9 +535,6 @@
d_target_objs="sparc-d.o"
extra_headers="visintrin.h"
;;
-spu*-*-*)
- cpu_type=spu
- ;;
s390*-*-*)
cpu_type=s390
d_target_objs="s390-d.o"
@@ -3171,15 +3168,6 @@
with_cpu=ultrasparc
tmake_file="${tmake_file} sparc/t-sparc"
;;
-spu-*-elf*)
- tm_file="dbxelf.h elfos.h spu/spu-elf.h spu/spu.h newlib-stdint.h"
- tmake_file="spu/t-spu-elf"
- native_system_header_dir=/include
- extra_headers="spu_intrinsics.h spu_internals.h vmx2spu.h spu_mfcio.h vec_types.h spu_cache.h"
- extra_modes=spu/spu-modes.def
- c_target_objs="${c_target_objs} spu-c.o"
- cxx_target_objs="${cxx_target_objs} spu-c.o"
- ;;
tic6x-*-elf)
tm_file="elfos.h ${tm_file} c6x/elf-common.h c6x/elf.h"
tm_file="${tm_file} dbxelf.h tm-dwarf2.h newlib-stdint.h"
@@ -4890,23 +4878,6 @@
esac
;;
- spu-*-*)
- supported_defaults="arch tune"
-
- for which in arch tune; do
- eval "val=\$with_$which"
- case ${val} in
- "" | cell | celledp)
- # OK
- ;;
- *)
- echo "Unknown cpu used in --with-$which=$val." 1>&2
- exit 1
- ;;
- esac
- done
- ;;
-
tic6x-*-*)
supported_defaults="arch"
===================================================================
@@ -27962,7 +27962,7 @@
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | m32c | m68k \
- | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \
+ | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
| tilegx | tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;
===================================================================
@@ -4999,7 +4999,7 @@
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | m32c | m68k \
- | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \
+ | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
| tilegx | tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;
===================================================================
@@ -1385,7 +1385,7 @@
defined in the N1275 draft of ISO/IEC DTR 18037. Support for named
address spaces in GCC will evolve as the draft technical report
changes. Calling conventions for any target might also change. At
-present, only the AVR, SPU, M32C, RL78, and x86 targets support
+present, only the AVR, M32C, RL78, and x86 targets support
address spaces other than the generic address space.
Address space identifiers may be used exactly like any other C type
@@ -1573,23 +1573,6 @@
addresses. Non-far variables are assumed to appear in the topmost
64@tie{}KiB of the address space.
-@subsection SPU Named Address Spaces
-@cindex @code{__ea} SPU Named Address Spaces
-
-On the SPU target variables may be declared as
-belonging to another address space by qualifying the type with the
-@code{__ea} address space identifier:
-
-@smallexample
-extern int __ea i;
-@end smallexample
-
-@noindent
-The compiler generates special code to access the variable @code{i}.
-It may use runtime library
-support, or generate special machine instructions to access that address
-space.
-
@subsection x86 Named Address Spaces
@cindex x86 named address spaces
@@ -2486,7 +2469,6 @@
* RX Function Attributes::
* S/390 Function Attributes::
* SH Function Attributes::
-* SPU Function Attributes::
* Symbian OS Function Attributes::
* V850 Function Attributes::
* Visium Function Attributes::
@@ -5839,24 +5821,6 @@
but it does not save and restore all registers.
@end table
-@node SPU Function Attributes
-@subsection SPU Function Attributes
-
-These function attributes are supported by the SPU back end:
-
-@table @code
-@item naked
-@cindex @code{naked} function attribute, SPU
-This attribute allows the compiler to construct the
-requisite function declaration, while allowing the body of the
-function to be assembly code. The specified function will not have
-prologue/epilogue sequences generated by the compiler. Only basic
-@code{asm} statements can safely be included in naked functions
-(@pxref{Basic Asm}). While using extended @code{asm} or a mixture of
-basic @code{asm} and C code may appear to work, they cannot be
-depended upon to work reliably and are not supported.
-@end table
-
@node Symbian OS Function Attributes
@subsection Symbian OS Function Attributes
@@ -6707,7 +6671,6 @@
* Nvidia PTX Variable Attributes::
* PowerPC Variable Attributes::
* RL78 Variable Attributes::
-* SPU Variable Attributes::
* V850 Variable Attributes::
* x86 Variable Attributes::
* Xstormy16 Variable Attributes::
@@ -7622,14 +7585,6 @@
specifies placement of the corresponding variable in the SADDR area,
which can be accessed more efficiently than the default memory region.
-@node SPU Variable Attributes
-@subsection SPU Variable Attributes
-
-@cindex @code{spu_vector} variable attribute, SPU
-The SPU supports the @code{spu_vector} attribute for variables. For
-documentation of this attribute please see the documentation in
-@ref{SPU Type Attributes}.
-
@node V850 Variable Attributes
@subsection V850 Variable Attributes
@@ -7737,7 +7692,6 @@
* ARM Type Attributes::
* MeP Type Attributes::
* PowerPC Type Attributes::
-* SPU Type Attributes::
* x86 Type Attributes::
@end menu
@@ -8328,15 +8282,6 @@
These attributes mainly are intended to support the @code{__vector},
@code{__pixel}, and @code{__bool} AltiVec keywords.
-@node SPU Type Attributes
-@subsection SPU Type Attributes
-
-@cindex @code{spu_vector} type attribute, SPU
-The SPU supports the @code{spu_vector} attribute for types. This attribute
-allows one to declare vector data types supported by the Sony/Toshiba/IBM SPU
-Language Extensions Specification. It is intended to support the
-@code{__vector} keyword.
-
@node x86 Type Attributes
@subsection x86 Type Attributes
@@ -13621,7 +13566,6 @@
* S/390 System z Built-in Functions::
* SH Built-in Functions::
* SPARC VIS Built-in Functions::
-* SPU Built-in Functions::
* TI C6X Built-in Functions::
* TILE-Gx Built-in Functions::
* TILEPro Built-in Functions::
@@ -21160,61 +21104,6 @@
long __builtin_vis_fpcmpur32shl (v2si, v2si, int);
@end smallexample
-@node SPU Built-in Functions
-@subsection SPU Built-in Functions
-
-GCC provides extensions for the SPU processor as described in the
-Sony/Toshiba/IBM SPU Language Extensions Specification. GCC's
-implementation differs in several ways.
-
-@itemize @bullet
-
-@item
-The optional extension of specifying vector constants in parentheses is
-not supported.
-
-@item
-A vector initializer requires no cast if the vector constant is of the
-same type as the variable it is initializing.
-
-@item
-If @code{signed} or @code{unsigned} is omitted, the signedness of the
-vector type is the default signedness of the base type. The default
-varies depending on the operating system, so a portable program should
-always specify the signedness.
-
-@item
-By default, the keyword @code{__vector} is added. The macro
-@code{vector} is defined in @code{<spu_intrinsics.h>} and can be
-undefined.
-
-@item
-GCC allows using a @code{typedef} name as the type specifier for a
-vector type.
-
-@item
-For C, overloaded functions are implemented with macros so the following
-does not work:
-
-@smallexample
- spu_add ((vector signed int)@{1, 2, 3, 4@}, foo);
-@end smallexample
-
-@noindent
-Since @code{spu_add} is a macro, the vector constant in the example
-is treated as four separate arguments. Wrap the entire argument in
-parentheses for this to work.
-
-@item
-The extended version of @code{__builtin_expect} is not supported.
-
-@end itemize
-
-@emph{Note:} Only the interface described in the aforementioned
-specification is supported. Internally, GCC uses built-in functions to
-implement the required functionality, but these are not supported and
-are subject to change without notice.
-
@node TI C6X Built-in Functions
@subsection TI C6X Built-in Functions
===================================================================
@@ -1214,17 +1214,6 @@
-mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol
-mlra -mno-lra}
-@emph{SPU Options}
-@gccoptlist{-mwarn-reloc -merror-reloc @gol
--msafe-dma -munsafe-dma @gol
--mbranch-hints @gol
--msmall-mem -mlarge-mem -mstdmain @gol
--mfixed-range=@var{register-range} @gol
--mea32 -mea64 @gol
--maddress-space-conversion -mno-address-space-conversion @gol
--mcache-size=@var{cache-size} @gol
--matomic-updates -mno-atomic-updates}
-
@emph{System V Options}
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
@@ -15717,7 +15706,6 @@
* SH Options::
* Solaris 2 Options::
* SPARC Options::
-* SPU Options::
* System V Options::
* TILE-Gx Options::
* TILEPro Options::
@@ -26770,141 +26758,6 @@
Otherwise, assume no such offset is present.
@end table
-@node SPU Options
-@subsection SPU Options
-@cindex SPU options
-
-These @samp{-m} options are supported on the SPU:
-
-@table @gcctabopt
-@item -mwarn-reloc
-@itemx -merror-reloc
-@opindex mwarn-reloc
-@opindex merror-reloc
-
-The loader for SPU does not handle dynamic relocations. By default, GCC
-gives an error when it generates code that requires a dynamic
-relocation. @option{-mno-error-reloc} disables the error,
-@option{-mwarn-reloc} generates a warning instead.
-
-@item -msafe-dma
-@itemx -munsafe-dma
-@opindex msafe-dma
-@opindex munsafe-dma
-
-Instructions that initiate or test completion of DMA must not be
-reordered with respect to loads and stores of the memory that is being
-accessed.
-With @option{-munsafe-dma} you must use the @code{volatile} keyword to protect
-memory accesses, but that can lead to inefficient code in places where the
-memory is known to not change. Rather than mark the memory as volatile,
-you can use @option{-msafe-dma} to tell the compiler to treat
-the DMA instructions as potentially affecting all memory.
-
-@item -mbranch-hints
-@opindex mbranch-hints
-
-By default, GCC generates a branch hint instruction to avoid
-pipeline stalls for always-taken or probably-taken branches. A hint
-is not generated closer than 8 instructions away from its branch.
-There is little reason to disable them, except for debugging purposes,
-or to make an object a little bit smaller.
-
-@item -msmall-mem
-@itemx -mlarge-mem
-@opindex msmall-mem
-@opindex mlarge-mem
-
-By default, GCC generates code assuming that addresses are never larger
-than 18 bits. With @option{-mlarge-mem} code is generated that assumes
-a full 32-bit address.
-
-@item -mstdmain
-@opindex mstdmain
-
-By default, GCC links against startup code that assumes the SPU-style
-main function interface (which has an unconventional parameter list).
-With @option{-mstdmain}, GCC links your program against startup
-code that assumes a C99-style interface to @code{main}, including a
-local copy of @code{argv} strings.
-
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator cannot use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
-
-@item -mea32
-@itemx -mea64
-@opindex mea32
-@opindex mea64
-Compile code assuming that pointers to the PPU address space accessed
-via the @code{__ea} named address space qualifier are either 32 or 64
-bits wide. The default is 32 bits. As this is an ABI-changing option,
-all object code in an executable must be compiled with the same setting.
-
-@item -maddress-space-conversion
-@itemx -mno-address-space-conversion
-@opindex maddress-space-conversion
-@opindex mno-address-space-conversion
-Allow/disallow treating the @code{__ea} address space as superset
-of the generic address space. This enables explicit type casts
-between @code{__ea} and generic pointer as well as implicit
-conversions of generic pointers to @code{__ea} pointers. The
-default is to allow address space pointer conversions.
-
-@item -mcache-size=@var{cache-size}
-@opindex mcache-size
-This option controls the version of libgcc that the compiler links to an
-executable and selects a software-managed cache for accessing variables
-in the @code{__ea} address space with a particular cache size. Possible
-options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64}
-and @samp{128}. The default cache size is 64KB.
-
-@item -matomic-updates
-@itemx -mno-atomic-updates
-@opindex matomic-updates
-@opindex mno-atomic-updates
-This option controls the version of libgcc that the compiler links to an
-executable and selects whether atomic updates to the software-managed
-cache of PPU-side variables are used. If you use atomic updates, changes
-to a PPU variable from SPU code using the @code{__ea} named address space
-qualifier do not interfere with changes to other PPU variables residing
-in the same cache line from PPU code. If you do not use atomic updates,
-such interference may occur; however, writing back cache lines is
-more efficient. The default behavior is to use atomic updates.
-
-@item -mdual-nops
-@itemx -mdual-nops=@var{n}
-@opindex mdual-nops
-By default, GCC inserts NOPs to increase dual issue when it expects
-it to increase performance. @var{n} can be a value from 0 to 10. A
-smaller @var{n} inserts fewer NOPs. 10 is the default, 0 is the
-same as @option{-mno-dual-nops}. Disabled with @option{-Os}.
-
-@item -mhint-max-nops=@var{n}
-@opindex mhint-max-nops
-Maximum number of NOPs to insert for a branch hint. A branch hint must
-be at least 8 instructions away from the branch it is affecting. GCC
-inserts up to @var{n} NOPs to enforce this, otherwise it does not
-generate the branch hint.
-
-@item -mhint-max-distance=@var{n}
-@opindex mhint-max-distance
-The encoding of the branch hint instruction limits the hint to be within
-256 instructions of the branch it is affecting. By default, GCC makes
-sure it is within 125.
-
-@item -msafe-hints
-@opindex msafe-hints
-Work around a hardware bug that causes the SPU to stall indefinitely.
-By default, GCC inserts the @code{hbrp} instruction to make sure
-this stall won't happen.
-
-@end table
-
@node System V Options
@subsection Options for System V
===================================================================
@@ -3736,76 +3736,6 @@
@end table
-@item SPU---@file{config/spu/spu.h}
-@table @code
-@item a
-An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
-
-@item c
-An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
-
-@item d
-An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
-
-@item f
-An immediate which can be loaded with @code{fsmbi}.
-
-@item A
-An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
-
-@item B
-An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
-
-@item C
-An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
-
-@item D
-An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
-
-@item I
-A constant in the range [@minus{}64, 63] for shift/rotate instructions.
-
-@item J
-An unsigned 7-bit constant for conversion/nop/channel instructions.
-
-@item K
-A signed 10-bit constant for most arithmetic instructions.
-
-@item M
-A signed 16 bit immediate for @code{stop}.
-
-@item N
-An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
-
-@item O
-An unsigned 7-bit constant whose 3 least significant bits are 0.
-
-@item P
-An unsigned 3-bit constant for 16-byte rotates and shifts
-
-@item R
-Call operand, reg, for indirect calls
-
-@item S
-Call operand, symbol, for relative calls.
-
-@item T
-Call operand, const_int, for absolute calls.
-
-@item U
-An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
-
-@item W
-An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
-
-@item Y
-An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
-
-@item Z
-An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
-
-@end table
-
@item TI C6X family---@file{config/c6x/constraints.md}
@table @code
@item a
===================================================================
@@ -2011,9 +2011,6 @@
@item ppc_recip_hw
PowerPC target supports executing reciprocal estimate instructions.
-@item spu_auto_overlay
-SPU target has toolchain that supports automatic overlay generation.
-
@item vmx_hw
PowerPC target supports executing AltiVec instructions.
@@ -2423,13 +2420,6 @@
Target supports compiling @code{xop} instructions.
@end table
-@subsubsection Local to tests in @code{gcc.target/spu/ea}
-
-@table @code
-@item ealib
-Target @code{__ea} library functions are available.
-@end table
-
@subsubsection Local to tests in @code{gcc.test-framework}
@table @code