@@ -27,6 +27,14 @@ extern const fenv_t *__fe_nomask_env_priv (void);
extern const fenv_t *__fe_mask_env (void) attribute_hidden;
+#ifdef _ARCH_PWR8
+/* There is no performance advantage to non-stop mode. */
+#define __ENTER_NON_STOP() do {} while (0)
+#else
+#define __ENTER_NON_STOP() do { (void) __fe_mask_env (); } while (0)
+#endif
+#define __EXIT_NON_STOP() do { (void) __fe_nomask_env_priv (); } while (0)
+
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
@@ -34,7 +42,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
#define __TEST_AND_ENTER_NON_STOP(old, new) \
do { \
if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \
- (void) __fe_mask_env (); \
+ __ENTER_NON_STOP (); \
} while (0)
/* If the old env has no enabled exceptions and the new env has any enabled
@@ -44,7 +52,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
#define __TEST_AND_EXIT_NON_STOP(old, new) \
do { \
if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \
- (void) __fe_nomask_env_priv (); \
+ __EXIT_NON_STOP (); \
} while (0)
/* The sticky bits in the FPSCR indicating exceptions have occurred. */
From: "Paul A. Clarke" <pc@us.ibm.com> Since at least POWER8, there is no performance advantage to entering "Ignore Exceptions Mode", and doing so conditionally requires the conditional logic as well as a system call. Make it a no-op. 2019-09-19 Paul A. Clarke <pc@us.ibm.com> * sysdeps/powerpc/fpu/fenv_libc.h: (__ENTER_NON_STOP): New. (__EXIT_NON_STOP): New. (__TEST_AND_ENTER_NON_STOP): Use __ENTER_NON_STOP. (__TEST_AND_EXIT_NON_STOP): Use __EXIT_NON_STOP. --- v2: This is a new patch in the series. sysdeps/powerpc/fpu/fenv_libc.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)