Message ID | 1565165849-16246-1-git-send-email-zhangshaokun@hisilicon.com |
---|---|
State | Not Applicable |
Delegated to: | David Miller |
Headers | show |
Series | net: stmmac: Fix the miscalculation of mapping from rxq to dma channel | expand |
From: Shaokun Zhang <zhangshaokun@hisilicon.com> Date: Aug/07/2019, 09:17:29 (UTC+00:00) > From: yuqi jin <jinyuqi@huawei.com> > > XGMAC_MTL_RXQ_DMA_MAP1 will be configured if the number of queues is > greater than 3, but local variable chan will shift left more than 32-bits. > Let's fix this issue. This was already fixed in -net. Please see [1] [1] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/co mmit/drivers/net/ethernet/stmicro/stmmac?id=e8df7e8c233a18d2704e37ecff475 83b494789d3 --- Thanks, Jose Miguel Abreu
Hi Jose, Thanks your quick reply. On 2019/8/7 16:24, Jose Abreu wrote: > From: Shaokun Zhang <zhangshaokun@hisilicon.com> > Date: Aug/07/2019, 09:17:29 (UTC+00:00) > >> From: yuqi jin <jinyuqi@huawei.com> >> >> XGMAC_MTL_RXQ_DMA_MAP1 will be configured if the number of queues is >> greater than 3, but local variable chan will shift left more than 32-bits. >> Let's fix this issue. > > This was already fixed in -net. Please see [1] > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/co > mmit/drivers/net/ethernet/stmicro/stmmac?id=e8df7e8c233a18d2704e37ecff475 > 83b494789d3 > > --- > Thanks, > Jose Miguel Abreu > >
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 0a32c96a7854..de4b15f31727 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -166,13 +166,14 @@ static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue, u32 chan) { void __iomem *ioaddr = hw->pcsr; - u32 value, reg; + u32 value, reg, index; reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1; + index = (queue < 4) ? queue : queue - 4; value = readl(ioaddr + reg); - value &= ~XGMAC_QxMDMACH(queue); - value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue); + value &= ~XGMAC_QxMDMACH(index); + value |= (chan << XGMAC_QxMDMACH_SHIFT(index)) & XGMAC_QxMDMACH(index); writel(value, ioaddr + reg); }