| Message ID | 20190806151214.6783-1-daniel.baluta@nxp.com |
|---|---|
| Headers | show |
| Series | Add support for new SAI IP version | expand |
On Tue, Aug 06, 2019 at 06:12:10PM +0300, Daniel Baluta wrote: > SAI IP supports up to 8 data lines. The configuration of > supported number of data lines is decided at SoC integration > time. > > This patch adds definitions for all related data TX/RX registers: > * TDR0..7, Transmit data register > * TFR0..7, Transmit FIFO register > * RDR0..7, Receive data register > * RFR0..7, Receive FIFO register > > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Thanks > --- > sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------ > sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++--- > 2 files changed, 98 insertions(+), 14 deletions(-) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 6d3c6c8d50ce..17b0aff4ee8b 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -685,7 +685,14 @@ static struct reg_default fsl_sai_reg_defaults[] = { > {FSL_SAI_TCR3, 0}, > {FSL_SAI_TCR4, 0}, > {FSL_SAI_TCR5, 0}, > - {FSL_SAI_TDR, 0}, > + {FSL_SAI_TDR0, 0}, > + {FSL_SAI_TDR1, 0}, > + {FSL_SAI_TDR2, 0}, > + {FSL_SAI_TDR3, 0}, > + {FSL_SAI_TDR4, 0}, > + {FSL_SAI_TDR5, 0}, > + {FSL_SAI_TDR6, 0}, > + {FSL_SAI_TDR7, 0}, > {FSL_SAI_TMR, 0}, > {FSL_SAI_RCR1, 0}, > {FSL_SAI_RCR2, 0}, > @@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) > case FSL_SAI_TCR3: > case FSL_SAI_TCR4: > case FSL_SAI_TCR5: > - case FSL_SAI_TFR: > + case FSL_SAI_TFR0: > + case FSL_SAI_TFR1: > + case FSL_SAI_TFR2: > + case FSL_SAI_TFR3: > + case FSL_SAI_TFR4: > + case FSL_SAI_TFR5: > + case FSL_SAI_TFR6: > + case FSL_SAI_TFR7: > case FSL_SAI_TMR: > case FSL_SAI_RCSR: > case FSL_SAI_RCR1: > @@ -712,8 +726,22 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) > case FSL_SAI_RCR3: > case FSL_SAI_RCR4: > case FSL_SAI_RCR5: > - case FSL_SAI_RDR: > - case FSL_SAI_RFR: > + case FSL_SAI_RDR0: > + case FSL_SAI_RDR1: > + case FSL_SAI_RDR2: > + case FSL_SAI_RDR3: > + case FSL_SAI_RDR4: > + case FSL_SAI_RDR5: > + case FSL_SAI_RDR6: > + case FSL_SAI_RDR7: > + case FSL_SAI_RFR0: > + case FSL_SAI_RFR1: > + case FSL_SAI_RFR2: > + case FSL_SAI_RFR3: > + case FSL_SAI_RFR4: > + case FSL_SAI_RFR5: > + case FSL_SAI_RFR6: > + case FSL_SAI_RFR7: > case FSL_SAI_RMR: > return true; > default: > @@ -726,9 +754,30 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) > switch (reg) { > case FSL_SAI_TCSR: > case FSL_SAI_RCSR: > - case FSL_SAI_TFR: > - case FSL_SAI_RFR: > - case FSL_SAI_RDR: > + case FSL_SAI_TFR0: > + case FSL_SAI_TFR1: > + case FSL_SAI_TFR2: > + case FSL_SAI_TFR3: > + case FSL_SAI_TFR4: > + case FSL_SAI_TFR5: > + case FSL_SAI_TFR6: > + case FSL_SAI_TFR7: > + case FSL_SAI_RFR0: > + case FSL_SAI_RFR1: > + case FSL_SAI_RFR2: > + case FSL_SAI_RFR3: > + case FSL_SAI_RFR4: > + case FSL_SAI_RFR5: > + case FSL_SAI_RFR6: > + case FSL_SAI_RFR7: > + case FSL_SAI_RDR0: > + case FSL_SAI_RDR1: > + case FSL_SAI_RDR2: > + case FSL_SAI_RDR3: > + case FSL_SAI_RDR4: > + case FSL_SAI_RDR5: > + case FSL_SAI_RDR6: > + case FSL_SAI_RDR7: > return true; > default: > return false; > @@ -744,7 +793,14 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) > case FSL_SAI_TCR3: > case FSL_SAI_TCR4: > case FSL_SAI_TCR5: > - case FSL_SAI_TDR: > + case FSL_SAI_TDR0: > + case FSL_SAI_TDR1: > + case FSL_SAI_TDR2: > + case FSL_SAI_TDR3: > + case FSL_SAI_TDR4: > + case FSL_SAI_TDR5: > + case FSL_SAI_TDR6: > + case FSL_SAI_TDR7: > case FSL_SAI_TMR: > case FSL_SAI_RCSR: > case FSL_SAI_RCR1: > @@ -885,8 +941,8 @@ static int fsl_sai_probe(struct platform_device *pdev) > MCLK_DIR(index)); > } > > - sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; > - sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; > + sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; > + sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; > sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; > sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; > > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h > index 7c1ef671da28..4bb478041d67 100644 > --- a/sound/soc/fsl/fsl_sai.h > +++ b/sound/soc/fsl/fsl_sai.h > @@ -20,8 +20,22 @@ > #define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */ > #define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */ > #define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */ > -#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */ > -#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */ > +#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */ > +#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */ > +#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */ > +#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */ > +#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */ > +#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */ > +#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */ > +#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */ > +#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */ > +#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */ > +#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */ > +#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */ > +#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */ > +#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */ > +#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */ > +#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */ > #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ > #define FSL_SAI_RCSR 0x80 /* SAI Receive Control */ > #define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */ > @@ -29,8 +43,22 @@ > #define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */ > #define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */ > #define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */ > -#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */ > -#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */ > +#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */ > +#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */ > +#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */ > +#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */ > +#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */ > +#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */ > +#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */ > +#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */ > +#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */ > +#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */ > +#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */ > +#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */ > +#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */ > +#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */ > +#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */ > +#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */ > #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */ > > #define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR) > -- > 2.17.1 >
On Tue, Aug 06, 2019 at 06:12:11PM +0300, Daniel Baluta wrote: > Tx channel enable (TCE) / Rx channel enable (RCE) bits > enable corresponding data channel for Tx/Rx operation. > > Because SAI supports up the 8 channels TCE/RCE occupy > up the 8 bits inside TCR3/RCR3 registers we need to extend > the mask to reflect this. > > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Thanks > --- > sound/soc/fsl/fsl_sai.c | 6 ++++-- > sound/soc/fsl/fsl_sai.h | 1 + > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 17b0aff4ee8b..637b1d12a575 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -599,7 +599,8 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, > bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; > int ret; > > - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, > + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), > + FSL_SAI_CR3_TRCE_MASK, > FSL_SAI_CR3_TRCE); > > ret = snd_pcm_hw_constraint_list(substream->runtime, 0, > @@ -614,7 +615,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream, > struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); > bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; > > - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); > + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), > + FSL_SAI_CR3_TRCE_MASK, 0); > } > > static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h > index 4bb478041d67..20c5b9b1e8bc 100644 > --- a/sound/soc/fsl/fsl_sai.h > +++ b/sound/soc/fsl/fsl_sai.h > @@ -110,6 +110,7 @@ > > /* SAI Transmit and Receive Configuration 3 Register */ > #define FSL_SAI_CR3_TRCE BIT(16) > +#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16) > #define FSL_SAI_CR3_WDFL(x) (x) > #define FSL_SAI_CR3_WDFL_MASK 0x1f > > -- > 2.17.1 >
On Tue, Aug 06, 2019 at 06:12:12PM +0300, Daniel Baluta wrote: > New IP version introduces Version ID and Parameter registers > and optionally added Timestamp feature. > > VERID and PARAM registers are placed at the top of registers > address space and some registers are shifted according to > the following table: > > Tx/Rx data registers and Tx/Rx FIFO registers keep their > addresses, all other registers are shifted by 8. > > SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map > of the Reference Manual [1]. > > In order to make as less changes as possible we attach an offset > to each register offset to each changed register definition. The > offset is read from each board private data. > > [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf > > Signed-off-by: Mihai Serban <mihai.serban@nxp.com> > [initial coding in the NXP internal tree] > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > [bugfixing and cleanups] > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> > [adapted to linux-next] Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> One small request that we can do with a separate patch later: > struct fsl_sai_soc_data { > bool use_imx_pcm; > unsigned int fifo_depth; > + unsigned int reg_offset; > }; I think we need a list of comments for the structure defines. It might be okay for the old two entries but reg_offset isn't that explicit any more.
So far SAI IPs integrated with imx6 only supported one data line. Starting with imx7 and imx8 SAI integration support up to 8 data lines. First patch introduce register definition to support this. New SAI IP version introduces two new registers (Version and Parmeter registers) which are placed at the beginning of register address space. For this reason we need to fix the register's address. Support for this is introduced in patch 3. Changes since v2: - removed patches regarding data line mask because I need to find a better way to describe to model data lines. Perhaps,we only need to specify how many datalines a specific SAI instance supports and then let SAI driver to activate datalines based on the number of channels. Will open the discussion on this on a separate thread. - fixed devicetree documentation as per Nicolin comments and will send a separate patch to convert it to yaml. Changes since v1: - removed patches from Lucas as they were already accepted - addressed comments from Lucas and Nicolin regarding device tree property naming - removed comment saying that "datalines" must be always consecutively enabled (this is not true, checked with IP owner) - added new patch to document newly introduced compatbile strings - removed patch introducing combined mode as I will still need some time to figure out how to properly allow users to set it. Daniel Baluta (5): ASoC: fsl_sai: Add registers definition for multiple datalines ASoC: fsl_sai: Update Tx/Rx channel enable mask ASoC: fsl_sai: Add support for SAI new version ASoC: fsl_sai: Add support for imx7ulp/imx8mq ASoC: dt-bindings: Introduce compatible strings for 7ULP and 8MQ .../devicetree/bindings/sound/fsl-sai.txt | 3 +- sound/soc/fsl/fsl_sai.c | 320 ++++++++++++------ sound/soc/fsl/fsl_sai.h | 78 +++-- 3 files changed, 273 insertions(+), 128 deletions(-)