Message ID | 1564394627-3810-1-git-send-email-claudiu.manoil@nxp.com |
---|---|
Headers | show |
Series | enetc: Add mdio bus driver for the PCIe MDIO endpoint | expand |
On Mon, Jul 29, 2019 at 01:03:44PM +0300, Claudiu Manoil wrote: > What's needed is basically a pointer to the mdio registers. > This is one way to store it inside bus->priv allocated space, > without upsetting sparse. > Reworked accessors to avoid __iomem casting. > Used devm_* variant to further clean up the init error / > remove paths. > > Fixes following sparse warning: > warning: incorrect type in assignment (different address spaces) > expected void *priv > got struct enetc_mdio_regs [noderef] <asn:2>*[assigned] regs > > Fixes: ebfcb23d62ab ("enetc: Add ENETC PF level external MDIO support") > > Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Thanks, much nicer. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
> + hw->port = pci_iomap(pdev, 0, 0); > + if (!bus->priv) { hw->port ?? Andrew
On Mon, Jul 29, 2019 at 01:03:47PM +0300, Claudiu Manoil wrote: > LS1028a has one Ethernet management interface. On the QDS board, the > MDIO signals are multiplexed to either on-board AR8035 PHY device or > to 4 PCIe slots allowing for SGMII cards. > To enable the Ethernet ENETC Port 1, which can only be connected to a > RGMII PHY, the multiplexer needs to be configured to route the MDIO to > the AR8035 PHY. The MDIO/MDC routing is controlled by bits 7:4 of FPGA > board config register 0x54, and value 0 selects the on-board RGMII PHY. > The FPGA board config registers are accessible on the i2c bus, at address > 0x66. > > The PF3 MDIO PCIe integrated endpoint device allows for centralized access > to the MDIO bus. Add the corresponding devicetree node and set it to be > the MDIO bus parent. > > Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> > Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
>-----Original Message----- >From: Andrew Lunn <andrew@lunn.ch> >Sent: Monday, July 29, 2019 6:35 PM >To: Claudiu Manoil <claudiu.manoil@nxp.com> >Cc: David S . Miller <davem@davemloft.net>; Rob Herring ><robh+dt@kernel.org>; Leo Li <leoyang.li@nxp.com>; Alexandru Marginean ><alexandru.marginean@nxp.com>; netdev@vger.kernel.org; >devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- >kernel@vger.kernel.org >Subject: Re: [PATCH net-next v3 2/4] enetc: Add mdio bus driver for the PCIe >MDIO endpoint > >> + hw->port = pci_iomap(pdev, 0, 0); >> + if (!bus->priv) { > >hw->port ?? > Yeah, better ignore this for now 😊 It's for the enetc accessors, enetc_port_..().
>-----Original Message----- >From: netdev-owner@vger.kernel.org <netdev-owner@vger.kernel.org> On >Behalf Of Claudiu Manoil >Sent: Monday, July 29, 2019 6:40 PM >To: Andrew Lunn <andrew@lunn.ch> >Cc: David S . Miller <davem@davemloft.net>; Rob Herring ><robh+dt@kernel.org>; Leo Li <leoyang.li@nxp.com>; Alexandru Marginean ><alexandru.marginean@nxp.com>; netdev@vger.kernel.org; >devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- >kernel@vger.kernel.org >Subject: RE: [PATCH net-next v3 2/4] enetc: Add mdio bus driver for the PCIe >MDIO endpoint > >>-----Original Message----- >>From: Andrew Lunn <andrew@lunn.ch> >>Sent: Monday, July 29, 2019 6:35 PM >>To: Claudiu Manoil <claudiu.manoil@nxp.com> >>Cc: David S . Miller <davem@davemloft.net>; Rob Herring >><robh+dt@kernel.org>; Leo Li <leoyang.li@nxp.com>; Alexandru Marginean >><alexandru.marginean@nxp.com>; netdev@vger.kernel.org; >>devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >>linux- kernel@vger.kernel.org >>Subject: Re: [PATCH net-next v3 2/4] enetc: Add mdio bus driver for the >>PCIe MDIO endpoint >> >>> + hw->port = pci_iomap(pdev, 0, 0); >>> + if (!bus->priv) { >> >>hw->port ?? >> > >Yeah, better ignore this for now 😊 >It's for the enetc accessors, enetc_port_..(). Oh I see, it's a mistake. I'm checking the wrong thing. Sorry. Thanks for the review.