Message ID | 20190713034634.44585-1-icenowy@aosc.io |
---|---|
Headers | show |
Series | Support for Allwinner V3/S3L and Sochip S3 | expand |
On Sat, Jul 13, 2019 at 11:46:27AM +0800, Icenowy Zheng wrote: > Introduce the GPIO pins that is only available on V3 (not on V3s) to the > V3s pinctrl driver. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
On Sat, Jul 13, 2019 at 11:46:28AM +0800, Icenowy Zheng wrote: > The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot > when developing the V3s CCU driver. > > Add back the missing PLL_DDR1. > > Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> queued for 5.4, thanks Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote: > The MMC2 clock slices are currently not defined in V3s CCU driver, which > makes MMC2 not working. > > Fix this issue. > > Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > New patch in v4. > > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > index 4eb68243e310..9c88015d4419 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { > [CLK_MMC1] = &mmc1_clk.common.hw, > [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, > [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, > + [CLK_MMC2] = &mmc1_clk.common.hw, > + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, > + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, You're using the same structures than mmc1, I guess it's a copy and paste mistake? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote: >> The MMC2 clock slices are currently not defined in V3s CCU driver, >which >> makes MMC2 not working. >> >> Fix this issue. >> >> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> New patch in v4. >> >> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >> index 4eb68243e310..9c88015d4419 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >> @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data >sun8i_v3s_hw_clks = { >> [CLK_MMC1] = &mmc1_clk.common.hw, >> [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, >> [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, >> + [CLK_MMC2] = &mmc1_clk.common.hw, >> + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, >> + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, > >You're using the same structures than mmc1, I guess it's a copy and >paste mistake? Yes. > >Maxime > >-- >Maxime Ripard, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com
On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote: > The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, > but with more GPIO wired out of the package. > > Add DTSI files for these SoCs. The DTSI file for V3 just replaces the > pinctrl compatible string, and the S3/S3L DTSI files just include the V3 > DTSI file. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes since v2. > > arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ > arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ > arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ > 3 files changed, 26 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi > create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi > create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi b/arch/arm/boot/dts/sun8i-s3.dtsi > new file mode 100644 > index 000000000000..0f41a25ecb30 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3.dtsi > @@ -0,0 +1,6 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi > new file mode 100644 > index 000000000000..0f41a25ecb30 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi > @@ -0,0 +1,6 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi > new file mode 100644 > index 000000000000..6ae8645ade50 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-v3.dtsi > @@ -0,0 +1,14 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3s.dtsi" > + > +&ccu { > + compatible = "allwinner,sun8i-v3-ccu"; > +}; > + > +&pio { > + compatible = "allwinner,sun8i-v3-pinctrl"; > +}; Is there any difference between the S3, S3L and V3? If not, then we don't need all those DTSI, just add the v3 Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
于 2019年7月20日 GMT+08:00 下午5:48:14, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote: >> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, >> but with more GPIO wired out of the package. >> >> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the >> pinctrl compatible string, and the S3/S3L DTSI files just include the >V3 >> DTSI file. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> No changes since v2. >> >> arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ >> arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ >> arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ >> 3 files changed, 26 insertions(+) >> create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi >> create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi >> create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi >> >> diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi >b/arch/arm/boot/dts/sun8i-s3.dtsi >> new file mode 100644 >> index 000000000000..0f41a25ecb30 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-s3.dtsi >> @@ -0,0 +1,6 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3.dtsi" >> diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi >b/arch/arm/boot/dts/sun8i-s3l.dtsi >> new file mode 100644 >> index 000000000000..0f41a25ecb30 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi >> @@ -0,0 +1,6 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3.dtsi" >> diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi >b/arch/arm/boot/dts/sun8i-v3.dtsi >> new file mode 100644 >> index 000000000000..6ae8645ade50 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-v3.dtsi >> @@ -0,0 +1,14 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3s.dtsi" >> + >> +&ccu { >> + compatible = "allwinner,sun8i-v3-ccu"; >> +}; >> + >> +&pio { >> + compatible = "allwinner,sun8i-v3-pinctrl"; >> +}; > >Is there any difference between the S3, S3L and V3? DRAM. This might be useful when we introduce DRAM DVFS. > >If not, then we don't need all those DTSI, just add the v3 But I agree with this now. > >Maxime > >-- >Maxime Ripard, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com
On Sat, Jul 13, 2019 at 11:46:34AM +0800, Icenowy Zheng wrote: > Lichee zero plus is a core board made by Sipeed, which includes on-board > TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug > header, a microUSB slot and a gold finger connector for expansion. It > can use either Sochip S3 or Allwinner S3L SoC. > > Add the basic device tree for the core board, w/o optional onboard > storage, and with S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes in v4. > > Changes in v3: > - Drop common regulator DTSI usage and added vcc3v3 regulator. > > arch/arm/boot/dts/Makefile | 1 + > .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ > .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 46 +++++++++++++++++++ > 3 files changed, 55 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 9159fa2cea90..e320460a952b 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1114,6 +1114,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-r16-nintendo-super-nes-classic.dtb \ > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > + sun8i-s3-lichee-zero-plus.dtb \ > sun8i-t3-cqa3t-bv3.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > sun8i-v3s-licheepi-zero-dock.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > new file mode 100644 > index 000000000000..7d2f6b145190 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +/dts-v1/; > +#include "sun8i-s3.dtsi" > +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" Why do we need to mention both the S3 and S3l in the name? What are the differences between the two, and why do you need to share a DTSI? > diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > new file mode 100644 > index 000000000000..2677d319fb29 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_vcc3v3: vcc3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > +}; > + > +&mmc0 { > + broken-cd; > + bus-width = <4>; > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; > + status = "okay"; How can it do OTG if there's no controlable VBUS? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com