diff mbox series

[net-next,1/1] qed: Add support for Timestamping the unicast PTP packets.

Message ID 20190702150412.31132-1-skalluru@marvell.com
State Changes Requested
Delegated to: David Miller
Headers show
Series [net-next,1/1] qed: Add support for Timestamping the unicast PTP packets. | expand

Commit Message

Sudarsana Reddy Kalluru July 2, 2019, 3:04 p.m. UTC 
This patch masks the lower 4 bits of PARAM-MASK registers as required
by the Hardware to detect/timestamp the unicast PTP packets. The register
definition in the header file captures more details on the individual bits.

Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com>
Signed-off-by: Ariel Elior <aelior@marvell.com>
---
 drivers/net/ethernet/qlogic/qed/qed_ptp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

David Miller July 2, 2019, 7:23 p.m. UTC | #1 
From: Sudarsana Reddy Kalluru <skalluru@marvell.com>
Date: Tue, 2 Jul 2019 08:04:12 -0700

> The register definition in the header file captures more details on
> the individual bits.

Where is this register definition in the header file and why aren't
CPP defines from there being used instead of a mask constant mask?

Thanks.
Sudarsana Reddy Kalluru July 3, 2019, 2:27 a.m. UTC | #2 
> -----Original Message-----
> From: David Miller <davem@davemloft.net>
> Sent: Wednesday, July 3, 2019 12:53 AM
> To: Sudarsana Reddy Kalluru <skalluru@marvell.com>
> Cc: netdev@vger.kernel.org; Michal Kalderon <mkalderon@marvell.com>;
> Ariel Elior <aelior@marvell.com>
> Subject: Re: [PATCH net-next 1/1] qed: Add support for Timestamping the
> unicast PTP packets.
> 
> From: Sudarsana Reddy Kalluru <skalluru@marvell.com>
> Date: Tue, 2 Jul 2019 08:04:12 -0700
> 
> > The register definition in the header file captures more details on
> > the individual bits.
> 
> Where is this register definition in the header file and why aren't CPP defines
> from there being used instead of a mask constant mask?
> 
> Thanks.
Sorry, my mistake. taking back my statement. Will send the updated patch with CPP define.
diff mbox series

Patch

diff --git a/drivers/net/ethernet/qlogic/qed/qed_ptp.c b/drivers/net/ethernet/qlogic/qed/qed_ptp.c
index f3ebdc5..4a7acfc 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_ptp.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_ptp.c
@@ -243,7 +243,7 @@  static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
 		return -EINVAL;
 	}
 
-	qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0);
+	qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0xF);
 	qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
 	qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, enable_cfg);
 
@@ -253,7 +253,7 @@  static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
 		qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
 	} else {
 		qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, enable_cfg);
-		qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0);
+		qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0xF);
 		qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, rule_mask);
 	}