mbox series

[v4,00/13] Allwinner A64/H6 IR support

Message ID 20190604162959.29199-1-peron.clem@gmail.com
Headers show
Series Allwinner A64/H6 IR support | expand

Message

Clément Péron June 4, 2019, 4:29 p.m. UTC 
Hi,

A64 IR support series[1] pointed out that an A31 bindings should be
introduced.

This series introduce the A31 compatible bindings, then switch it on
the already existing board.

Finally introduce A64 and H6 support.

I have reenable the other H6 boards IR support as Ondrej solve the issue.

Regards,
Clément

[1] https://lore.kernel.org/patchwork/patch/1031390/#1221464
[2] https://lkml.org/lkml/2019/5/27/321
[3] https://patchwork.kernel.org/patch/10975563/

Changes since v3:
 - Reenable IR for other H6 boards
 - Add RXSTA bits definition
 - Add Sean Young's "Acked-by" tags

Changes since v2:
 - Disable IR for other H6 boards
 - Split DTS patch for H3/H5
 - Introduce IR quirks

Changes since v1:
 - Document reset lines as required since A31
 - Explain the memory mapping difference in commit log
 - Fix misspelling "Allwiner" to "Allwinner"
Clément Péron (11):
  dt-bindings: media: sunxi-ir: Add A31 compatible
  media: rc: Introduce sunxi_ir_quirks
  media: rc: sunxi: Add A31 compatible
  media: rc: sunxi: Add RXSTA bits definition
  ARM: dts: sunxi: Prefer A31 bindings for IR
  ARM: dts: sunxi: Prefer A31 bindings for IR
  dt-bindings: media: sunxi-ir: Add A64 compatible
  dt-bindings: media: sunxi-ir: Add H6 compatible
  arm64: dts: allwinner: h6: Add IR receiver node
  arm64: dts: allwinner: h6: Enable IR on H6 boards
  arm64: defconfig: Enable IR SUNXI option

Igors Makejevs (1):
  arm64: dts: allwinner: a64: Add IR node

Jernej Skrabec (1):
  arm64: dts: allwinner: a64: Enable IR on Orange Pi Win

 .../devicetree/bindings/media/sunxi-ir.txt    | 11 ++-
 arch/arm/boot/dts/sun6i-a31.dtsi              |  2 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi             |  2 +-
 arch/arm/boot/dts/sun9i-a80.dtsi              |  2 +-
 arch/arm/boot/dts/sunxi-h3-h5.dtsi            |  2 +-
 .../dts/allwinner/sun50i-a64-orangepi-win.dts |  4 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++
 .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |  4 +
 .../dts/allwinner/sun50i-h6-orangepi.dtsi     |  4 +
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts |  4 +
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 19 ++++
 arch/arm64/configs/defconfig                  |  1 +
 drivers/media/rc/sunxi-cir.c                  | 88 ++++++++++++++-----
 13 files changed, 135 insertions(+), 26 deletions(-)

Comments

Maxime Ripard June 5, 2019, 9:49 a.m. UTC | #1 
On Tue, Jun 04, 2019 at 06:29:48PM +0200, Clément Péron wrote:
> This driver is used in various Allwinner SoC with different configuration.
>
> Introduce a quirks struct to know the fifo size and if a reset is required.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> Acked-by: Sean Young <sean@mess.org>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Maxime Ripard June 5, 2019, 9:49 a.m. UTC | #2 
On Tue, Jun 04, 2019 at 06:29:49PM +0200, Clément Péron wrote:
> Allwiner A31 has a different memory mapping so add the compatible
> we will need it later.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> Acked-by: Sean Young <sean@mess.org>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Maxime Ripard June 5, 2019, 9:51 a.m. UTC | #3 
On Tue, Jun 04, 2019 at 06:29:50PM +0200, Clément Péron wrote:
> We are using RXINT bits definition when looking at RXSTA register.
>
> These bits are equal but it's not really proper.
>
> Introduce the RXSTA bits and use them to have coherency.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> index 0504ebfc831f..572bd2257d35 100644
> --- a/drivers/media/rc/sunxi-cir.c
> +++ b/drivers/media/rc/sunxi-cir.c
> @@ -48,11 +48,11 @@
>
>  /* Rx Interrupt Enable */
>  #define SUNXI_IR_RXINT_REG    0x2C
> -/* Rx FIFO Overflow */
> +/* Rx FIFO Overflow Interrupt Enable */
>  #define REG_RXINT_ROI_EN		BIT(0)
> -/* Rx Packet End */
> +/* Rx Packet End Interrupt Enable */
>  #define REG_RXINT_RPEI_EN		BIT(1)
> -/* Rx FIFO Data Available */
> +/* Rx FIFO Data Available Interrupt Enable */
>  #define REG_RXINT_RAI_EN		BIT(4)
>
>  /* Rx FIFO available byte level */
> @@ -60,6 +60,12 @@
>
>  /* Rx Interrupt Status */
>  #define SUNXI_IR_RXSTA_REG    0x30
> +/* Rx FIFO Overflow */
> +#define REG_RXSTA_ROI			BIT(0)
> +/* Rx Packet End */
> +#define REG_RXSTA_RPE			BIT(1)
> +/* Rx FIFO Data Available */
> +#define REG_RXSTA_RA			BIT(4)

I'm fine with it on principle, but if the consistency needs to be
maintained then we could just reuse the above defines

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Clément Péron June 5, 2019, 12:44 p.m. UTC | #4 
Hi Maxime,

On Wed, 5 Jun 2019 at 11:51, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Tue, Jun 04, 2019 at 06:29:50PM +0200, Clément Péron wrote:
> > We are using RXINT bits definition when looking at RXSTA register.
> >
> > These bits are equal but it's not really proper.
> >
> > Introduce the RXSTA bits and use them to have coherency.
> >
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
> >  1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> > index 0504ebfc831f..572bd2257d35 100644
> > --- a/drivers/media/rc/sunxi-cir.c
> > +++ b/drivers/media/rc/sunxi-cir.c
> > @@ -48,11 +48,11 @@
> >
> >  /* Rx Interrupt Enable */
> >  #define SUNXI_IR_RXINT_REG    0x2C
> > -/* Rx FIFO Overflow */
> > +/* Rx FIFO Overflow Interrupt Enable */
> >  #define REG_RXINT_ROI_EN             BIT(0)
> > -/* Rx Packet End */
> > +/* Rx Packet End Interrupt Enable */
> >  #define REG_RXINT_RPEI_EN            BIT(1)
> > -/* Rx FIFO Data Available */
> > +/* Rx FIFO Data Available Interrupt Enable */
> >  #define REG_RXINT_RAI_EN             BIT(4)
> >
> >  /* Rx FIFO available byte level */
> > @@ -60,6 +60,12 @@
> >
> >  /* Rx Interrupt Status */
> >  #define SUNXI_IR_RXSTA_REG    0x30
> > +/* Rx FIFO Overflow */
> > +#define REG_RXSTA_ROI                        BIT(0)
> > +/* Rx Packet End */
> > +#define REG_RXSTA_RPE                        BIT(1)
> > +/* Rx FIFO Data Available */
> > +#define REG_RXSTA_RA                 BIT(4)
>
> I'm fine with it on principle, but if the consistency needs to be
> maintained then we could just reuse the above defines

There is no comment why we can reuse them, they can also be some wrong
case for example the RXINT_DRQ_EN bit is not present in RXSTA and same
for STAT bit present in RXSTA and not present in RXINT.

I have discover and read this code a month ago and this logic is
really not obvious nor explain.

Maybe this hack could be done when we will introduce a quirks, but for
the moment I really think that it's more proper and readable to
introduce them properly.

Regards,
Clément

>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Maxime Ripard June 5, 2019, 8 p.m. UTC | #5 
On Wed, Jun 05, 2019 at 02:44:06PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> On Wed, 5 Jun 2019 at 11:51, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Jun 04, 2019 at 06:29:50PM +0200, Clément Péron wrote:
> > > We are using RXINT bits definition when looking at RXSTA register.
> > >
> > > These bits are equal but it's not really proper.
> > >
> > > Introduce the RXSTA bits and use them to have coherency.
> > >
> > > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > > ---
> > >  drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
> > >  1 file changed, 12 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> > > index 0504ebfc831f..572bd2257d35 100644
> > > --- a/drivers/media/rc/sunxi-cir.c
> > > +++ b/drivers/media/rc/sunxi-cir.c
> > > @@ -48,11 +48,11 @@
> > >
> > >  /* Rx Interrupt Enable */
> > >  #define SUNXI_IR_RXINT_REG    0x2C
> > > -/* Rx FIFO Overflow */
> > > +/* Rx FIFO Overflow Interrupt Enable */
> > >  #define REG_RXINT_ROI_EN             BIT(0)
> > > -/* Rx Packet End */
> > > +/* Rx Packet End Interrupt Enable */
> > >  #define REG_RXINT_RPEI_EN            BIT(1)
> > > -/* Rx FIFO Data Available */
> > > +/* Rx FIFO Data Available Interrupt Enable */
> > >  #define REG_RXINT_RAI_EN             BIT(4)
> > >
> > >  /* Rx FIFO available byte level */
> > > @@ -60,6 +60,12 @@
> > >
> > >  /* Rx Interrupt Status */
> > >  #define SUNXI_IR_RXSTA_REG    0x30
> > > +/* Rx FIFO Overflow */
> > > +#define REG_RXSTA_ROI                        BIT(0)
> > > +/* Rx Packet End */
> > > +#define REG_RXSTA_RPE                        BIT(1)
> > > +/* Rx FIFO Data Available */
> > > +#define REG_RXSTA_RA                 BIT(4)
> >
> > I'm fine with it on principle, but if the consistency needs to be
> > maintained then we could just reuse the above defines
>
> There is no comment why we can reuse them, they can also be some wrong
> case for example the RXINT_DRQ_EN bit is not present in RXSTA and same
> for STAT bit present in RXSTA and not present in RXINT.
>
> I have discover and read this code a month ago and this logic is
> really not obvious nor explain.
>
> Maybe this hack could be done when we will introduce a quirks, but for
> the moment I really think that it's more proper and readable to
> introduce them properly.

I don't think we understood each other :)

I was talking about having something like

#define REG_RXSTA_ROI  REG_RXINT_ROI_EN

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Clément Péron June 5, 2019, 8:34 p.m. UTC | #6 
On Wed, 5 Jun 2019 at 22:00, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Wed, Jun 05, 2019 at 02:44:06PM +0200, Clément Péron wrote:
> > Hi Maxime,
> >
> > On Wed, 5 Jun 2019 at 11:51, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Tue, Jun 04, 2019 at 06:29:50PM +0200, Clément Péron wrote:
> > > > We are using RXINT bits definition when looking at RXSTA register.
> > > >
> > > > These bits are equal but it's not really proper.
> > > >
> > > > Introduce the RXSTA bits and use them to have coherency.
> > > >
> > > > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > > > ---
> > > >  drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
> > > >  1 file changed, 12 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> > > > index 0504ebfc831f..572bd2257d35 100644
> > > > --- a/drivers/media/rc/sunxi-cir.c
> > > > +++ b/drivers/media/rc/sunxi-cir.c
> > > > @@ -48,11 +48,11 @@
> > > >
> > > >  /* Rx Interrupt Enable */
> > > >  #define SUNXI_IR_RXINT_REG    0x2C
> > > > -/* Rx FIFO Overflow */
> > > > +/* Rx FIFO Overflow Interrupt Enable */
> > > >  #define REG_RXINT_ROI_EN             BIT(0)
> > > > -/* Rx Packet End */
> > > > +/* Rx Packet End Interrupt Enable */
> > > >  #define REG_RXINT_RPEI_EN            BIT(1)
> > > > -/* Rx FIFO Data Available */
> > > > +/* Rx FIFO Data Available Interrupt Enable */
> > > >  #define REG_RXINT_RAI_EN             BIT(4)
> > > >
> > > >  /* Rx FIFO available byte level */
> > > > @@ -60,6 +60,12 @@
> > > >
> > > >  /* Rx Interrupt Status */
> > > >  #define SUNXI_IR_RXSTA_REG    0x30
> > > > +/* Rx FIFO Overflow */
> > > > +#define REG_RXSTA_ROI                        BIT(0)
> > > > +/* Rx Packet End */
> > > > +#define REG_RXSTA_RPE                        BIT(1)
> > > > +/* Rx FIFO Data Available */
> > > > +#define REG_RXSTA_RA                 BIT(4)
> > >
> > > I'm fine with it on principle, but if the consistency needs to be
> > > maintained then we could just reuse the above defines
> >
> > There is no comment why we can reuse them, they can also be some wrong
> > case for example the RXINT_DRQ_EN bit is not present in RXSTA and same
> > for STAT bit present in RXSTA and not present in RXINT.
> >
> > I have discover and read this code a month ago and this logic is
> > really not obvious nor explain.
> >
> > Maybe this hack could be done when we will introduce a quirks, but for
> > the moment I really think that it's more proper and readable to
> > introduce them properly.
>
> I don't think we understood each other :)
>
> I was talking about having something like
>
> #define REG_RXSTA_ROI  REG_RXINT_ROI_EN
Ok, I will send an update.

Thanks for the review,
Clément


>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com