Message ID | 20190521125226.GS6820@bubble.grove.modra.org |
---|---|
State | New |
Headers | show |
Series | [RS6000] Don't pass -many to the assembler | expand |
Hi! On Tue, May 21, 2019 at 10:22:26PM +0930, Alan Modra wrote: > This is a repost of > https://gcc.gnu.org/ml/gcc-patches/2018-12/msg00911.html with a small > tweak to rs6000_machine_from_flags (&~ instead of ^). > > Bootstrapped and regression tested powerpc64le-linux power8 and > power9. OK to apply now that we're in stage1? > > * config/rs6000/rs6000.h (ASM_OPT_ANY): Define. > (ASM_CPU_SPEC): Conditionally add -many. > * config/rs6000/rs6000.c (rs6000_machine): New static var. > (rs6000_machine_from_flags, emit_asm_machine): New functions.. > (rs6000_file_start): ..extracted from here, and modified to > test all ISA bits. > (rs6000_output_function_prologue): Emit .machine as necessary. > * testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c: Don't use > power mnemonics. > * testsuite/gcc.dg/vect/O3-pr70130.c: Disable default options > added by check_vect_support_and_set_flags. > * testsuite/gcc.dg/vect/pr48765.c: Likewise. > * testsuite/gfortran.dg/vect/pr45714-b.f: Likewise. > +static const char * > +rs6000_machine_from_flags (void) > +{ > + if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) > + return "power9"; > + if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0) > + return "power8"; > + if ((rs6000_isa_flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0) > + return "power7"; > + if ((rs6000_isa_flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0) > + return "power6"; > + if ((rs6000_isa_flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0) > + return "power5"; > + if ((rs6000_isa_flags & ISA_2_1_MASKS) != 0) > + return "power4"; > + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0) > + return "ppc64"; > + return "ppc"; > +} As you know I'm trying to get rid of most of the separate user-selectable features we have currently. I think I'll steal this code :-) (Is Power5 2.4? Not 2.2?) > + { > + rs6000_output_savres_externs (file); > +#ifdef USING_ELFOS_H > + const char *curr_machine = rs6000_machine_from_flags (); > + if (rs6000_machine != curr_machine) > + { > + rs6000_machine = curr_machine; > + emit_asm_machine (); > + } > +#endif > + } Comparing fixed strings using ==... Not great. I'll change things to use an enum soon, so it's okay for now. > diff --git a/gcc/testsuite/gcc.dg/vect/O3-pr70130.c b/gcc/testsuite/gcc.dg/vect/O3-pr70130.c > index 18a295c83f0..f8b84405140 100644 > --- a/gcc/testsuite/gcc.dg/vect/O3-pr70130.c > +++ b/gcc/testsuite/gcc.dg/vect/O3-pr70130.c > @@ -1,5 +1,5 @@ > /* { dg-require-effective-target vsx_hw { target powerpc*-*-* } } */ > -/* { dg-additional-options "-mcpu=power7" { target powerpc*-*-* } } */ > +/* { dg-additional-options "-mcpu=power7 -mno-power9-vector -mno-power8-vector" { target powerpc*-*-* } } */ -mdejagnu-cpu=power7 should make the -mno-* things unnecessary I think? Hrm, I missed the few testcases outside gcc.target/powerpc/ when I did that. Please try that? Okay for trunk with that. Thanks! Segher
On Tue, May 21, 2019 at 09:48:10AM -0500, Segher Boessenkool wrote: > > +static const char * > > +rs6000_machine_from_flags (void) > > +{ > > + if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) > > + return "power9"; > > + if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0) > > + return "power8"; > > + if ((rs6000_isa_flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0) > > + return "power7"; > > + if ((rs6000_isa_flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0) > > + return "power6"; > > + if ((rs6000_isa_flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0) > > + return "power5"; > > + if ((rs6000_isa_flags & ISA_2_1_MASKS) != 0) > > + return "power4"; > > + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0) > > + return "ppc64"; > > + return "ppc"; > > +} > > As you know I'm trying to get rid of most of the separate user-selectable > features we have currently. I think I'll steal this code :-) > > (Is Power5 2.4? Not 2.2?) Yes, I think power5 was 2.02, but I haven't looked at cpu and arch books to verify exactly what power5 and power5+ was. Note that gas lumps power5 and power5+ in one category so "power5" from rs6000_machine_from_flags means power5+ too. This change was based on the fact that "friz" and other similar instructions enabled by gcc with TARGET_FPRND are enabled in gas by "-mpower5", "-mpwr5", or "-mpwr5x". ("-mpower5+" isn't a valid gas option.) rs6000-cpus.def puts OPTION_MASK_FPRND in ISA_2_4_MASKS, so ISA_2_4_MASKS is the one to use in deciding to pass "-mpower5" to gas. > -mdejagnu-cpu=power7 should make the -mno-* things unnecessary I think? No, it doesn't. The -mno- options are to counter options added by check_vect_support_and_set_flags based on hardware detection. On power8 hardware just switching to -mdejagnu-cpu results in, for example: ...xgcc -B.../ ...gcc.dg/vect/pr4875.c -fno-diagnostics-show-caret \ -fno-diagnostics-show-line-numbers -fdiagnostics-color=never -flto \ -ffat-lto-objects -maltivec -mpower8-vector -ftree-vectorize \ -fno-vect-cost-model -fno-common -O2 -fdump-tree-vect-details \ -O3 -mdejagnu-cpu=power6 -S -o pr48765.s
On Wed, May 22, 2019 at 12:56:15PM +0930, Alan Modra wrote: > On Tue, May 21, 2019 at 09:48:10AM -0500, Segher Boessenkool wrote: > > (Is Power5 2.4? Not 2.2?) > > Yes, I think power5 was 2.02, but I haven't looked at cpu and arch > books to verify exactly what power5 and power5+ was. My notes say p5 is 2.02 and p5+ is 2.04. > Note that gas > lumps power5 and power5+ in one category so "power5" from > rs6000_machine_from_flags means power5+ too. Gotcha, good to know. GCC can unfortunately not lump the two together, or code compiled for Power5 will not necessarily work on a Power5 anymore. For the few people who care, but hey. > This change was based on the fact that "friz" and other similar > instructions enabled by gcc with TARGET_FPRND are enabled in gas by > "-mpower5", "-mpwr5", or "-mpwr5x". ("-mpower5+" isn't a valid gas > option.) rs6000-cpus.def puts OPTION_MASK_FPRND in ISA_2_4_MASKS, so > ISA_2_4_MASKS is the one to use in deciding to pass "-mpower5" to > gas. FPRND is power5+, 2.04. > > -mdejagnu-cpu=power7 should make the -mno-* things unnecessary I think? > > No, it doesn't. The -mno- options are to counter options added by > check_vect_support_and_set_flags based on hardware detection. Yeah, I realised that later... Some later email I think. It seems that check_vect_support_and_set_flags will need some work (or the tests using it). Segher
Hello, I am sorry to come back to this thread after such a long time. I recently noticed that one of RTEMS multilibs is broken (for whatever reason it didn't show up in my regular build): /build/git-build/b-gcc-git-powerpc-rtems5/powerpc-rtems5/m8540/nof/libgcc (master) > make # If this is the top-level multilib, build all the other # multilibs. /build/git-build/b-gcc-git-powerpc-rtems5/./gcc/xgcc -B/build/git-build/b-gcc-git-powerpc-rtems5/./gcc/ -nostdinc -B/build/git-build/b-gcc-git-powerpc-rtems5/powerpc-rtems5/m8540/nof/newlib/ -isystem /build/git-build/b-gcc-git-powerpc-rtems5/powerpc-rtems5/m8540/nof/newlib/targ-include -isystem /home/EB/sebastian_h/archive/gcc-git/newlib/libc/include -B/opt/rtems/5/powerpc-rtems5/bin/ -B/opt/rtems/5/powerpc-rtems5/lib/ -isystem /opt/rtems/5/powerpc-rtems5/include -isystem /opt/rtems/5/powerpc-rtems5/sys-include -mcpu=8540 -msoft-float -g -O2 -O2 -I/home/EB/sebastian_h/archive/gcc-git/libgcc/../newlib/libc/sys/rtems/include -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -g -DIN_LIBGCC2 -fbuilding-libgcc -fno-stack-protector -Dinhibit_libc -I. -I. -I../../../.././gcc -I/home/EB/sebastian_h/archive/gcc-git/libgcc -I/home/EB/sebastian_h/archive/gcc-git/libgcc/. -I/home/EB/sebastian_h/archive/gcc-git/libgcc/../gcc -I/home/EB/sebastian_h/archive/gcc-git/libgcc/../include -DHAVE_CC_TLS -o crtsavfpr_s.o -MT crtsavfpr_s.o -MD -MP -MF crtsavfpr_s.dep -DSHARED -c -xassembler-with-cpp /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S: Assembler messages: /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:41: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:42: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:43: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:44: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:45: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:46: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:47: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:48: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:49: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:50: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:51: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:52: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:53: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:54: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:55: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:56: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:57: Error: unrecognized opcode: `stfd' /home/EB/sebastian_h/archive/gcc-git/libgcc/config/rs6000/crtsavfpr.S:58: Error: unrecognized opcode: `stfd' The assembler is called via: /build/git-build/b-gcc-git-powerpc-rtems5/./gcc/as --gdwarf2 -I /home/EB/sebastian_h/archive/gcc-git/libgcc/../newlib/libc/sys/rtems/include -I . -I . -I ../../../.././gcc -I /home/EB/sebastian_h/archive/gcc-git/libgcc -I /home/EB/sebastian_h/archive/gcc-git/libgcc/. -I /home/EB/sebastian_h/archive/gcc-git/libgcc/../gcc -I /home/EB/sebastian_h/archive/gcc-git/libgcc/../include -a32 -me500 -mbig -o crtsavfpr_s.o /tmp/cc6Fy8nn.s The e500 has no standard FPU. For this reason the multilib flags are: -mcpu=8540 -msoft-float What do you think about the attached patch?
Hi! On Mon, Apr 06, 2020 at 10:35:34PM +0200, Sebastian Huber wrote: > What do you think about the attached patch? (Please use a correct MIME type for attachments (x-* never is correct on mailing lists. Just text/plain will do fine.) > libgcc/ > > * config/rs6000/crtresfpr.S: Disable all functions if > _SOFT_DOUBLE is defined. Can't you just use an appropriate .machine? I'd prefer that, that's how AltiVec stuff is done, for example. > * config/rs6000/crtresxfpr.S: Likewise. > * config/rs6000/crtsavfpr.S: Likewise. (Broken indentation). > +/* On PowerPC64 Linux, these functions are provided by the linker. Soft-double > + * configurations do not need these functions. */ > +#if !defined(__powerpc64__) && !defined(_SOFT_DOUBLE) We use __NO_FPRS__ more often. All of these are the same now, but this name makes more sense as well ;-) Segher
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b5dc5f30f88..d27871ab907 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5664,6 +5664,36 @@ rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, /* Default CPU string for rs6000*_file_start functions. */ static const char *rs6000_default_cpu; +#ifdef USING_ELFOS_H +static const char *rs6000_machine; + +static const char * +rs6000_machine_from_flags (void) +{ + if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) + return "power9"; + if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0) + return "power8"; + if ((rs6000_isa_flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0) + return "power7"; + if ((rs6000_isa_flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0) + return "power6"; + if ((rs6000_isa_flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0) + return "power5"; + if ((rs6000_isa_flags & ISA_2_1_MASKS) != 0) + return "power4"; + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0) + return "ppc64"; + return "ppc"; +} + +static void +emit_asm_machine (void) +{ + fprintf (asm_out_file, "\t.machine %s\n", rs6000_machine); +} +#endif + /* Do anything needed at the start of the asm file. */ static void @@ -5729,27 +5759,10 @@ rs6000_file_start (void) } #ifdef USING_ELFOS_H + rs6000_machine = rs6000_machine_from_flags (); if (!(rs6000_default_cpu && rs6000_default_cpu[0]) && !global_options_set.x_rs6000_cpu_index) - { - fputs ("\t.machine ", asm_out_file); - if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0) - fputs ("power9\n", asm_out_file); - else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0) - fputs ("power8\n", asm_out_file); - else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0) - fputs ("power7\n", asm_out_file); - else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0) - fputs ("power6\n", asm_out_file); - else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0) - fputs ("power5\n", asm_out_file); - else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0) - fputs ("power4\n", asm_out_file); - else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0) - fputs ("ppc64\n", asm_out_file); - else - fputs ("ppc\n", asm_out_file); - } + emit_asm_machine (); #endif if (DEFAULT_ABI == ABI_ELFv2) @@ -27536,7 +27549,17 @@ static void rs6000_output_function_prologue (FILE *file) { if (!cfun->is_thunk) - rs6000_output_savres_externs (file); + { + rs6000_output_savres_externs (file); +#ifdef USING_ELFOS_H + const char *curr_machine = rs6000_machine_from_flags (); + if (rs6000_machine != curr_machine) + { + rs6000_machine = curr_machine; + emit_asm_machine (); + } +#endif + } /* ELFv2 ABI r2 setup code and local entry point. This must follow immediately after the global entry point label. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index eaf309b45b7..f435d8bf1db 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -70,6 +70,12 @@ #define PPC405_ERRATUM77 0 #endif +#if CHECKING_P +#define ASM_OPT_ANY "" +#else +#define ASM_OPT_ANY " -many" +#endif + /* Common ASM definitions used by ASM_SPEC among the various targets for handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to provide the default assembler options if the user uses -mcpu=native, so if @@ -137,8 +143,8 @@ mvsx: -mpower7; \ mpowerpc64: -mppc64;: %(asm_default)}; \ :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ -%{mvsx: -mvsx -maltivec; maltivec: -maltivec} \ --many" +%{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ +ASM_OPT_ANY #define CPP_DEFAULT_SPEC "" diff --git a/gcc/testsuite/gcc.dg/vect/O3-pr70130.c b/gcc/testsuite/gcc.dg/vect/O3-pr70130.c index 18a295c83f0..f8b84405140 100644 --- a/gcc/testsuite/gcc.dg/vect/O3-pr70130.c +++ b/gcc/testsuite/gcc.dg/vect/O3-pr70130.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target vsx_hw { target powerpc*-*-* } } */ -/* { dg-additional-options "-mcpu=power7" { target powerpc*-*-* } } */ +/* { dg-additional-options "-mcpu=power7 -mno-power9-vector -mno-power8-vector" { target powerpc*-*-* } } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/pr48765.c b/gcc/testsuite/gcc.dg/vect/pr48765.c index ae364379d07..b091a145d0f 100644 --- a/gcc/testsuite/gcc.dg/vect/pr48765.c +++ b/gcc/testsuite/gcc.dg/vect/pr48765.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ -/* { dg-additional-options "-O3 -mcpu=power6" } */ +/* { dg-additional-options "-O3 -mcpu=power6 -mno-power9-vector -mno-power8-vector -mno-vsx" } */ enum reg_class { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c b/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c index 14908dba690..eea7f6ffc2e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c @@ -45,14 +45,14 @@ __asm__ ("\t.globl\t" #NAME "_asm\n\t" \ #NAME "_asm:\n\t" \ "lis 11,gparms@ha\n\t" \ "la 11,gparms@l(11)\n\t" \ - "st 3,0(11)\n\t" \ - "st 4,4(11)\n\t" \ - "st 5,8(11)\n\t" \ - "st 6,12(11)\n\t" \ - "st 7,16(11)\n\t" \ - "st 8,20(11)\n\t" \ - "st 9,24(11)\n\t" \ - "st 10,28(11)\n\t" \ + "stw 3,0(11)\n\t" \ + "stw 4,4(11)\n\t" \ + "stw 5,8(11)\n\t" \ + "stw 6,12(11)\n\t" \ + "stw 7,16(11)\n\t" \ + "stw 8,20(11)\n\t" \ + "stw 9,24(11)\n\t" \ + "stw 10,28(11)\n\t" \ "stfd 1,32(11)\n\t" \ "stfd 2,40(11)\n\t" \ "stfd 3,48(11)\n\t" \ diff --git a/gcc/testsuite/gfortran.dg/vect/pr45714-b.f b/gcc/testsuite/gfortran.dg/vect/pr45714-b.f index 0d00c6fd666..abf33cd25b8 100644 --- a/gcc/testsuite/gfortran.dg/vect/pr45714-b.f +++ b/gcc/testsuite/gfortran.dg/vect/pr45714-b.f @@ -1,5 +1,5 @@ ! { dg-do compile { target powerpc*-*-* } } -! { dg-additional-options "-O3 -mcpu=power7 -ffast-math -mveclibabi=mass" } +! { dg-additional-options "-O3 -mcpu=power7 -mno-power9-vector -mno-power8-vector -ffast-math -mveclibabi=mass" } integer index(18),i,j,k,l,ipiv(18),info,ichange,neq,lda,ldb, & nrhs,iplas