| Message ID | 20190117103748.36613-8-anup.patel@wdc.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | SiFive FU540 Support | expand |
On 01/17/2019 11:39 AM, Anup Patel wrote: > This patch adds fixed-factor clock driver which derives clock > rate by dividing (div) and multiplying (mult) fixed factors > to a parent clock. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > drivers/clk/Makefile | 4 +- > drivers/clk/clk_fixed_factor.c | 74 ++++++++++++++++++++++++++++++++++ > 2 files changed, 77 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/clk_fixed_factor.c > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 2f4446568c..fa59259ea3 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -4,7 +4,9 @@ > # Wolfgang Denk, DENX Software Engineering, wd@denx.de. > # > > -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o > +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o > +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o > +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o > > obj-y += imx/ > obj-y += tegra/ > diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c > new file mode 100644 > index 0000000000..eab1724c26 > --- /dev/null > +++ b/drivers/clk/clk_fixed_factor.c > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2019 Western Digital Corporation or its affiliates. > + * > + * Author: Anup Patel <anup.patel@wdc.com> > + */ > + > +#include <common.h> > +#include <clk-uclass.h> > +#include <div64.h> > +#include <dm.h> > + > +struct clk_fixed_factor { > + struct clk parent; > + unsigned int div; > + unsigned int mult; > +}; > + > +#define to_clk_fixed_factor(dev) \ > + ((struct clk_fixed_factor *)dev_get_platdata(dev)) > + > +static ulong clk_fixed_factor_get_rate(struct clk *clk) > +{ > + int ret; > + struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); > + > + if (clk->id != 0) > + return -EINVAL; > + > + ret = clk_get_rate(&ff->parent); > + if (IS_ERR_VALUE(ret)) > + return ret; > + > + do_div(ret, ff->div); > + > + return ret * ff->mult; > +} > + > +const struct clk_ops clk_fixed_factor_ops = { > + .get_rate = clk_fixed_factor_get_rate, > +}; > + > +static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev) > +{ > +#if !CONFIG_IS_ENABLED(OF_PLATDATA) Why do you need this? Alex > + int err; > + struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); > + > + err = clk_get_by_index(dev, 0, &ff->parent); > + if (err) > + return err; > + > + ff->div = dev_read_u32_default(dev, "clock-div", 1); > + ff->mult = dev_read_u32_default(dev, "clock-mult", 1); > +#endif > + > + return 0; > +} > + > +static const struct udevice_id clk_fixed_factor_match[] = { > + { > + .compatible = "fixed-factor-clock", > + }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(clk_fixed_factor) = { > + .name = "fixed_factor_clock", > + .id = UCLASS_CLK, > + .of_match = clk_fixed_factor_match, > + .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata, > + .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor), > + .ops = &clk_fixed_factor_ops, > +};
> -----Original Message----- > From: Alexander Graf [mailto:agraf@suse.de] > Sent: Thursday, January 17, 2019 11:51 PM > To: Anup Patel <Anup.Patel@wdc.com>; Rick Chen <rick@andestech.com>; > Bin Meng <bmeng.cn@gmail.com>; Joe Hershberger > <joe.hershberger@ni.com>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; > Masahiro Yamada <yamada.masahiro@socionext.com>; Simon Glass > <sjg@chromium.org> > Cc: Palmer Dabbelt <palmer@sifive.com>; Paul Walmsley > <paul.walmsley@sifive.com>; Atish Patra <Atish.Patra@wdc.com>; > Christoph Hellwig <hch@infradead.org>; U-Boot Mailing List <u- > boot@lists.denx.de> > Subject: Re: [PATCH 07/11] clk: Add fixed-factor clock driver > > On 01/17/2019 11:39 AM, Anup Patel wrote: > > This patch adds fixed-factor clock driver which derives clock rate by > > dividing (div) and multiplying (mult) fixed factors to a parent clock. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > --- > > drivers/clk/Makefile | 4 +- > > drivers/clk/clk_fixed_factor.c | 74 > ++++++++++++++++++++++++++++++++++ > > 2 files changed, 77 insertions(+), 1 deletion(-) > > create mode 100644 drivers/clk/clk_fixed_factor.c > > > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > > 2f4446568c..fa59259ea3 100644 > > --- a/drivers/clk/Makefile > > +++ b/drivers/clk/Makefile > > @@ -4,7 +4,9 @@ > > # Wolfgang Denk, DENX Software Engineering, wd@denx.de. > > # > > > > -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o > > +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o > > +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o > > +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o > > > > obj-y += imx/ > > obj-y += tegra/ > > diff --git a/drivers/clk/clk_fixed_factor.c > > b/drivers/clk/clk_fixed_factor.c new file mode 100644 index > > 0000000000..eab1724c26 > > --- /dev/null > > +++ b/drivers/clk/clk_fixed_factor.c > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (c) 2019 Western Digital Corporation or its affiliates. > > + * > > + * Author: Anup Patel <anup.patel@wdc.com> */ > > + > > +#include <common.h> > > +#include <clk-uclass.h> > > +#include <div64.h> > > +#include <dm.h> > > + > > +struct clk_fixed_factor { > > + struct clk parent; > > + unsigned int div; > > + unsigned int mult; > > +}; > > + > > +#define to_clk_fixed_factor(dev) \ > > + ((struct clk_fixed_factor *)dev_get_platdata(dev)) > > + > > +static ulong clk_fixed_factor_get_rate(struct clk *clk) { > > + int ret; > > + struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); > > + > > + if (clk->id != 0) > > + return -EINVAL; > > + > > + ret = clk_get_rate(&ff->parent); > > + if (IS_ERR_VALUE(ret)) > > + return ret; > > + > > + do_div(ret, ff->div); > > + > > + return ret * ff->mult; > > +} > > + > > +const struct clk_ops clk_fixed_factor_ops = { > > + .get_rate = clk_fixed_factor_get_rate, }; > > + > > +static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev) { > > +#if !CONFIG_IS_ENABLED(OF_PLATDATA) > > Why do you need this? This is for boards/configuration where OF_PLATDATA is not enabled. For such boards, the board support code will provide platdata. I saw similar thing in clk_fixed_rate.c too hence kept it here. Do you want me to drop this "#if"? > > Alex > > > + int err; > > + struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); > > + > > + err = clk_get_by_index(dev, 0, &ff->parent); > > + if (err) > > + return err; > > + > > + ff->div = dev_read_u32_default(dev, "clock-div", 1); > > + ff->mult = dev_read_u32_default(dev, "clock-mult", 1); #endif > > + > > + return 0; > > +} > > + > > +static const struct udevice_id clk_fixed_factor_match[] = { > > + { > > + .compatible = "fixed-factor-clock", > > + }, > > + { /* sentinel */ } > > +}; > > + > > +U_BOOT_DRIVER(clk_fixed_factor) = { > > + .name = "fixed_factor_clock", > > + .id = UCLASS_CLK, > > + .of_match = clk_fixed_factor_match, > > + .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata, > > + .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor), > > + .ops = &clk_fixed_factor_ops, > > +}; Regards, Anup
On 01/18/2019 07:14 AM, Anup Patel wrote: > >> -----Original Message----- >> From: Alexander Graf [mailto:agraf@suse.de] >> Sent: Thursday, January 17, 2019 11:51 PM >> To: Anup Patel <Anup.Patel@wdc.com>; Rick Chen <rick@andestech.com>; >> Bin Meng <bmeng.cn@gmail.com>; Joe Hershberger >> <joe.hershberger@ni.com>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; >> Masahiro Yamada <yamada.masahiro@socionext.com>; Simon Glass >> <sjg@chromium.org> >> Cc: Palmer Dabbelt <palmer@sifive.com>; Paul Walmsley >> <paul.walmsley@sifive.com>; Atish Patra <Atish.Patra@wdc.com>; >> Christoph Hellwig <hch@infradead.org>; U-Boot Mailing List <u- >> boot@lists.denx.de> >> Subject: Re: [PATCH 07/11] clk: Add fixed-factor clock driver >> >> On 01/17/2019 11:39 AM, Anup Patel wrote: >>> This patch adds fixed-factor clock driver which derives clock rate by >>> dividing (div) and multiplying (mult) fixed factors to a parent clock. >>> >>> Signed-off-by: Anup Patel <anup.patel@wdc.com> >>> Signed-off-by: Atish Patra <atish.patra@wdc.com> >>> --- >>> drivers/clk/Makefile | 4 +- >>> drivers/clk/clk_fixed_factor.c | 74 >> ++++++++++++++++++++++++++++++++++ >>> 2 files changed, 77 insertions(+), 1 deletion(-) >>> create mode 100644 drivers/clk/clk_fixed_factor.c >>> >>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index >>> 2f4446568c..fa59259ea3 100644 >>> --- a/drivers/clk/Makefile >>> +++ b/drivers/clk/Makefile >>> @@ -4,7 +4,9 @@ >>> # Wolfgang Denk, DENX Software Engineering, wd@denx.de. >>> # >>> >>> -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o >>> +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o >>> +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o >>> +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o >>> >>> obj-y += imx/ >>> obj-y += tegra/ >>> diff --git a/drivers/clk/clk_fixed_factor.c >>> b/drivers/clk/clk_fixed_factor.c new file mode 100644 index >>> 0000000000..eab1724c26 >>> --- /dev/null >>> +++ b/drivers/clk/clk_fixed_factor.c >>> @@ -0,0 +1,74 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (c) 2019 Western Digital Corporation or its affiliates. >>> + * >>> + * Author: Anup Patel <anup.patel@wdc.com> */ >>> + >>> +#include <common.h> >>> +#include <clk-uclass.h> >>> +#include <div64.h> >>> +#include <dm.h> >>> + >>> +struct clk_fixed_factor { >>> + struct clk parent; >>> + unsigned int div; >>> + unsigned int mult; >>> +}; >>> + >>> +#define to_clk_fixed_factor(dev) \ >>> + ((struct clk_fixed_factor *)dev_get_platdata(dev)) >>> + >>> +static ulong clk_fixed_factor_get_rate(struct clk *clk) { >>> + int ret; >>> + struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); >>> + >>> + if (clk->id != 0) >>> + return -EINVAL; >>> + >>> + ret = clk_get_rate(&ff->parent); >>> + if (IS_ERR_VALUE(ret)) >>> + return ret; >>> + >>> + do_div(ret, ff->div); >>> + >>> + return ret * ff->mult; >>> +} >>> + >>> +const struct clk_ops clk_fixed_factor_ops = { >>> + .get_rate = clk_fixed_factor_get_rate, }; >>> + >>> +static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev) { >>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA) >> Why do you need this? > This is for boards/configuration where OF_PLATDATA is not enabled. For such boards, the board support code will provide platdata. > > I saw similar thing in clk_fixed_rate.c too hence kept it here. Do you want me to drop this "#if"? I would prefer if we don't advocate OF_PLATDATA more than we have to. So I'm all for making it harder to use it :). In other words, yes, please drop support for it for now. Alex
> -----Original Message----- > From: Alexander Graf [mailto:agraf@suse.de] > Sent: Monday, January 21, 2019 7:49 PM > To: Anup Patel <Anup.Patel@wdc.com>; Rick Chen <rick@andestech.com>; > Bin Meng <bmeng.cn@gmail.com>; Joe Hershberger > <joe.hershberger@ni.com>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; > Masahiro Yamada <yamada.masahiro@socionext.com>; Simon Glass > <sjg@chromium.org> > Cc: Palmer Dabbelt <palmer@sifive.com>; Paul Walmsley > <paul.walmsley@sifive.com>; Atish Patra <Atish.Patra@wdc.com>; > Christoph Hellwig <hch@infradead.org>; U-Boot Mailing List <u- > boot@lists.denx.de> > Subject: Re: [PATCH 07/11] clk: Add fixed-factor clock driver > > On 01/18/2019 07:14 AM, Anup Patel wrote: > > > >> -----Original Message----- > >> From: Alexander Graf [mailto:agraf@suse.de] > >> Sent: Thursday, January 17, 2019 11:51 PM > >> To: Anup Patel <Anup.Patel@wdc.com>; Rick Chen > <rick@andestech.com>; > >> Bin Meng <bmeng.cn@gmail.com>; Joe Hershberger > >> <joe.hershberger@ni.com>; Lukas Auer > >> <lukas.auer@aisec.fraunhofer.de>; Masahiro Yamada > >> <yamada.masahiro@socionext.com>; Simon Glass <sjg@chromium.org> > >> Cc: Palmer Dabbelt <palmer@sifive.com>; Paul Walmsley > >> <paul.walmsley@sifive.com>; Atish Patra <Atish.Patra@wdc.com>; > >> Christoph Hellwig <hch@infradead.org>; U-Boot Mailing List <u- > >> boot@lists.denx.de> > >> Subject: Re: [PATCH 07/11] clk: Add fixed-factor clock driver > >> > >> On 01/17/2019 11:39 AM, Anup Patel wrote: > >>> This patch adds fixed-factor clock driver which derives clock rate > >>> by dividing (div) and multiplying (mult) fixed factors to a parent clock. > >>> > >>> Signed-off-by: Anup Patel <anup.patel@wdc.com> > >>> Signed-off-by: Atish Patra <atish.patra@wdc.com> > >>> --- > >>> drivers/clk/Makefile | 4 +- > >>> drivers/clk/clk_fixed_factor.c | 74 > >> ++++++++++++++++++++++++++++++++++ > >>> 2 files changed, 77 insertions(+), 1 deletion(-) > >>> create mode 100644 drivers/clk/clk_fixed_factor.c > >>> > >>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > >>> 2f4446568c..fa59259ea3 100644 > >>> --- a/drivers/clk/Makefile > >>> +++ b/drivers/clk/Makefile > >>> @@ -4,7 +4,9 @@ > >>> # Wolfgang Denk, DENX Software Engineering, wd@denx.de. > >>> # > >>> > >>> -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o > >>> +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o > >>> +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o > >>> +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o > >>> > >>> obj-y += imx/ > >>> obj-y += tegra/ > >>> diff --git a/drivers/clk/clk_fixed_factor.c > >>> b/drivers/clk/clk_fixed_factor.c new file mode 100644 index > >>> 0000000000..eab1724c26 > >>> --- /dev/null > >>> +++ b/drivers/clk/clk_fixed_factor.c > >>> @@ -0,0 +1,74 @@ > >>> +// SPDX-License-Identifier: GPL-2.0+ > >>> +/* > >>> + * Copyright (c) 2019 Western Digital Corporation or its affiliates. > >>> + * > >>> + * Author: Anup Patel <anup.patel@wdc.com> */ > >>> + > >>> +#include <common.h> > >>> +#include <clk-uclass.h> > >>> +#include <div64.h> > >>> +#include <dm.h> > >>> + > >>> +struct clk_fixed_factor { > >>> + struct clk parent; > >>> + unsigned int div; > >>> + unsigned int mult; > >>> +}; > >>> + > >>> +#define to_clk_fixed_factor(dev) \ > >>> + ((struct clk_fixed_factor *)dev_get_platdata(dev)) > >>> + > >>> +static ulong clk_fixed_factor_get_rate(struct clk *clk) { > >>> + int ret; > >>> + struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); > >>> + > >>> + if (clk->id != 0) > >>> + return -EINVAL; > >>> + > >>> + ret = clk_get_rate(&ff->parent); > >>> + if (IS_ERR_VALUE(ret)) > >>> + return ret; > >>> + > >>> + do_div(ret, ff->div); > >>> + > >>> + return ret * ff->mult; > >>> +} > >>> + > >>> +const struct clk_ops clk_fixed_factor_ops = { > >>> + .get_rate = clk_fixed_factor_get_rate, }; > >>> + > >>> +static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev) > >>> +{ #if !CONFIG_IS_ENABLED(OF_PLATDATA) > >> Why do you need this? > > This is for boards/configuration where OF_PLATDATA is not enabled. For > such boards, the board support code will provide platdata. > > > > I saw similar thing in clk_fixed_rate.c too hence kept it here. Do you want > me to drop this "#if"? > > I would prefer if we don't advocate OF_PLATDATA more than we have to. So > I'm all for making it harder to use it :). In other words, yes, please drop > support for it for now. Okay, I will drop the "#if". Regards, Anup
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2f4446568c..fa59259ea3 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -4,7 +4,9 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o obj-y += imx/ obj-y += tegra/ diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c new file mode 100644 index 0000000000..eab1724c26 --- /dev/null +++ b/drivers/clk/clk_fixed_factor.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Author: Anup Patel <anup.patel@wdc.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> + +struct clk_fixed_factor { + struct clk parent; + unsigned int div; + unsigned int mult; +}; + +#define to_clk_fixed_factor(dev) \ + ((struct clk_fixed_factor *)dev_get_platdata(dev)) + +static ulong clk_fixed_factor_get_rate(struct clk *clk) +{ + int ret; + struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); + + if (clk->id != 0) + return -EINVAL; + + ret = clk_get_rate(&ff->parent); + if (IS_ERR_VALUE(ret)) + return ret; + + do_div(ret, ff->div); + + return ret * ff->mult; +} + +const struct clk_ops clk_fixed_factor_ops = { + .get_rate = clk_fixed_factor_get_rate, +}; + +static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int err; + struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); + + err = clk_get_by_index(dev, 0, &ff->parent); + if (err) + return err; + + ff->div = dev_read_u32_default(dev, "clock-div", 1); + ff->mult = dev_read_u32_default(dev, "clock-mult", 1); +#endif + + return 0; +} + +static const struct udevice_id clk_fixed_factor_match[] = { + { + .compatible = "fixed-factor-clock", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(clk_fixed_factor) = { + .name = "fixed_factor_clock", + .id = UCLASS_CLK, + .of_match = clk_fixed_factor_match, + .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor), + .ops = &clk_fixed_factor_ops, +};