| Message ID | 20181211150221.62514-3-anup@brainfault.org |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | SiFive UART support | expand |
On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote: > > This patch enables SiFive UART driver for QEMU RISC-V emulation > by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS. > > Signed-off-by: Anup Patel <anup@brainfault.org> > --- > board/emulation/qemu-riscv/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 56bb5337d4..436db01a53 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -32,5 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply BOARD_LATE_INIT imply OF_BOARD_SETUP + imply SIFIVE_SERIAL endif
This patch enables SiFive UART driver for QEMU RISC-V emulation by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS. Signed-off-by: Anup Patel <anup@brainfault.org> --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)