| Message ID | 20181211150221.62514-1-anup@brainfault.org |
|---|---|
| Headers | show |
| Series | SiFive UART support | expand |
Hi Anup, On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote: > > This patchset adds SiFive UART driver for SiFive UART > found on SiFive boards. > > The driver is tested on QEMU sifive_u machine. In fact, > with this patchset same U-Boot binary boots on QEMU virt > machine and QEMU sifive_u machine in both M-mode and > S-mode. > Could you please specify how to test this? I tried your v1 patch but U-Boot did not boot. I must have missed something ... > The patches are based upon latest RISC-V UBoot tree > (git://git.denx.de/u-boot-riscv.git) at commit id > 48cbf6246052de10d35b616b5efb2f783904a49d > > Changes since v1: > - Fixed copyright header in SiFive UART driver > - Imply SIFIVE_SERIAL for QEMU emulation instead > of enabling it in defconfigs. > Regards, Bin
On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Anup, > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote: > > > > This patchset adds SiFive UART driver for SiFive UART > > found on SiFive boards. > > > > The driver is tested on QEMU sifive_u machine. In fact, > > with this patchset same U-Boot binary boots on QEMU virt > > machine and QEMU sifive_u machine in both M-mode and > > S-mode. > > > > Could you please specify how to test this? I tried your v1 patch but > U-Boot did not boot. I must have missed something ... To try this patches in M-mode do the following (in u-boot source directory): # ARCH=riscv # CROSS_COMPILE=riscv64-unknown-linux-gnu- # make qemu-riscv64_defconfig # make # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio -kernel ./u-boot OR # qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -kernel ./u-boot Regards, Anup
Hi Anup, On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > Hi Anup, > > > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote: > > > > > > This patchset adds SiFive UART driver for SiFive UART > > > found on SiFive boards. > > > > > > The driver is tested on QEMU sifive_u machine. In fact, > > > with this patchset same U-Boot binary boots on QEMU virt > > > machine and QEMU sifive_u machine in both M-mode and > > > S-mode. > > > > > > > Could you please specify how to test this? I tried your v1 patch but > > U-Boot did not boot. I must have missed something ... > > To try this patches in M-mode do the following (in u-boot source directory): > # ARCH=riscv > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > # make qemu-riscv64_defconfig > # make > # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio > -kernel ./u-boot I tried exactly the same, but no console output. > OR > # qemu-system-riscv64 -M virt -m 256M -display none -serial stdio > -kernel ./u-boot > Regards, Bin
On Tue, Dec 11, 2018 at 9:45 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Anup, > > On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup@brainfault.org> wrote: > > > > On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > Hi Anup, > > > > > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote: > > > > > > > > This patchset adds SiFive UART driver for SiFive UART > > > > found on SiFive boards. > > > > > > > > The driver is tested on QEMU sifive_u machine. In fact, > > > > with this patchset same U-Boot binary boots on QEMU virt > > > > machine and QEMU sifive_u machine in both M-mode and > > > > S-mode. > > > > > > > > > > Could you please specify how to test this? I tried your v1 patch but > > > U-Boot did not boot. I must have missed something ... > > > > To try this patches in M-mode do the following (in u-boot source directory): > > # ARCH=riscv > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > # make qemu-riscv64_defconfig > > # make > > # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio > > -kernel ./u-boot > > I tried exactly the same, but no console output. > Ahh, understood your problem. There is a bug in QEMU FDT generation for sifive_u. Here's the QEMU fix (which I have send to QEMU mailing list): Return-Path: <anup@brainfault.org> Received: from anup-ubuntu64.qualcomm.com ([49.207.50.107]) by smtp.googlemail.com with ESMTPSA id 19sm33410406pfs.108.2018.12.05.00.27.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 00:27:15 -0800 (PST) From: Anup Patel <anup@brainfault.org> To: qemu-riscv@nongnu.org Cc: Anup Patel <anup@brainfault.org> Subject: [PATCH 2/2] hw/riscv/sifive_u: Set 'clock-frequency' DT property for SiFive UART Date: Wed, 5 Dec 2018 13:57:03 +0530 Message-Id: <20181205082703.13945-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181205082703.13945-1-anup@brainfault.org> References: <20181205082703.13945-1-anup@brainfault.org> The 'clock-frequency' DT property is required by U-Boot to compute divider value. This patch sets 'clock-frequency' DT property of SiFive UART DT node (similar to virt machine). Signed-off-by: Anup Patel <anup@brainfault.org> --- hw/riscv/sifive_u.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b3a4352986..5fa666fefc 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -238,6 +238,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ / 2); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
On Wed, Dec 12, 2018 at 12:20 AM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Dec 11, 2018 at 9:45 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > Hi Anup, > > > > On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup@brainfault.org> wrote: > > > > > > On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > Hi Anup, > > > > > > > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote: > > > > > > > > > > This patchset adds SiFive UART driver for SiFive UART > > > > > found on SiFive boards. > > > > > > > > > > The driver is tested on QEMU sifive_u machine. In fact, > > > > > with this patchset same U-Boot binary boots on QEMU virt > > > > > machine and QEMU sifive_u machine in both M-mode and > > > > > S-mode. > > > > > > > > > > > > > Could you please specify how to test this? I tried your v1 patch but > > > > U-Boot did not boot. I must have missed something ... > > > > > > To try this patches in M-mode do the following (in u-boot source directory): > > > # ARCH=riscv > > > # CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > # make qemu-riscv64_defconfig > > > # make > > > # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio > > > -kernel ./u-boot > > > > I tried exactly the same, but no console output. > > > > Ahh, understood your problem. > > There is a bug in QEMU FDT generation for sifive_u. > > Here's the QEMU fix (which I have send to QEMU mailing list): > With the new info, now I am able to boot U-Boot on QEMU sifive_u. Regards, Bin
On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote: > > This patchset adds SiFive UART driver for SiFive UART > found on SiFive boards. > > The driver is tested on QEMU sifive_u machine. In fact, > with this patchset same U-Boot binary boots on QEMU virt > machine and QEMU sifive_u machine in both M-mode and > S-mode. > > The patches are based upon latest RISC-V UBoot tree > (git://git.denx.de/u-boot-riscv.git) at commit id > 48cbf6246052de10d35b616b5efb2f783904a49d > > Changes since v1: > - Fixed copyright header in SiFive UART driver > - Imply SIFIVE_SERIAL for QEMU emulation instead > of enabling it in defconfigs. > > Anup Patel (2): > drivers: serial: Add SiFive UART driver > riscv: qemu: Imply SIFIVE_SERIAL for emulation > > board/emulation/qemu-riscv/Kconfig | 1 + > drivers/serial/Kconfig | 13 ++ > drivers/serial/Makefile | 1 + > drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++ > 4 files changed, 206 insertions(+) > create mode 100644 drivers/serial/serial_sifive.c > > -- > 2.17.1 > Hi Rick, The required QEMU fix has been submitted by Alistair Francis on QEMU mailing list. (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive UART") Can you please consider this series for U-Boot v2019.01? Thanks, Anup
Hi Anup > > From: Anup Patel [mailto:anup@brainfault.org] > > Sent: Friday, December 14, 2018 5:23 PM > > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer > > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot > > Mailing List > > Subject: Re: [PATCH v2 0/2] SiFive UART support > > > > On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote: > > > > > > This patchset adds SiFive UART driver for SiFive UART found on SiFive > > > boards. > > > > > > The driver is tested on QEMU sifive_u machine. In fact, with this > > > patchset same U-Boot binary boots on QEMU virt machine and QEMU > > > sifive_u machine in both M-mode and S-mode. > > > > > > The patches are based upon latest RISC-V UBoot tree > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > 48cbf6246052de10d35b616b5efb2f783904a49d > > > > > > Changes since v1: > > > - Fixed copyright header in SiFive UART driver > > > - Imply SIFIVE_SERIAL for QEMU emulation instead > > > of enabling it in defconfigs. > > > > > > Anup Patel (2): > > > drivers: serial: Add SiFive UART driver > > > riscv: qemu: Imply SIFIVE_SERIAL for emulation > > > > > > board/emulation/qemu-riscv/Kconfig | 1 + > > > drivers/serial/Kconfig | 13 ++ > > > drivers/serial/Makefile | 1 + > > > drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++ > > > 4 files changed, 206 insertions(+) > > > create mode 100644 drivers/serial/serial_sifive.c > > > > > > -- > > > 2.17.1 > > > > > > > Hi Rick, > > > > The required QEMU fix has been submitted by Alistair Francis on QEMU mailing > > list. > > (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive > > UART") > > > > Can you please consider this series for U-Boot v2019.01? > > OK I will include yours in this PR. B.R Rick > > Thanks, > > Anup
On Mon, Dec 17, 2018 at 7:21 AM Rick Chen <rickchen36@gmail.com> wrote: > > Hi Anup > > > > From: Anup Patel [mailto:anup@brainfault.org] > > > Sent: Friday, December 14, 2018 5:23 PM > > > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer > > > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot > > > Mailing List > > > Subject: Re: [PATCH v2 0/2] SiFive UART support > > > > > > On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote: > > > > > > > > This patchset adds SiFive UART driver for SiFive UART found on SiFive > > > > boards. > > > > > > > > The driver is tested on QEMU sifive_u machine. In fact, with this > > > > patchset same U-Boot binary boots on QEMU virt machine and QEMU > > > > sifive_u machine in both M-mode and S-mode. > > > > > > > > The patches are based upon latest RISC-V UBoot tree > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > 48cbf6246052de10d35b616b5efb2f783904a49d > > > > > > > > Changes since v1: > > > > - Fixed copyright header in SiFive UART driver > > > > - Imply SIFIVE_SERIAL for QEMU emulation instead > > > > of enabling it in defconfigs. > > > > > > > > Anup Patel (2): > > > > drivers: serial: Add SiFive UART driver > > > > riscv: qemu: Imply SIFIVE_SERIAL for emulation > > > > > > > > board/emulation/qemu-riscv/Kconfig | 1 + > > > > drivers/serial/Kconfig | 13 ++ > > > > drivers/serial/Makefile | 1 + > > > > drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++ > > > > 4 files changed, 206 insertions(+) > > > > create mode 100644 drivers/serial/serial_sifive.c > > > > > > > > -- > > > > 2.17.1 > > > > > > > > > > Hi Rick, > > > > > > The required QEMU fix has been submitted by Alistair Francis on QEMU mailing > > > list. > > > (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive > > > UART") > > > > > > Can you please consider this series for U-Boot v2019.01? > > > > > OK > I will include yours in this PR. I have send v3 of this patch. Please include that. Thanks, Anup
Hi Anup Anup Patel <anup@brainfault.org> 於 2018年12月17日 週一 下午12:15寫道： > > On Mon, Dec 17, 2018 at 7:21 AM Rick Chen <rickchen36@gmail.com> wrote: > > > > Hi Anup > > > > > > From: Anup Patel [mailto:anup@brainfault.org] > > > > Sent: Friday, December 14, 2018 5:23 PM > > > > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer > > > > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot > > > > Mailing List > > > > Subject: Re: [PATCH v2 0/2] SiFive UART support > > > > > > > > On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote: > > > > > > > > > > This patchset adds SiFive UART driver for SiFive UART found on SiFive > > > > > boards. > > > > > > > > > > The driver is tested on QEMU sifive_u machine. In fact, with this > > > > > patchset same U-Boot binary boots on QEMU virt machine and QEMU > > > > > sifive_u machine in both M-mode and S-mode. > > > > > > > > > > The patches are based upon latest RISC-V UBoot tree > > > > > (git://git.denx.de/u-boot-riscv.git) at commit id > > > > > 48cbf6246052de10d35b616b5efb2f783904a49d > > > > > > > > > > Changes since v1: > > > > > - Fixed copyright header in SiFive UART driver > > > > > - Imply SIFIVE_SERIAL for QEMU emulation instead > > > > > of enabling it in defconfigs. > > > > > > > > > > Anup Patel (2): > > > > > drivers: serial: Add SiFive UART driver > > > > > riscv: qemu: Imply SIFIVE_SERIAL for emulation > > > > > > > > > > board/emulation/qemu-riscv/Kconfig | 1 + > > > > > drivers/serial/Kconfig | 13 ++ > > > > > drivers/serial/Makefile | 1 + > > > > > drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++ > > > > > 4 files changed, 206 insertions(+) > > > > > create mode 100644 drivers/serial/serial_sifive.c > > > > > > > > > > -- > > > > > 2.17.1 > > > > > > > > > > > > > Hi Rick, > > > > > > > > The required QEMU fix has been submitted by Alistair Francis on QEMU mailing > > > > list. > > > > (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive > > > > UART") > > > > > > > > Can you please consider this series for U-Boot v2019.01? > > > > > > > > OK > > I will include yours in this PR. > > I have send v3 of this patch. Please include that. > Yes. I fetch your v3 and apply to u-boot-riscv.git. Travis is verifying. Then I will send a PR later. B.R Rick > Thanks, > Anup