Message ID | 5BFC2F2F.70104@foss.arm.com |
---|---|
State | New |
Headers | show |
Series | [arm,1/3] Rename mul64 attr to widen_mul64 | expand |
On Mon, Nov 26, 2018 at 11:36:47AM -0600, Kyrill Tkachov wrote: > Hi all, > > On some cores the X-register MADD/MSUB (and hence MUL and MNEG) instructions may behave differently > than the W-register forms and the scheduling models may want to reflect that. > That is currently not possible because both sizes use the mla scheduling type. > > This patch introduces the mla64 type that is used to represent the 64-bit MADD,MSUB,MUL,MNEG instructions. > It annotates the necessary aarch64.md patterns and updates the existing aarch64 scheduling models to handle it. > It is currently handled the same way as the 32-bit forms so as not to introduce a difference in behaviour. > However, now we have the freedom to model it differently, if we so choose. > Sameera, Steve, Philipp, this is an FYI that you can update the relevant .md files to model these instructions > in a more precise way, if warranted (if this is approved.) > > Bootstrapped and tested on aarch64-none-linux (and tested on arm-none-eabi). > > Ok for trunk? OK for AArch64. You can self-approve the Arm part. James > 2018-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com> > > * config/arm/types.md (mla64): New type. > * config/arm/xgene1.md: Handle mla64. > * config/arm/cortex-a57.md: Likewise. > * config/arm/cortex-a53.md: Likewise. > * config/aarch64/thunderx2t99.md: Likewise. > * config/aarch64/thunderx.md: Likewise. > * config/aarch64/falkor.md: Likewise. > * config/aarch64/saphira.md: Likewise. > * config/aarch64/iterators.md (is_64_suf): New mode attribute. > * config/aarch64/aarch64.md (mul<mode>3): Use is_64_suf in type. > (madd<mode>): Likewise. > (*msub<mode>): Likewise. > (*mul<mode>_neg): Likewise.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 73559b52ac24c58a8e23a297eac6d9a58b37b8fe..b2d8a99f4969ff0cb3fb577451b3096a4a684662 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3385,7 +3385,7 @@ (define_insn "mul<mode>3" (match_operand:GPI 2 "register_operand" "r")))] "" "mul\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "mla")] + [(set_attr "type" "mla<is_64_suf>")] ) ;; zero_extend version of above @@ -3406,7 +3406,7 @@ (define_insn "madd<mode>" (match_operand:GPI 3 "register_operand" "r")))] "" "madd\\t%<w>0, %<w>1, %<w>2, %<w>3" - [(set_attr "type" "mla")] + [(set_attr "type" "mla<is_64_suf>")] ) ;; zero_extend version of above @@ -3429,7 +3429,7 @@ (define_insn "*msub<mode>" "" "msub\\t%<w>0, %<w>1, %<w>2, %<w>3" - [(set_attr "type" "mla")] + [(set_attr "type" "mla<is_64_suf>")] ) ;; zero_extend version of above @@ -3452,7 +3452,7 @@ (define_insn "*mul<mode>_neg" "" "mneg\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "mla")] + [(set_attr "type" "mla<is_64_suf>")] ) ;; zero_extend version of above diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md index 45cbff93b24fc516806662dfeb63e4286b0e95cd..76fe908b8079b1879fac3ec15a7f44064a5d1dd4 100644 --- a/gcc/config/aarch64/falkor.md +++ b/gcc/config/aarch64/falkor.md @@ -616,7 +616,7 @@ (define_insn_reservation "falkor_muldiv_4_x_mul" 4 (define_insn_reservation "falkor_muldiv_4_x_mla" 4 (and (eq_attr "tune" "falkor") - (eq_attr "type" "mla,smlal,umlal")) + (eq_attr "type" "mla,mla64,smlal,umlal")) "falkor_x") (define_insn_reservation "falkor_muldiv_5_x_mul" 5 diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 142914ad80d0f1be29433d4479bd767f875e6bd2..cd1c2fa8ce2848699591798295f4339185b1902d 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -600,6 +600,9 @@ (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) +;; Return "64" for DImode and nothing for other modes +(define_mode_attr is_64_suf [(SI "") (DI "64")]) + ;; Give the ordinal of the MSB in the mode (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")]) diff --git a/gcc/config/aarch64/saphira.md b/gcc/config/aarch64/saphira.md index ff1a13a0ec5f90087b73e12bc15c70df1d2f8fab..a61ce8e7cb34205cd2b21e5b9734aa668ee88da2 100644 --- a/gcc/config/aarch64/saphira.md +++ b/gcc/config/aarch64/saphira.md @@ -493,7 +493,7 @@ (define_insn_reservation "saphira_muldiv_4_x_mul" 4 (define_insn_reservation "saphira_muldiv_4_x_mla" 4 (and (eq_attr "tune" "saphira") - (eq_attr "type" "mla,smlal,umlal")) + (eq_attr "type" "mla,mla64,smlal,umlal")) "saphira_x") (define_insn_reservation "saphira_muldiv_5_x_mul" 5 diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index df55db8bb0cf0b84f4803ad3afe52a5844037d35..8bbf1d687d1c3e504e54f6f8e1655b41f1059b95 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -63,7 +63,7 @@ (define_insn_reservation "thunderx_csel" 2 (define_insn_reservation "thunderx_mul" 4 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "mul,muls,mla,mlas,clz,smull,umull,smlal,umlal")) + (eq_attr "type" "mul,muls,mla,mla64,mlas,clz,smull,umull,smlal,umlal")) "thunderx_pipe1 + thunderx_mult") ;; crcb,crch,crcw is 4 cycles and can only happen on pipe 1 diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index fb71de55eeca67573323b5f6c9e37af4097913df..3170651f714040e427e92d69e4054f7cbae27440 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -121,7 +121,7 @@ (define_insn_reservation "thunderx2t99_div" 13 (define_insn_reservation "thunderx2t99_madd" 5 (and (eq_attr "tune" "thunderx2t99") - (eq_attr "type" "mla,smlal,umlal")) + (eq_attr "type" "mla,mla64,smlal,umlal")) "thunderx2t99_i1,thunderx2t99_i1m1,thunderx2t99_i1m2,thunderx2t99_i1m3,\ thunderx2t99_i012") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 5e9fa88c4a15c0c8d9f0e54e9f0c740317234467..8921eaa3410de4c7e13f722ff5eeaba3d68cb50f 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -111,7 +111,8 @@ (define_insn_reservation "cortex_a53_alu_extr" 3 (define_insn_reservation "cortex_a53_mul" 4 (and (eq_attr "tune" "cortexa53") (ior (eq_attr "mul32" "yes") - (eq_attr "widen_mul64" "yes"))) + (eq_attr "widen_mul64" "yes")) + (eq_attr "type" "mla64")) "cortex_a53_slot_any+cortex_a53_imul") ;; From the perspective of the GCC scheduling state machine, if we wish to diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index 89e322cc248c239b00b1328f2e0fc9d59dccc298..75ca6daea904f497fbb24cc5d8d90af70074bee3 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -328,7 +328,8 @@ (define_insn_reservation "cortex_a57_alu_shift_reg" 3 (define_insn_reservation "cortex_a57_mult32" 3 (and (eq_attr "tune" "cortexa57") (ior (eq_attr "mul32" "yes") - (eq_attr "widen_mul64" "yes"))) + (eq_attr "widen_mul64" "yes") + (eq_attr "type" "mla64"))) "ca57_mx") ;; Integer divide diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 3f10367545cc9b9b4f54340dcd9873df5b6ca95b..3d583a771e3cb2d95948ce8119963826a62429f3 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -102,6 +102,7 @@ ; logics_shift_imm as logic_shift_imm, setting condition flags. ; logics_shift_reg as logic_shift_reg, setting condition flags. ; mla integer multiply accumulate. +; mla64 integer 64-bit multiply accumulate. Used only on AArch64. ; mlas integer multiply accumulate, flag setting. ; mov_imm simple MOV instruction that moves an immediate to ; register. This includes MOVW, but not MOVT. @@ -628,6 +629,7 @@ (define_attr "type" logics_shift_imm,\ logics_shift_reg,\ mla,\ + mla64,\ mlas,\ mov_imm,\ mov_reg,\ diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index 893cb37e4bb93687de08b4d2b63848f9432b1252..e918707761999ebb4eb5ce3e92c421908fd3c4a9 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -166,7 +166,8 @@ (define_bypass 2 "xgene1_alus" (define_insn_reservation "xgene1_mul32" 4 (and (eq_attr "tune" "xgene1") - (eq_attr "mul32" "yes")) + (ior (eq_attr "type" "mla64") + (eq_attr "mul32" "yes"))) "xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing, xgene1_IXB_compl") (define_insn_reservation "xgene1_widen_mul64" 5