| Message ID | 20181019220743.15020-5-lukas.auer@aisec.fraunhofer.de |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | General fixes / cleanup for RISC-V and improvements to qemu-riscv | expand |
Hi Lukas, On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer <lukas.auer@aisec.fraunhofer.de> wrote: > > RISC-V defines the base integer instruction sets as RV32I and RV64I. > Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to match ARCH_RV64I > this convention. > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > --- > > arch/riscv/Kconfig | 16 ++++++++-------- > arch/riscv/lib/setjmp.S | 2 +- > configs/ax25-ae350_defconfig | 2 +- > configs/qemu-riscv64_defconfig | 2 +- > include/config_distro_bootcmd.h | 8 ++++---- > 5 files changed, 15 insertions(+), 15 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Regards, Bin
> > Hi Lukas, > > > > On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > wrote: > > > > > > RISC-V defines the base integer instruction sets as RV32I and RV64I. > > > Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to > > > match > > > > ARCH_RV64I > > > > > this convention. > > > > > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > > --- > > > > > > arch/riscv/Kconfig | 16 ++++++++-------- > > > arch/riscv/lib/setjmp.S | 2 +- > > > configs/ax25-ae350_defconfig | 2 +- > > > configs/qemu-riscv64_defconfig | 2 +- > > > include/config_distro_bootcmd.h | 8 ++++---- > > > 5 files changed, 15 insertions(+), 15 deletions(-) > > > > > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> > > > Regards, > > > Bin
Hi Bin, On Mon, 2018-10-22 at 14:23 +0800, Bin Meng wrote: > Hi Lukas, > > On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer > <lukas.auer@aisec.fraunhofer.de> wrote: > > > > RISC-V defines the base integer instruction sets as RV32I and > > RV64I. > > Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to > > match > > ARCH_RV64I > Fixed in v2. Thanks, Lukas > > this convention. > > > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > --- > > > > arch/riscv/Kconfig | 16 ++++++++-------- > > arch/riscv/lib/setjmp.S | 2 +- > > configs/ax25-ae350_defconfig | 2 +- > > configs/qemu-riscv64_defconfig | 2 +- > > include/config_distro_bootcmd.h | 8 ++++---- > > 5 files changed, 15 insertions(+), 15 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > Regards, > Bin
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 168ca3de7c..7c76b4d664 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,20 +20,20 @@ source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" choice - prompt "CPU selection" - default CPU_RISCV_32 + prompt "Base ISA" + default ARCH_RV32I -config CPU_RISCV_32 - bool "RISC-V 32-bit" +config ARCH_RV32I + bool "RV32I" select 32BIT help - Choose this option to build an U-Boot for RISCV32 architecture. + Choose this option to target the RV32I base integer instruction set. -config CPU_RISCV_64 - bool "RISC-V 64-bit" +config ARCH_RV64I + bool "RV64I" select 64BIT help - Choose this option to build an U-Boot for RISCV64 architecture. + Choose this option to target the RV64I base integer instruction set. endchoice diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 8f5a6a23aa..72bc9241f6 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -6,7 +6,7 @@ #include <config.h> #include <linux/linkage.h> -#ifdef CONFIG_CPU_RISCV_64 +#ifdef CONFIG_ARCH_RV64I #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) #else diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index 614ef15dc7..9282f05981 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -1,7 +1,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_AX25_AE350=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index d6c1a5d646..60b647efe8 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_TARGET_QEMU_VIRT=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 373fee78a9..54186efe7b 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -99,9 +99,9 @@ #define BOOTEFI_NAME "bootia32.efi" #elif defined(CONFIG_X86_RUN_64BIT) #define BOOTEFI_NAME "bootx64.efi" -#elif defined(CONFIG_CPU_RISCV_32) +#elif defined(CONFIG_ARCH_RV32I) #define BOOTEFI_NAME "bootriscv32.efi" -#elif defined(CONFIG_CPU_RISCV_64) +#elif defined(CONFIG_ARCH_RV64I) #define BOOTEFI_NAME "bootriscv64.efi" #endif #endif @@ -257,10 +257,10 @@ #elif defined(__i386__) #define BOOTENV_EFI_PXE_ARCH "0x6" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000" -#elif defined(CONFIG_CPU_RISCV_32) || ((defined(__riscv) && __riscv_xlen == 32)) +#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32)) #define BOOTENV_EFI_PXE_ARCH "0x19" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000" -#elif defined(CONFIG_CPU_RISCV_64) || ((defined(__riscv) && __riscv_xlen == 64)) +#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64)) #define BOOTENV_EFI_PXE_ARCH "0x1b" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000" #elif defined(CONFIG_SANDBOX)
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> --- arch/riscv/Kconfig | 16 ++++++++-------- arch/riscv/lib/setjmp.S | 2 +- configs/ax25-ae350_defconfig | 2 +- configs/qemu-riscv64_defconfig | 2 +- include/config_distro_bootcmd.h | 8 ++++---- 5 files changed, 15 insertions(+), 15 deletions(-)