Message ID | e68ed01cdfba5b7610559607a3c706b294a216fc.1536931725.git.christophe.leroy@c-s.fr |
---|---|
State | Superseded, archived |
Headers | show |
Series | None | expand |
On Fri, Sep 14, 2018 at 01:32:03PM +0000, Christophe Leroy wrote: > Add description of DT bindings for mpc8xxx-wdt driver which > handles the CPU watchdog timer on the mpc83xx, mpc86xx and mpc8xx. > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > --- > .../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt > > diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt > new file mode 100644 > index 000000000000..1d99e1e4d306 > --- /dev/null > +++ b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt > @@ -0,0 +1,25 @@ > +* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx) > + > +Required properties: > +- compatible: Shall contain one of the following: > + "mpc83xx_wdt" for an mpc83xx > + "fsl,mpc8610-wdt" for an mpc86xx > + "fsl,mpc823-wdt" for an mpc8xx > +- reg: base physical address and length of the area hosting the > + watchdog registers. > + On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100> > + On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100> > + On the 8xx, "General System Interface Unit" area: <0x0 0x10> > + Note for Rob: The above has been implemented for several years. This is merely to document the current implementation. Maybe "mpc83xx_wdt" should be deprecated and replaced, but I think that should be a separate patch. > +Optional properties: > +- reg: additionnal physical address and length (4) of location of the s/additionnal/additional/ > + Reset Status Register (called RSTRSCR on the mpc86xx) > + On the 83xx, it is located at offset 0x910 > + On the 86xx, it is located at offset 0xe0094 > + On the 8xx, it is located at offset 0x288 > + > +Example: > + WDT: watchdog@0 { > + compatible = "fsl,mpc823-wdt"; > + reg = <0x0 0x10 0x288 0x4>; > + }; > -- > 2.13.3 >
diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt new file mode 100644 index 000000000000..1d99e1e4d306 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt @@ -0,0 +1,25 @@ +* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx) + +Required properties: +- compatible: Shall contain one of the following: + "mpc83xx_wdt" for an mpc83xx + "fsl,mpc8610-wdt" for an mpc86xx + "fsl,mpc823-wdt" for an mpc8xx +- reg: base physical address and length of the area hosting the + watchdog registers. + On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100> + On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100> + On the 8xx, "General System Interface Unit" area: <0x0 0x10> + +Optional properties: +- reg: additionnal physical address and length (4) of location of the + Reset Status Register (called RSTRSCR on the mpc86xx) + On the 83xx, it is located at offset 0x910 + On the 86xx, it is located at offset 0xe0094 + On the 8xx, it is located at offset 0x288 + +Example: + WDT: watchdog@0 { + compatible = "fsl,mpc823-wdt"; + reg = <0x0 0x10 0x288 0x4>; + };
Add description of DT bindings for mpc8xxx-wdt driver which handles the CPU watchdog timer on the mpc83xx, mpc86xx and mpc8xx. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- .../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt