| Message ID | 20180901120407.9912-1-hauke@hauke-m.de |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | Add support for Lantiq / Intel vrx200 network | expand |
On 9/1/2018 5:04 AM, Hauke Mehrtens wrote: > This adds the binding for the PMAC core between the CPU and the GSWIP > switch found on the xrx200 / VR9 Lantiq / Intel SoC. > > Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> > Cc: devicetree@vger.kernel.org > --- > .../devicetree/bindings/net/lantiq,xrx200-net.txt | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt > > diff --git a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt > new file mode 100644 > index 000000000000..8a2fe5200cdc > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt > @@ -0,0 +1,21 @@ > +Lantiq xRX200 GSWIP PMAC Ethernet driver > +================================== > + > +Required properties: > + > +- compatible : "lantiq,xrx200-net" for the PMAC of the embedded > + : GSWIP in the xXR200 > +- reg : memory range of the PMAC core inside of the GSWIP core > +- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for > + : the TX interrupt and "rx" for the RX interrupt. You would likely want to document that the order should be strict, that is TX interrupt first and RX interrupt second, but other than that: Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
On 09/03/2018 09:46 PM, Florian Fainelli wrote: > > > On 9/1/2018 5:04 AM, Hauke Mehrtens wrote: >> This adds the binding for the PMAC core between the CPU and the GSWIP >> switch found on the xrx200 / VR9 Lantiq / Intel SoC. >> >> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> >> Cc: devicetree@vger.kernel.org >> --- >> .../devicetree/bindings/net/lantiq,xrx200-net.txt | 21 >> +++++++++++++++++++++ >> 1 file changed, 21 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt >> >> diff --git >> a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt >> b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt >> new file mode 100644 >> index 000000000000..8a2fe5200cdc >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt >> @@ -0,0 +1,21 @@ >> +Lantiq xRX200 GSWIP PMAC Ethernet driver >> +================================== >> + >> +Required properties: >> + >> +- compatible : "lantiq,xrx200-net" for the PMAC of the embedded >> + : GSWIP in the xXR200 >> +- reg : memory range of the PMAC core inside of the GSWIP core >> +- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for >> + : the TX interrupt and "rx" for the RX interrupt. > > You would likely want to document that the order should be strict, that > is TX interrupt first and RX interrupt second, but other than that: > > Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Currently this is fetched based on the name like this: platform_get_irq_byname(pdev, "rx"); I do not care about the order, just interrupt-names must match. Hauke
diff --git a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt new file mode 100644 index 000000000000..8a2fe5200cdc --- /dev/null +++ b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt @@ -0,0 +1,21 @@ +Lantiq xRX200 GSWIP PMAC Ethernet driver +================================== + +Required properties: + +- compatible : "lantiq,xrx200-net" for the PMAC of the embedded + : GSWIP in the xXR200 +- reg : memory range of the PMAC core inside of the GSWIP core +- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for + : the TX interrupt and "rx" for the RX interrupt. + +Example: + +eth0: eth@E10B308 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = <0xE10B308 0x30>; + interrupts = <73>, <72>; + interrupt-names = "tx", "rx"; +};
This adds the binding for the PMAC core between the CPU and the GSWIP switch found on the xrx200 / VR9 Lantiq / Intel SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: devicetree@vger.kernel.org --- .../devicetree/bindings/net/lantiq,xrx200-net.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt