Message ID | 20180725093649.32332-5-hch@lst.de |
---|---|
State | Changes Requested, archived |
Headers | show |
Series | None | expand |
On Wed, Jul 25, 2018 at 11:36:47AM +0200, Christoph Hellwig wrote: > From: Palmer Dabbelt <palmer@dabbelt.com> > > This patch adds documentation on the RISC-V local interrupt controller, > which is a per-hart interrupt controller that manages all interrupts > entering a RISC-V hart. This interrupt controller is present on all > RISC-V systems. > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > --- > .../interrupt-controller/riscv,cpu-intc.txt | 41 +++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt My questions and comments on the prior version from Palmer remain. > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt > new file mode 100644 > index 000000000000..61900e2e3868 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt > @@ -0,0 +1,41 @@ > +RISC-V Hart-Level Interrupt Controller (HLIC) > +--------------------------------------------- > + > +RISC-V cores include Control Status Registers (CSRs) which are local to each > +hart and can be read or written by software. Some of these CSRs are used to > +control local interrupts connected to the core. Every interrupt is ultimately > +routed through a hart's HLIC before it interrupts that hart. > + > +The RISC-V supervisor ISA manual specifies three interrupt sources that are > +attached to every HLIC: software interrupts, the timer interrupt, and external > +interrupts. Software interrupts are used to send IPIs between cores. The > +timer interrupt comes from an architecturally mandated real-time timer that is > +controller via SBI calls and CSR reads. External interrupts connect all other > +device interrupts to the HLIC, which are routed via the platform-level > +interrupt controller (PLIC). > + > +All RISC-V systems that conform to the supervisor ISA specification are > +required to have a HLIC with these three interrupt sources present. Since the > +interrupt map is defined by the ISA it's not listed in the HLIC's device tree > +entry, though external interrupt controllers (like the PLIC, for example) will > +need to define how their interrupts map to the relevant HLICs. > + > +Required properties: > +- compatible : "riscv,cpu-intc" > +- #interrupt-cells : should be <1> > +- interrupt-controller : Identifies the node as an interrupt controller > + > +Furthermore, this interrupt-controller MUST be embedded inside the cpu > +definition of the hart whose CSRs control these local interrupts. > + > +An example device tree entry for a HLIC is show below. > + > + cpu1: cpu@1 { > + compatible = "riscv"; > + ... > + cpu1-intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > -- > 2.18.0 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jul 31, 2018 at 04:37:14PM -0600, Rob Herring wrote: > On Wed, Jul 25, 2018 at 11:36:47AM +0200, Christoph Hellwig wrote: > > From: Palmer Dabbelt <palmer@dabbelt.com> > > > > This patch adds documentation on the RISC-V local interrupt controller, > > which is a per-hart interrupt controller that manages all interrupts > > entering a RISC-V hart. This interrupt controller is present on all > > RISC-V systems. > > > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > > --- > > .../interrupt-controller/riscv,cpu-intc.txt | 41 +++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt > > My questions and comments on the prior version from Palmer remain. Can you point to these questions please? I don't even rember when this was last posted as it must have been a long time ago. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Aug 1, 2018 at 1:08 AM Christoph Hellwig <hch@lst.de> wrote: > > On Tue, Jul 31, 2018 at 04:37:14PM -0600, Rob Herring wrote: > > On Wed, Jul 25, 2018 at 11:36:47AM +0200, Christoph Hellwig wrote: > > > From: Palmer Dabbelt <palmer@dabbelt.com> > > > > > > This patch adds documentation on the RISC-V local interrupt controller, > > > which is a per-hart interrupt controller that manages all interrupts > > > entering a RISC-V hart. This interrupt controller is present on all > > > RISC-V systems. > > > > > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > > > --- > > > .../interrupt-controller/riscv,cpu-intc.txt | 41 +++++++++++++++++++ > > > 1 file changed, 41 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt > > > > My questions and comments on the prior version from Palmer remain. > > Can you point to these questions please? I don't even rember when this > was last posted as it must have been a long time ago. It was just a month ago[1], but in googling for the links some comments from the 1st posting a year ago[2] aren't addressed either. That applies to the PLIC too. Rob [1] https://lkml.org/lkml/2018/7/3/1001 [2] https://lkml.org/lkml/2017/6/27/24 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt new file mode 100644 index 000000000000..61900e2e3868 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt @@ -0,0 +1,41 @@ +RISC-V Hart-Level Interrupt Controller (HLIC) +--------------------------------------------- + +RISC-V cores include Control Status Registers (CSRs) which are local to each +hart and can be read or written by software. Some of these CSRs are used to +control local interrupts connected to the core. Every interrupt is ultimately +routed through a hart's HLIC before it interrupts that hart. + +The RISC-V supervisor ISA manual specifies three interrupt sources that are +attached to every HLIC: software interrupts, the timer interrupt, and external +interrupts. Software interrupts are used to send IPIs between cores. The +timer interrupt comes from an architecturally mandated real-time timer that is +controller via SBI calls and CSR reads. External interrupts connect all other +device interrupts to the HLIC, which are routed via the platform-level +interrupt controller (PLIC). + +All RISC-V systems that conform to the supervisor ISA specification are +required to have a HLIC with these three interrupt sources present. Since the +interrupt map is defined by the ISA it's not listed in the HLIC's device tree +entry, though external interrupt controllers (like the PLIC, for example) will +need to define how their interrupts map to the relevant HLICs. + +Required properties: +- compatible : "riscv,cpu-intc" +- #interrupt-cells : should be <1> +- interrupt-controller : Identifies the node as an interrupt controller + +Furthermore, this interrupt-controller MUST be embedded inside the cpu +definition of the hart whose CSRs control these local interrupts. + +An example device tree entry for a HLIC is show below. + + cpu1: cpu@1 { + compatible = "riscv"; + ... + cpu1-intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + };