| Message ID | cover.aa759035f6eefdd0bb2a5ae335dab5bd5399bd46.1532954208.git-series.quentin.schulz@bootlin.com |
|---|---|
| Headers | show |
| Series | mscc: ocelot: add support for SerDes muxing configuration | expand |
Hi again, On Mon, Jul 30, 2018 at 02:43:45PM +0200, Quentin Schulz wrote: > The Ocelot switch has currently a hardcoded SerDes muxing that suits only > a particular use case. Any other board setup will fail to work. > > To prepare for upcoming boards' support that do not have the same muxing, > create a PHY driver that will handle all possible cases. > > A SerDes can work in SGMII, QSGMII or PCIe and is also muxed to use a > given port depending on the selected mode or board design. > > The SerDes configuration is in the middle of an address space (HSIO) that > is used to configure some parts in the MAC controller driver, that is why > we need to use a syscon so that we can write to the same address space from > different drivers safely using regmap. > > Patches from generic PHY and net should be safe to be merged separately. > > I suggest patches 1 to 5 and 10 go through net while the others (6 to 9) > go through the generic PHY subsystem. > Actually more like the following: 1 and 8 through MIPS tree, 2 to 5 and 10 through net, 6, 7 and 9 through PHY. Quentin > Thanks, > Quentin > > Quentin Schulz (10): > MIPS: mscc: ocelot: make HSIO registers address range a syscon > dt-bindings: net: ocelot: remove hsio from the list of register address spaces > net: mscc: ocelot: get HSIO regmap from syscon > net: mscc: ocelot: move the HSIO header to include/soc > net: mscc: ocelot: simplify register access for PLL5 configuration > phy: add QSGMII and PCIE modes > dt-bindings: phy: add DT binding for Microsemi Ocelot SerDes muxing > MIPS: mscc: ocelot: add SerDes mux DT node > phy: add driver for Microsemi Ocelot SerDes muxing > net: mscc: ocelot: make use of SerDes PHYs for handling their configuration > > Documentation/devicetree/bindings/mips/mscc.txt | 16 +- > Documentation/devicetree/bindings/net/mscc-ocelot.txt | 9 +- > Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt | 42 +- > arch/mips/boot/dts/mscc/ocelot.dtsi | 19 +- > drivers/net/ethernet/mscc/Kconfig | 2 +- > drivers/net/ethernet/mscc/ocelot.c | 16 +- > drivers/net/ethernet/mscc/ocelot.h | 79 +- > drivers/net/ethernet/mscc/ocelot_board.c | 54 +- > drivers/net/ethernet/mscc/ocelot_hsio.h | 785 +------ > drivers/net/ethernet/mscc/ocelot_regs.c | 93 +- > drivers/phy/Kconfig | 1 +- > drivers/phy/Makefile | 1 +- > drivers/phy/mscc/Kconfig | 11 +- > drivers/phy/mscc/Makefile | 5 +- > drivers/phy/mscc/phy-ocelot-serdes.c | 314 +++- > include/linux/phy/phy.h | 2 +- > include/soc/mscc/ocelot_hsio.h | 859 +++++++- > 17 files changed, 1343 insertions(+), 965 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt > delete mode 100644 drivers/net/ethernet/mscc/ocelot_hsio.h > create mode 100644 drivers/phy/mscc/Kconfig > create mode 100644 drivers/phy/mscc/Makefile > create mode 100644 drivers/phy/mscc/phy-ocelot-serdes.c > create mode 100644 include/soc/mscc/ocelot_hsio.h > > base-commit: d6e74c71c4de5222f147b64bf747e8a3c523c690 > -- > git-series 0.9.1
> The SerDes configuration is in the middle of an address space (HSIO) that > is used to configure some parts in the MAC controller driver, that is why > we need to use a syscon so that we can write to the same address space from > different drivers safely using regmap. Hi Quentin I assume breaking backwards compatibility is not an issue here, since there currently is only one board using the DT binding. But it would be good to give a warning in the cover notes. git bisect will also break for this one particular board. And since these changes are going through different trees, it could be quite a big break. Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jul 30, 2018 at 02:43:55PM +0200, Quentin Schulz wrote: > + err = of_get_phy_mode(portnp); > + if (err < 0) > + ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA; > + else > + ocelot->ports[port]->phy_mode = err; > + > + if (ocelot->ports[port]->phy_mode == PHY_INTERFACE_MODE_NA) > + continue; > + > + if (ocelot->ports[port]->phy_mode == PHY_INTERFACE_MODE_SGMII) > + phy_mode = PHY_MODE_SGMII; > + else > + phy_mode = PHY_MODE_QSGMII; Hi Quentin Say somebody puts RGMII as the phy-mode? It would be better to verify it is only SGMII or QSGMII and return -EINVAL otherwise. > + > + serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); > + if (IS_ERR(serdes)) { > + if (PTR_ERR(serdes) == -EPROBE_DEFER) { > + dev_err(ocelot->dev, "deferring probe\n"); dev_dbg() ? It is not really an error. > + err = -EPROBE_DEFER; > + goto err_probe_ports; > + } > + > + dev_err(ocelot->dev, "missing SerDes phys for port%d\n", > + port); > + err = -ENODEV; err = PTR_ERR(serdes) so we get the actual error? > goto err_probe_ports; > } > + > + ocelot->ports[port]->serdes = serdes; > } > > register_netdevice_notifier(&ocelot_netdevice_nb); Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 30/07/2018 14:43:46+0200, Quentin Schulz wrote: > HSIO contains registers for PLL5 configuration, SerDes/switch port > muxing and a thermal sensor, hence we can't keep it in the switch DT > node. > > Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > arch/mips/boot/dts/mscc/ocelot.dtsi | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi > index afe8fc9..c51663a 100644 > --- a/arch/mips/boot/dts/mscc/ocelot.dtsi > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi > @@ -96,7 +96,6 @@ > reg = <0x1010000 0x10000>, > <0x1030000 0x10000>, > <0x1080000 0x100>, > - <0x10d0000 0x10000>, > <0x11e0000 0x100>, > <0x11f0000 0x100>, > <0x1200000 0x100>, > @@ -110,10 +109,10 @@ > <0x1280000 0x100>, > <0x1800000 0x80000>, > <0x1880000 0x10000>; > - reg-names = "sys", "rew", "qs", "hsio", "port0", > - "port1", "port2", "port3", "port4", "port5", > - "port6", "port7", "port8", "port9", "port10", > - "qsys", "ana"; > + reg-names = "sys", "rew", "qs", "port0", "port1", > + "port2", "port3", "port4", "port5", "port6", > + "port7", "port8", "port9", "port10", "qsys", > + "ana"; > interrupts = <21 22>; > interrupt-names = "xtr", "inj"; > > @@ -220,5 +219,10 @@ > pinctrl-0 = <&miim1>; > status = "disabled"; > }; > + > + hsio: syscon@10d0000 { > + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; > + reg = <0x10d0000 0x10000>; > + }; > }; > }; > -- > git-series 0.9.1
On 30/07/2018 14:43:48+0200, Quentin Schulz wrote: > HSIO address space was moved to a syscon, hence we need to get the > regmap of this address space from there and no more from the device > node. > > Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > drivers/net/ethernet/mscc/ocelot_board.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/mscc/ocelot_board.c b/drivers/net/ethernet/mscc/ocelot_board.c > index 26bb3b1..b7d755b 100644 > --- a/drivers/net/ethernet/mscc/ocelot_board.c > +++ b/drivers/net/ethernet/mscc/ocelot_board.c > @@ -9,6 +9,7 @@ > #include <linux/netdevice.h> > #include <linux/of_mdio.h> > #include <linux/of_platform.h> > +#include <linux/mfd/syscon.h> > #include <linux/skbuff.h> > > #include "ocelot.h" > @@ -162,6 +163,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev) > struct device_node *np = pdev->dev.of_node; > struct device_node *ports, *portnp; > struct ocelot *ocelot; > + struct regmap *hsio; > u32 val; > > struct { > @@ -173,7 +175,6 @@ static int mscc_ocelot_probe(struct platform_device *pdev) > { QSYS, "qsys" }, > { ANA, "ana" }, > { QS, "qs" }, > - { HSIO, "hsio" }, > }; > > if (!np && !pdev->dev.platform_data) > @@ -196,6 +197,14 @@ static int mscc_ocelot_probe(struct platform_device *pdev) > ocelot->targets[res[i].id] = target; > } > > + hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); > + if (IS_ERR(hsio)) { > + dev_err(&pdev->dev, "missing hsio syscon\n"); > + return PTR_ERR(hsio); > + } > + > + ocelot->targets[HSIO] = hsio; > + > err = ocelot_chip_init(ocelot); > if (err) > return err; > -- > git-series 0.9.1
On 30/07/2018 14:43:49+0200, Quentin Schulz wrote: > Since HSIO address space can be used by different drivers (PLL, SerDes > muxing, temperature sensor), let's move it somewhere it can be included > by all drivers. > > Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > drivers/net/ethernet/mscc/ocelot.h | 1 +- > drivers/net/ethernet/mscc/ocelot_hsio.h | 785 +------------------------- > drivers/net/ethernet/mscc/ocelot_regs.c | 1 +- > include/soc/mscc/ocelot_hsio.h | 785 +++++++++++++++++++++++++- > 4 files changed, 786 insertions(+), 786 deletions(-) > delete mode 100644 drivers/net/ethernet/mscc/ocelot_hsio.h > create mode 100644 include/soc/mscc/ocelot_hsio.h > > diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h > index 616bec3..2da20a3 100644 > --- a/drivers/net/ethernet/mscc/ocelot.h > +++ b/drivers/net/ethernet/mscc/ocelot.h > @@ -16,7 +16,6 @@ > > #include "ocelot_ana.h" > #include "ocelot_dev.h" > -#include "ocelot_hsio.h" > #include "ocelot_qsys.h" > #include "ocelot_rew.h" > #include "ocelot_sys.h" > diff --git a/drivers/net/ethernet/mscc/ocelot_hsio.h b/drivers/net/ethernet/mscc/ocelot_hsio.h > deleted file mode 100644 > index d93ddec..0000000 > --- a/drivers/net/ethernet/mscc/ocelot_hsio.h > +++ /dev/null > @@ -1,785 +0,0 @@ > -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > -/* > - * Microsemi Ocelot Switch driver > - * > - * Copyright (c) 2017 Microsemi Corporation > - */ > - > -#ifndef _MSCC_OCELOT_HSIO_H_ > -#define _MSCC_OCELOT_HSIO_H_ > - > -#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) > -#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) > -#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) > -#define HSIO_PLL5G_CFG0_DIV4 BIT(28) > -#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27) > -#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) > -#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23) > -#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) > -#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) > -#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18) > -#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) > -#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) > -#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16) > -#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) > -#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15) > -#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14) > -#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13) > -#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12) > -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) > -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6) > -#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) > -#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) > -#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0) > - > -#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18) > -#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17) > -#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16) > -#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15) > -#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14) > -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) > -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6) > -#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) > -#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5) > -#define HSIO_PLL5G_CFG1_PWD_TX BIT(4) > -#define HSIO_PLL5G_CFG1_PWD_RX BIT(3) > -#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2) > -#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1) > -#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0) > - > -#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30) > -#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29) > -#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28) > -#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27) > -#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26) > -#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25) > -#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24) > -#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16)) > -#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16) > -#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16) > -#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15) > -#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14) > -#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13) > -#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12) > -#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11) > -#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10) > -#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5)) > -#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5) > -#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5) > -#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4) > -#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3) > -#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2) > -#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1) > -#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0) > - > -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22)) > -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22) > -#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22) > -#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19)) > -#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19) > -#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19) > -#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18) > -#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17) > -#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16) > -#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15) > -#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14) > -#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13) > -#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12) > -#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11) > -#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10) > -#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9) > -#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8) > -#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) > -#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0) > - > -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) > -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16) > -#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) > -#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) > -#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0) > - > -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) > -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16) > -#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) > -#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) > -#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0) > - > -#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23) > -#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20)) > -#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20) > -#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20) > -#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19) > -#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16)) > -#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16) > -#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16) > -#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8)) > -#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8) > -#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8) > -#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7) > -#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6) > -#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) > -#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0) > - > -#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12) > -#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11) > -#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10) > -#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9) > -#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1)) > -#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1) > -#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1) > -#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0) > - > -#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21)) > -#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21) > -#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21) > -#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16)) > -#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16) > -#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16) > -#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4)) > -#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4) > -#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4) > -#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1)) > -#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1) > -#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1) > -#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0) > - > -#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20)) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16)) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) > -#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0) > - > -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4) > -#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2) > -#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1) > -#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0) > - > -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16)) > -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16) > -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16) > -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0)) > -#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0) > - > -#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13) > -#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12) > -#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10)) > -#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10) > -#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10) > -#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8)) > -#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8) > -#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) > -#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4) > -#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) > -#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0) > - > -#define HSIO_RCOMP_STATUS_BUSY BIT(12) > -#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7) > -#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) > -#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0) > - > -#define HSIO_SYNC_ETH_CFG_RSZ 0x4 > - > -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4) > -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1)) > -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1) > -#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1) > -#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0) > - > -#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0) > - > -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) > -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) > -#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) > -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11)) > -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11) > -#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11) > -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8)) > -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8) > -#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8) > -#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5)) > -#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5) > -#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5) > -#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4) > -#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1)) > -#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1) > -#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1) > -#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0) > - > -#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27) > -#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24)) > -#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24) > -#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24) > -#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19)) > -#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19) > -#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19) > -#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14) > -#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13) > -#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12) > -#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11) > -#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10) > -#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9) > -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6)) > -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6) > -#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6) > -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4)) > -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4) > -#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4) > -#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) > -#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0) > - > -#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17)) > -#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17) > -#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17) > -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13)) > -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13) > -#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) > -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10)) > -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10) > -#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) > -#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9) > -#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8) > -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4) > -#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) > -#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) > - > -#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9) > -#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8) > -#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7) > -#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6) > -#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) > -#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) > -#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) > -#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3) > -#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2) > -#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1) > -#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0) > - > -#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31) > -#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21) > -#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18) > -#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17) > -#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16) > -#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13)) > -#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13) > -#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13) > -#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12) > -#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11) > -#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10) > -#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9) > -#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8) > -#define HSIO_S1G_COMMON_CFG_HRATE BIT(7) > -#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0) > - > -#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22) > -#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21) > -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8)) > -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8) > -#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8) > -#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7) > -#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6) > -#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5) > -#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3) > - > -#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12) > -#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11) > -#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10) > -#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) > -#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) > - > -#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31) > -#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23) > -#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) > -#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) > -#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) > -#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) > -#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) > -#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) > -#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) > -#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3) > -#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2) > -#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0) > - > -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) > -#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) > -#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3) > -#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) > -#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) > -#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) > - > -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) > -#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) > -#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3) > -#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) > -#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) > -#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) > - > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16)) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) > -#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) > - > -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) > -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) > -#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) > -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) > -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) > -#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) > -#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) > -#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) > -#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3) > -#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2) > -#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0) > - > -#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) > -#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6) > -#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) > -#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3) > -#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2) > -#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1) > -#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0) > - > -#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) > - > -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31) > -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30) > -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0)) > -#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0) > - > -#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16)) > -#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16) > -#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16) > -#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7) > -#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6) > -#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3)) > -#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3) > -#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3) > -#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0)) > -#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0) > - > -#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31) > -#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23) > -#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) > -#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) > -#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) > -#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) > -#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) > -#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) > -#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) > -#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3) > -#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2) > -#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0) > - > -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) > -#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) > -#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3) > -#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) > -#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) > -#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) > - > -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) > -#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) > -#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3) > -#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) > -#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) > -#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) > - > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16)) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) > -#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) > - > -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13)) > -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13) > -#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13) > -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) > -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) > -#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) > -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) > -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) > -#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) > -#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7) > -#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6) > -#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) > -#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) > -#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3) > -#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2) > -#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0) > - > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18)) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13)) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0)) > -#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0) > - > -#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8) > -#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) > -#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6) > -#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) > -#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3) > -#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2) > -#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1) > -#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0) > - > -#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) > - > -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) > -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) > -#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) > -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10)) > -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10) > -#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) > -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8)) > -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8) > -#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) > -#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5)) > -#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5) > -#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5) > -#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4) > -#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1)) > -#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1) > -#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1) > -#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0) > - > -#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29)) > -#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29) > -#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29) > -#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28) > -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24)) > -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24) > -#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24) > -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20)) > -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20) > -#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20) > -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18)) > -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18) > -#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18) > -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15)) > -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15) > -#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13)) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11)) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9)) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7)) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7) > -#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7) > -#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6) > -#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5) > -#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4) > -#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3) > -#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2) > -#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1) > -#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0) > - > -#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17)) > -#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17) > -#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17) > -#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12)) > -#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12) > -#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12) > -#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8)) > -#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8) > -#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8) > -#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7) > -#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6) > -#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5) > -#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4) > -#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3) > -#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2) > -#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1) > -#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0) > - > -#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27)) > -#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27) > -#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27) > -#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22)) > -#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22) > -#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22) > -#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19)) > -#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19) > -#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19) > -#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16)) > -#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16) > -#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16) > -#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10)) > -#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10) > -#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10) > -#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5)) > -#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5) > -#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5) > -#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3)) > -#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3) > -#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3) > -#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0)) > -#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0) > - > -#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18)) > -#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18) > -#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) > -#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12)) > -#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12) > -#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) > -#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6)) > -#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6) > -#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) > -#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0)) > -#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0) > - > -#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18)) > -#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18) > -#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) > -#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12)) > -#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12) > -#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) > -#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6)) > -#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6) > -#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) > -#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0)) > -#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0) > - > -#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18)) > -#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18) > -#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) > -#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12)) > -#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12) > -#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) > -#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6)) > -#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6) > -#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) > -#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0)) > -#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0) > - > -#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31) > -#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30) > -#define HSIO_S6G_OB_CFG_OB_POL BIT(29) > -#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) > -#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23) > -#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) > -#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18)) > -#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18) > -#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18) > -#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17) > -#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16) > -#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11)) > -#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11) > -#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11) > -#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10) > -#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9) > -#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8) > -#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4)) > -#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4) > -#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4) > -#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) > -#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) > - > -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) > -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6) > -#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) > -#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0)) > -#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0) > - > -#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8) > -#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7) > -#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6) > -#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) > -#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) > -#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) > -#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3) > -#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2) > -#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1) > -#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0) > - > -#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17) > -#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16) > -#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15) > -#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14) > -#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13) > -#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12) > -#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9)) > -#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9) > -#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9) > -#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8) > -#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7) > -#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6) > -#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5) > -#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4) > -#define HSIO_S6G_COMMON_CFG_HRATE BIT(3) > -#define HSIO_S6G_COMMON_CFG_QRATE BIT(2) > -#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0)) > -#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0) > - > -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16)) > -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16) > -#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16) > -#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15) > -#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14) > -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) > -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6) > -#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) > -#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5) > -#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4) > -#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3) > -#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2) > -#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1) > -#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0) > - > -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5) > -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4) > -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3) > -#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2) > -#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1) > -#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0) > - > -#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16)) > -#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16) > -#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16) > -#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0)) > -#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0) > - > -#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8) > -#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7) > -#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6) > -#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5) > -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4) > -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3) > -#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2) > -#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1) > -#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0) > - > -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18)) > -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18) > -#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18) > -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12)) > -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12) > -#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12) > -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6)) > -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6) > -#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6) > -#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0)) > -#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0) > - > -#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2) > -#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1) > -#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0) > - > -#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10) > -#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9) > -#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8) > -#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) > -#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) > - > -#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26)) > -#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26) > -#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26) > -#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21)) > -#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21) > -#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21) > -#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16)) > -#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16) > -#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16) > -#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10)) > -#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10) > -#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10) > -#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5)) > -#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5) > -#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5) > -#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0)) > -#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0) > - > -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31) > -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30) > -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0)) > -#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0) > - > -#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6) > -#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5) > -#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4) > -#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3) > -#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2) > -#define HSIO_HW_CFG_PCIE_ENA BIT(1) > -#define HSIO_HW_CFG_QSGMII_ENA BIT(0) > - > -#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3) > -#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2) > -#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1) > -#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0) > - > -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1)) > -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1) > -#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1) > -#define HSIO_HW_QSGMII_STAT_SYNC BIT(0) > - > -#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1)) > -#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1) > -#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1) > -#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0) > - > -#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5) > -#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4) > -#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3) > -#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2) > -#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1) > -#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0) > - > -#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8)) > -#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8) > -#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8) > -#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0)) > -#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0) > - > -#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8) > -#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0)) > -#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0) > - > -#endif > diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c > index e334b40..bf0c609 100644 > --- a/drivers/net/ethernet/mscc/ocelot_regs.c > +++ b/drivers/net/ethernet/mscc/ocelot_regs.c > @@ -5,6 +5,7 @@ > * Copyright (c) 2017 Microsemi Corporation > */ > #include "ocelot.h" > +#include <soc/mscc/ocelot_hsio.h> > > static const u32 ocelot_ana_regmap[] = { > REG(ANA_ADVLEARN, 0x009000), > diff --git a/include/soc/mscc/ocelot_hsio.h b/include/soc/mscc/ocelot_hsio.h > new file mode 100644 > index 0000000..d93ddec > --- /dev/null > +++ b/include/soc/mscc/ocelot_hsio.h > @@ -0,0 +1,785 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Microsemi Ocelot Switch driver > + * > + * Copyright (c) 2017 Microsemi Corporation > + */ > + > +#ifndef _MSCC_OCELOT_HSIO_H_ > +#define _MSCC_OCELOT_HSIO_H_ > + > +#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) > +#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) > +#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) > +#define HSIO_PLL5G_CFG0_DIV4 BIT(28) > +#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27) > +#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) > +#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23) > +#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) > +#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) > +#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18) > +#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) > +#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) > +#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16) > +#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) > +#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15) > +#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14) > +#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13) > +#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12) > +#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) > +#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6) > +#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) > +#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0) > + > +#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18) > +#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17) > +#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16) > +#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15) > +#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14) > +#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) > +#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6) > +#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) > +#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5) > +#define HSIO_PLL5G_CFG1_PWD_TX BIT(4) > +#define HSIO_PLL5G_CFG1_PWD_RX BIT(3) > +#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2) > +#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1) > +#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0) > + > +#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30) > +#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29) > +#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28) > +#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27) > +#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26) > +#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25) > +#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24) > +#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16)) > +#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16) > +#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15) > +#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14) > +#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13) > +#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12) > +#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11) > +#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10) > +#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5)) > +#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5) > +#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4) > +#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3) > +#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2) > +#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1) > +#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0) > + > +#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22)) > +#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22) > +#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22) > +#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19)) > +#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19) > +#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19) > +#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18) > +#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17) > +#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16) > +#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15) > +#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14) > +#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13) > +#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12) > +#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11) > +#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10) > +#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9) > +#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8) > +#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) > +#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0) > + > +#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) > +#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16) > +#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) > +#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0) > + > +#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) > +#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16) > +#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) > +#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) > +#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0) > + > +#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23) > +#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20)) > +#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20) > +#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20) > +#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19) > +#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16)) > +#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16) > +#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16) > +#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8)) > +#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8) > +#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7) > +#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6) > +#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) > +#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0) > + > +#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12) > +#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11) > +#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10) > +#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9) > +#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1)) > +#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1) > +#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1) > +#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0) > + > +#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21)) > +#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21) > +#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21) > +#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16)) > +#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16) > +#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16) > +#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4)) > +#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4) > +#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4) > +#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1)) > +#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1) > +#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0) > + > +#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20)) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16)) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) > +#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0) > + > +#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4) > +#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2) > +#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1) > +#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0) > + > +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16)) > +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16) > +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16) > +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0)) > +#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0) > + > +#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13) > +#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12) > +#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10)) > +#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10) > +#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10) > +#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8)) > +#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8) > +#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) > +#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4) > +#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) > +#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0) > + > +#define HSIO_RCOMP_STATUS_BUSY BIT(12) > +#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7) > +#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) > +#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0) > + > +#define HSIO_SYNC_ETH_CFG_RSZ 0x4 > + > +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4) > +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1)) > +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1) > +#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0) > + > +#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0) > + > +#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) > +#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) > +#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) > +#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11)) > +#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11) > +#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11) > +#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8)) > +#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8) > +#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8) > +#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5)) > +#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5) > +#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4) > +#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1)) > +#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1) > +#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0) > + > +#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27) > +#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24)) > +#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24) > +#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24) > +#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19)) > +#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19) > +#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19) > +#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14) > +#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13) > +#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12) > +#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11) > +#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10) > +#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9) > +#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6)) > +#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6) > +#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4)) > +#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4) > +#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) > +#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0) > + > +#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17)) > +#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17) > +#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17) > +#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13)) > +#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13) > +#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) > +#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10)) > +#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10) > +#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) > +#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9) > +#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8) > +#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4) > +#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) > +#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) > + > +#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9) > +#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8) > +#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7) > +#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6) > +#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) > +#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) > +#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3) > +#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2) > +#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1) > +#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0) > + > +#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31) > +#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21) > +#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18) > +#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17) > +#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16) > +#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13)) > +#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13) > +#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13) > +#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12) > +#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11) > +#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10) > +#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9) > +#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8) > +#define HSIO_S1G_COMMON_CFG_HRATE BIT(7) > +#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0) > + > +#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22) > +#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21) > +#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8)) > +#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8) > +#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7) > +#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6) > +#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5) > +#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3) > + > +#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12) > +#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11) > +#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10) > +#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) > +#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) > + > +#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31) > +#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23) > +#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) > +#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) > +#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) > +#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) > +#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) > +#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) > +#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) > +#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3) > +#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2) > +#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0) > + > +#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > +#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) > +#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > +#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) > +#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3) > +#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) > +#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) > +#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) > + > +#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > +#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) > +#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > +#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) > +#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3) > +#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) > +#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) > +#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) > + > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16)) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) > +#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) > + > +#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) > +#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) > +#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) > +#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) > +#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) > +#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) > +#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) > +#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) > +#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3) > +#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2) > +#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0) > + > +#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) > +#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6) > +#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) > +#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3) > +#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2) > +#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1) > +#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0) > + > +#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) > + > +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31) > +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30) > +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0)) > +#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0) > + > +#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16)) > +#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16) > +#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16) > +#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7) > +#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6) > +#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3)) > +#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3) > +#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3) > +#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0)) > +#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0) > + > +#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31) > +#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23) > +#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) > +#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) > +#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) > +#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) > +#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) > +#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) > +#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) > +#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3) > +#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2) > +#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0) > + > +#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > +#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) > +#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > +#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) > +#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3) > +#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) > +#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) > +#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) > + > +#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) > +#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) > +#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) > +#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) > +#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3) > +#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) > +#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) > +#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) > + > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16)) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) > +#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) > + > +#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13)) > +#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13) > +#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13) > +#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) > +#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) > +#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) > +#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) > +#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) > +#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) > +#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7) > +#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6) > +#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) > +#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) > +#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3) > +#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2) > +#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0) > + > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18)) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13)) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0)) > +#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0) > + > +#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8) > +#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) > +#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6) > +#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) > +#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3) > +#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2) > +#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1) > +#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0) > + > +#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) > + > +#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) > +#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) > +#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) > +#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10)) > +#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10) > +#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) > +#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8)) > +#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8) > +#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) > +#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5)) > +#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5) > +#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5) > +#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4) > +#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1)) > +#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1) > +#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1) > +#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0) > + > +#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29)) > +#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29) > +#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29) > +#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28) > +#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24)) > +#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24) > +#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24) > +#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20)) > +#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20) > +#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20) > +#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18)) > +#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18) > +#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18) > +#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15)) > +#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15) > +#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13)) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11)) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9)) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7)) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7) > +#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7) > +#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6) > +#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5) > +#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4) > +#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3) > +#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2) > +#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1) > +#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0) > + > +#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17)) > +#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17) > +#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17) > +#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12)) > +#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12) > +#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12) > +#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8)) > +#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8) > +#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8) > +#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7) > +#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6) > +#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5) > +#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4) > +#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3) > +#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2) > +#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1) > +#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0) > + > +#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27)) > +#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27) > +#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27) > +#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22)) > +#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22) > +#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22) > +#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19)) > +#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19) > +#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19) > +#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16)) > +#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16) > +#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16) > +#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10)) > +#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10) > +#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10) > +#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5)) > +#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5) > +#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3)) > +#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3) > +#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3) > +#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0)) > +#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0) > + > +#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18)) > +#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18) > +#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) > +#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12)) > +#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12) > +#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) > +#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6)) > +#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6) > +#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0)) > +#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0) > + > +#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18)) > +#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18) > +#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) > +#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12)) > +#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12) > +#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) > +#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6)) > +#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6) > +#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0)) > +#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0) > + > +#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18)) > +#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18) > +#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) > +#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12)) > +#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12) > +#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) > +#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6)) > +#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6) > +#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0)) > +#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0) > + > +#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31) > +#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30) > +#define HSIO_S6G_OB_CFG_OB_POL BIT(29) > +#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) > +#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23) > +#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) > +#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18)) > +#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18) > +#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18) > +#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17) > +#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16) > +#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11)) > +#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11) > +#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11) > +#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10) > +#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9) > +#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8) > +#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4)) > +#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4) > +#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4) > +#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) > +#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) > + > +#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) > +#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6) > +#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) > +#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0)) > +#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0) > + > +#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8) > +#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7) > +#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6) > +#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) > +#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) > +#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) > +#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3) > +#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2) > +#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1) > +#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0) > + > +#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17) > +#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16) > +#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15) > +#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14) > +#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13) > +#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12) > +#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9)) > +#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9) > +#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9) > +#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8) > +#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7) > +#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6) > +#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5) > +#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4) > +#define HSIO_S6G_COMMON_CFG_HRATE BIT(3) > +#define HSIO_S6G_COMMON_CFG_QRATE BIT(2) > +#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0)) > +#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0) > + > +#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16)) > +#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16) > +#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16) > +#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15) > +#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14) > +#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) > +#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6) > +#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) > +#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5) > +#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4) > +#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3) > +#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2) > +#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1) > +#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0) > + > +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5) > +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4) > +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3) > +#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2) > +#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1) > +#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0) > + > +#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16)) > +#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16) > +#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16) > +#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0)) > +#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0) > + > +#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8) > +#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7) > +#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6) > +#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5) > +#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4) > +#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3) > +#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2) > +#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1) > +#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0) > + > +#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18)) > +#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18) > +#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18) > +#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12)) > +#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12) > +#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12) > +#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6)) > +#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6) > +#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6) > +#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0)) > +#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0) > + > +#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2) > +#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1) > +#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0) > + > +#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10) > +#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9) > +#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8) > +#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) > +#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) > + > +#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26)) > +#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26) > +#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26) > +#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21)) > +#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21) > +#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21) > +#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16)) > +#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16) > +#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16) > +#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10)) > +#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10) > +#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10) > +#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5)) > +#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5) > +#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5) > +#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0)) > +#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0) > + > +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31) > +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30) > +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0)) > +#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0) > + > +#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6) > +#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5) > +#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4) > +#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3) > +#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2) > +#define HSIO_HW_CFG_PCIE_ENA BIT(1) > +#define HSIO_HW_CFG_QSGMII_ENA BIT(0) > + > +#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3) > +#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2) > +#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1) > +#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0) > + > +#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1)) > +#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1) > +#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1) > +#define HSIO_HW_QSGMII_STAT_SYNC BIT(0) > + > +#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1)) > +#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1) > +#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1) > +#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0) > + > +#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5) > +#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4) > +#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3) > +#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2) > +#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1) > +#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0) > + > +#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8)) > +#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8) > +#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8) > +#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0)) > +#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0) > + > +#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8) > +#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0)) > +#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0) > + > +#endif > -- > git-series 0.9.1
On 30/07/2018 14:43:50+0200, Quentin Schulz wrote: > Since HSIO address space can be accessed by different drivers, let's > simplify the register address definitions so that it can be easily used > by all drivers and put the register address definition in the > include/soc/mscc/ocelot_hsio.h header file. > > Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > --- > drivers/net/ethernet/mscc/ocelot.h | 73 +--------------------- > drivers/net/ethernet/mscc/ocelot_regs.c | 92 ++------------------------ > include/soc/mscc/ocelot_hsio.h | 74 +++++++++++++++++++++- > 3 files changed, 83 insertions(+), 156 deletions(-) > > diff --git a/drivers/net/ethernet/mscc/ocelot.h b/drivers/net/ethernet/mscc/ocelot.h > index 2da20a3..3720e51 100644 > --- a/drivers/net/ethernet/mscc/ocelot.h > +++ b/drivers/net/ethernet/mscc/ocelot.h > @@ -332,79 +332,6 @@ enum ocelot_reg { > SYS_CM_DATA_RD, > SYS_CM_OP, > SYS_CM_DATA, > - HSIO_PLL5G_CFG0 = HSIO << TARGET_OFFSET, > - HSIO_PLL5G_CFG1, > - HSIO_PLL5G_CFG2, > - HSIO_PLL5G_CFG3, > - HSIO_PLL5G_CFG4, > - HSIO_PLL5G_CFG5, > - HSIO_PLL5G_CFG6, > - HSIO_PLL5G_STATUS0, > - HSIO_PLL5G_STATUS1, > - HSIO_PLL5G_BIST_CFG0, > - HSIO_PLL5G_BIST_CFG1, > - HSIO_PLL5G_BIST_CFG2, > - HSIO_PLL5G_BIST_STAT0, > - HSIO_PLL5G_BIST_STAT1, > - HSIO_RCOMP_CFG0, > - HSIO_RCOMP_STATUS, > - HSIO_SYNC_ETH_CFG, > - HSIO_SYNC_ETH_PLL_CFG, > - HSIO_S1G_DES_CFG, > - HSIO_S1G_IB_CFG, > - HSIO_S1G_OB_CFG, > - HSIO_S1G_SER_CFG, > - HSIO_S1G_COMMON_CFG, > - HSIO_S1G_PLL_CFG, > - HSIO_S1G_PLL_STATUS, > - HSIO_S1G_DFT_CFG0, > - HSIO_S1G_DFT_CFG1, > - HSIO_S1G_DFT_CFG2, > - HSIO_S1G_TP_CFG, > - HSIO_S1G_RC_PLL_BIST_CFG, > - HSIO_S1G_MISC_CFG, > - HSIO_S1G_DFT_STATUS, > - HSIO_S1G_MISC_STATUS, > - HSIO_MCB_S1G_ADDR_CFG, > - HSIO_S6G_DIG_CFG, > - HSIO_S6G_DFT_CFG0, > - HSIO_S6G_DFT_CFG1, > - HSIO_S6G_DFT_CFG2, > - HSIO_S6G_TP_CFG0, > - HSIO_S6G_TP_CFG1, > - HSIO_S6G_RC_PLL_BIST_CFG, > - HSIO_S6G_MISC_CFG, > - HSIO_S6G_OB_ANEG_CFG, > - HSIO_S6G_DFT_STATUS, > - HSIO_S6G_ERR_CNT, > - HSIO_S6G_MISC_STATUS, > - HSIO_S6G_DES_CFG, > - HSIO_S6G_IB_CFG, > - HSIO_S6G_IB_CFG1, > - HSIO_S6G_IB_CFG2, > - HSIO_S6G_IB_CFG3, > - HSIO_S6G_IB_CFG4, > - HSIO_S6G_IB_CFG5, > - HSIO_S6G_OB_CFG, > - HSIO_S6G_OB_CFG1, > - HSIO_S6G_SER_CFG, > - HSIO_S6G_COMMON_CFG, > - HSIO_S6G_PLL_CFG, > - HSIO_S6G_ACJTAG_CFG, > - HSIO_S6G_GP_CFG, > - HSIO_S6G_IB_STATUS0, > - HSIO_S6G_IB_STATUS1, > - HSIO_S6G_ACJTAG_STATUS, > - HSIO_S6G_PLL_STATUS, > - HSIO_S6G_REVID, > - HSIO_MCB_S6G_ADDR_CFG, > - HSIO_HW_CFG, > - HSIO_HW_QSGMII_CFG, > - HSIO_HW_QSGMII_STAT, > - HSIO_CLK_CFG, > - HSIO_TEMP_SENSOR_CTRL, > - HSIO_TEMP_SENSOR_CFG, > - HSIO_TEMP_SENSOR_STAT, > }; > > enum ocelot_regfield { > diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c b/drivers/net/ethernet/mscc/ocelot_regs.c > index bf0c609..9271af1 100644 > --- a/drivers/net/ethernet/mscc/ocelot_regs.c > +++ b/drivers/net/ethernet/mscc/ocelot_regs.c > @@ -103,82 +103,6 @@ static const u32 ocelot_qs_regmap[] = { > REG(QS_INH_DBG, 0x000048), > }; > > -static const u32 ocelot_hsio_regmap[] = { > - REG(HSIO_PLL5G_CFG0, 0x000000), > - REG(HSIO_PLL5G_CFG1, 0x000004), > - REG(HSIO_PLL5G_CFG2, 0x000008), > - REG(HSIO_PLL5G_CFG3, 0x00000c), > - REG(HSIO_PLL5G_CFG4, 0x000010), > - REG(HSIO_PLL5G_CFG5, 0x000014), > - REG(HSIO_PLL5G_CFG6, 0x000018), > - REG(HSIO_PLL5G_STATUS0, 0x00001c), > - REG(HSIO_PLL5G_STATUS1, 0x000020), > - REG(HSIO_PLL5G_BIST_CFG0, 0x000024), > - REG(HSIO_PLL5G_BIST_CFG1, 0x000028), > - REG(HSIO_PLL5G_BIST_CFG2, 0x00002c), > - REG(HSIO_PLL5G_BIST_STAT0, 0x000030), > - REG(HSIO_PLL5G_BIST_STAT1, 0x000034), > - REG(HSIO_RCOMP_CFG0, 0x000038), > - REG(HSIO_RCOMP_STATUS, 0x00003c), > - REG(HSIO_SYNC_ETH_CFG, 0x000040), > - REG(HSIO_SYNC_ETH_PLL_CFG, 0x000048), > - REG(HSIO_S1G_DES_CFG, 0x00004c), > - REG(HSIO_S1G_IB_CFG, 0x000050), > - REG(HSIO_S1G_OB_CFG, 0x000054), > - REG(HSIO_S1G_SER_CFG, 0x000058), > - REG(HSIO_S1G_COMMON_CFG, 0x00005c), > - REG(HSIO_S1G_PLL_CFG, 0x000060), > - REG(HSIO_S1G_PLL_STATUS, 0x000064), > - REG(HSIO_S1G_DFT_CFG0, 0x000068), > - REG(HSIO_S1G_DFT_CFG1, 0x00006c), > - REG(HSIO_S1G_DFT_CFG2, 0x000070), > - REG(HSIO_S1G_TP_CFG, 0x000074), > - REG(HSIO_S1G_RC_PLL_BIST_CFG, 0x000078), > - REG(HSIO_S1G_MISC_CFG, 0x00007c), > - REG(HSIO_S1G_DFT_STATUS, 0x000080), > - REG(HSIO_S1G_MISC_STATUS, 0x000084), > - REG(HSIO_MCB_S1G_ADDR_CFG, 0x000088), > - REG(HSIO_S6G_DIG_CFG, 0x00008c), > - REG(HSIO_S6G_DFT_CFG0, 0x000090), > - REG(HSIO_S6G_DFT_CFG1, 0x000094), > - REG(HSIO_S6G_DFT_CFG2, 0x000098), > - REG(HSIO_S6G_TP_CFG0, 0x00009c), > - REG(HSIO_S6G_TP_CFG1, 0x0000a0), > - REG(HSIO_S6G_RC_PLL_BIST_CFG, 0x0000a4), > - REG(HSIO_S6G_MISC_CFG, 0x0000a8), > - REG(HSIO_S6G_OB_ANEG_CFG, 0x0000ac), > - REG(HSIO_S6G_DFT_STATUS, 0x0000b0), > - REG(HSIO_S6G_ERR_CNT, 0x0000b4), > - REG(HSIO_S6G_MISC_STATUS, 0x0000b8), > - REG(HSIO_S6G_DES_CFG, 0x0000bc), > - REG(HSIO_S6G_IB_CFG, 0x0000c0), > - REG(HSIO_S6G_IB_CFG1, 0x0000c4), > - REG(HSIO_S6G_IB_CFG2, 0x0000c8), > - REG(HSIO_S6G_IB_CFG3, 0x0000cc), > - REG(HSIO_S6G_IB_CFG4, 0x0000d0), > - REG(HSIO_S6G_IB_CFG5, 0x0000d4), > - REG(HSIO_S6G_OB_CFG, 0x0000d8), > - REG(HSIO_S6G_OB_CFG1, 0x0000dc), > - REG(HSIO_S6G_SER_CFG, 0x0000e0), > - REG(HSIO_S6G_COMMON_CFG, 0x0000e4), > - REG(HSIO_S6G_PLL_CFG, 0x0000e8), > - REG(HSIO_S6G_ACJTAG_CFG, 0x0000ec), > - REG(HSIO_S6G_GP_CFG, 0x0000f0), > - REG(HSIO_S6G_IB_STATUS0, 0x0000f4), > - REG(HSIO_S6G_IB_STATUS1, 0x0000f8), > - REG(HSIO_S6G_ACJTAG_STATUS, 0x0000fc), > - REG(HSIO_S6G_PLL_STATUS, 0x000100), > - REG(HSIO_S6G_REVID, 0x000104), > - REG(HSIO_MCB_S6G_ADDR_CFG, 0x000108), > - REG(HSIO_HW_CFG, 0x00010c), > - REG(HSIO_HW_QSGMII_CFG, 0x000110), > - REG(HSIO_HW_QSGMII_STAT, 0x000114), > - REG(HSIO_CLK_CFG, 0x000118), > - REG(HSIO_TEMP_SENSOR_CTRL, 0x00011c), > - REG(HSIO_TEMP_SENSOR_CFG, 0x000120), > - REG(HSIO_TEMP_SENSOR_STAT, 0x000124), > -}; > - > static const u32 ocelot_qsys_regmap[] = { > REG(QSYS_PORT_MODE, 0x011200), > REG(QSYS_SWITCH_PORT_MODE, 0x011234), > @@ -303,7 +227,6 @@ static const u32 ocelot_sys_regmap[] = { > static const u32 *ocelot_regmap[] = { > [ANA] = ocelot_ana_regmap, > [QS] = ocelot_qs_regmap, > - [HSIO] = ocelot_hsio_regmap, > [QSYS] = ocelot_qsys_regmap, > [REW] = ocelot_rew_regmap, > [SYS] = ocelot_sys_regmap, > @@ -454,9 +377,11 @@ static void ocelot_pll5_init(struct ocelot *ocelot) > /* Configure PLL5. This will need a proper CCF driver > * The values are coming from the VTSS API for Ocelot > */ > - ocelot_write(ocelot, HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | > - HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8), HSIO_PLL5G_CFG4); > - ocelot_write(ocelot, HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | > + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, > + HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | > + HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); > + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, > + HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | > HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | > HSIO_PLL5G_CFG0_ENA_BIAS | > HSIO_PLL5G_CFG0_ENA_VCO_BUF | > @@ -466,13 +391,14 @@ static void ocelot_pll5_init(struct ocelot *ocelot) > HSIO_PLL5G_CFG0_SELBGV820(4) | > HSIO_PLL5G_CFG0_DIV4 | > HSIO_PLL5G_CFG0_ENA_CLKTREE | > - HSIO_PLL5G_CFG0_ENA_LANE, HSIO_PLL5G_CFG0); > - ocelot_write(ocelot, HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | > + HSIO_PLL5G_CFG0_ENA_LANE); > + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, > + HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | > HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | > HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | > HSIO_PLL5G_CFG2_ENA_AMPCTRL | > HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | > - HSIO_PLL5G_CFG2_AMPC_SEL(0x10), HSIO_PLL5G_CFG2); > + HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); > } > > int ocelot_chip_init(struct ocelot *ocelot) > diff --git a/include/soc/mscc/ocelot_hsio.h b/include/soc/mscc/ocelot_hsio.h > index d93ddec..43112dd 100644 > --- a/include/soc/mscc/ocelot_hsio.h > +++ b/include/soc/mscc/ocelot_hsio.h > @@ -8,6 +8,80 @@ > #ifndef _MSCC_OCELOT_HSIO_H_ > #define _MSCC_OCELOT_HSIO_H_ > > +#define HSIO_PLL5G_CFG0 0x0000 > +#define HSIO_PLL5G_CFG1 0x0004 > +#define HSIO_PLL5G_CFG2 0x0008 > +#define HSIO_PLL5G_CFG3 0x000c > +#define HSIO_PLL5G_CFG4 0x0010 > +#define HSIO_PLL5G_CFG5 0x0014 > +#define HSIO_PLL5G_CFG6 0x0018 > +#define HSIO_PLL5G_STATUS0 0x001c > +#define HSIO_PLL5G_STATUS1 0x0020 > +#define HSIO_PLL5G_BIST_CFG0 0x0024 > +#define HSIO_PLL5G_BIST_CFG1 0x0028 > +#define HSIO_PLL5G_BIST_CFG2 0x002c > +#define HSIO_PLL5G_BIST_STAT0 0x0030 > +#define HSIO_PLL5G_BIST_STAT1 0x0034 > +#define HSIO_RCOMP_CFG0 0x0038 > +#define HSIO_RCOMP_STATUS 0x003c > +#define HSIO_SYNC_ETH_CFG 0x0040 > +#define HSIO_SYNC_ETH_PLL_CFG 0x0048 > +#define HSIO_S1G_DES_CFG 0x004c > +#define HSIO_S1G_IB_CFG 0x0050 > +#define HSIO_S1G_OB_CFG 0x0054 > +#define HSIO_S1G_SER_CFG 0x0058 > +#define HSIO_S1G_COMMON_CFG 0x005c > +#define HSIO_S1G_PLL_CFG 0x0060 > +#define HSIO_S1G_PLL_STATUS 0x0064 > +#define HSIO_S1G_DFT_CFG0 0x0068 > +#define HSIO_S1G_DFT_CFG1 0x006c > +#define HSIO_S1G_DFT_CFG2 0x0070 > +#define HSIO_S1G_TP_CFG 0x0074 > +#define HSIO_S1G_RC_PLL_BIST_CFG 0x0078 > +#define HSIO_S1G_MISC_CFG 0x007c > +#define HSIO_S1G_DFT_STATUS 0x0080 > +#define HSIO_S1G_MISC_STATUS 0x0084 > +#define HSIO_MCB_S1G_ADDR_CFG 0x0088 > +#define HSIO_S6G_DIG_CFG 0x008c > +#define HSIO_S6G_DFT_CFG0 0x0090 > +#define HSIO_S6G_DFT_CFG1 0x0094 > +#define HSIO_S6G_DFT_CFG2 0x0098 > +#define HSIO_S6G_TP_CFG0 0x009c > +#define HSIO_S6G_TP_CFG1 0x00a0 > +#define HSIO_S6G_RC_PLL_BIST_CFG 0x00a4 > +#define HSIO_S6G_MISC_CFG 0x00a8 > +#define HSIO_S6G_OB_ANEG_CFG 0x00ac > +#define HSIO_S6G_DFT_STATUS 0x00b0 > +#define HSIO_S6G_ERR_CNT 0x00b4 > +#define HSIO_S6G_MISC_STATUS 0x00b8 > +#define HSIO_S6G_DES_CFG 0x00bc > +#define HSIO_S6G_IB_CFG 0x00c0 > +#define HSIO_S6G_IB_CFG1 0x00c4 > +#define HSIO_S6G_IB_CFG2 0x00c8 > +#define HSIO_S6G_IB_CFG3 0x00cc > +#define HSIO_S6G_IB_CFG4 0x00d0 > +#define HSIO_S6G_IB_CFG5 0x00d4 > +#define HSIO_S6G_OB_CFG 0x00d8 > +#define HSIO_S6G_OB_CFG1 0x00dc > +#define HSIO_S6G_SER_CFG 0x00e0 > +#define HSIO_S6G_COMMON_CFG 0x00e4 > +#define HSIO_S6G_PLL_CFG 0x00e8 > +#define HSIO_S6G_ACJTAG_CFG 0x00ec > +#define HSIO_S6G_GP_CFG 0x00f0 > +#define HSIO_S6G_IB_STATUS0 0x00f4 > +#define HSIO_S6G_IB_STATUS1 0x00f8 > +#define HSIO_S6G_ACJTAG_STATUS 0x00fc > +#define HSIO_S6G_PLL_STATUS 0x0100 > +#define HSIO_S6G_REVID 0x0104 > +#define HSIO_MCB_S6G_ADDR_CFG 0x0108 > +#define HSIO_HW_CFG 0x010c > +#define HSIO_HW_QSGMII_CFG 0x0110 > +#define HSIO_HW_QSGMII_STAT 0x0114 > +#define HSIO_CLK_CFG 0x0118 > +#define HSIO_TEMP_SENSOR_CTRL 0x011c > +#define HSIO_TEMP_SENSOR_CFG 0x0120 > +#define HSIO_TEMP_SENSOR_STAT 0x0124 > + > #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) > #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) > #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) > -- > git-series 0.9.1
Hi Andrew, On Mon, Jul 30, 2018 at 03:50:18PM +0200, Andrew Lunn wrote: > On Mon, Jul 30, 2018 at 02:43:55PM +0200, Quentin Schulz wrote: > > > + err = of_get_phy_mode(portnp); > > + if (err < 0) > > + ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA; > > + else > > + ocelot->ports[port]->phy_mode = err; > > + > > + if (ocelot->ports[port]->phy_mode == PHY_INTERFACE_MODE_NA) > > + continue; > > + > > + if (ocelot->ports[port]->phy_mode == PHY_INTERFACE_MODE_SGMII) > > + phy_mode = PHY_MODE_SGMII; > > + else > > + phy_mode = PHY_MODE_QSGMII; > > Hi Quentin > > Say somebody puts RGMII as the phy-mode? It would be better to verify > it is only SGMII or QSGMII and return -EINVAL otherwise. > I'll replace this with a switch case to handle other cases. > > + > > + serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); > > + if (IS_ERR(serdes)) { > > + if (PTR_ERR(serdes) == -EPROBE_DEFER) { > > + dev_err(ocelot->dev, "deferring probe\n"); > > dev_dbg() ? It is not really an error. > Ack. > > + err = -EPROBE_DEFER; > > + goto err_probe_ports; > > + } > > + > > + dev_err(ocelot->dev, "missing SerDes phys for port%d\n", > > + port); > > + err = -ENODEV; > > err = PTR_ERR(serdes) so we get the actual error? > Ack. Thanks, Quentin
Hi Andrew, On Mon, Jul 30, 2018 at 03:24:41PM +0200, Andrew Lunn wrote: > > The SerDes configuration is in the middle of an address space (HSIO) that > > is used to configure some parts in the MAC controller driver, that is why > > we need to use a syscon so that we can write to the same address space from > > different drivers safely using regmap. > > Hi Quentin > > I assume breaking backwards compatibility is not an issue here, since > there currently is only one board using the DT binding. But it would > be good to give a warning in the cover notes. git bisect will also > break for this one particular board. And since these changes are going > through different trees, it could be quite a big break. > Yes sorry, I should have mentioned it in the cover letter, will do if/when there is a v2. Thanks, Quentin