@@ -100,12 +100,37 @@ enum
/* Conversion-to-integer of a NaN or a number too large or too small. */
FE_INVALID_INTEGER_CONVERSION =
# define FE_INVALID_INTEGER_CONVERSION (1 << (31 - 23))
- FE_INVALID_INTEGER_CONVERSION
+ FE_INVALID_INTEGER_CONVERSION,
# define FE_ALL_INVALID \
(FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
| FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
| FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
+
+ /* Enable invalid operation exception. */
+ FE_INVALID_ENABLE =
+# define FE_INVALID_ENABLE (1 << (31 - 24))
+ FE_INVALID_ENABLE,
+
+ /* Enable overflow exception. */
+ FE_OVERFLOW_ENABLE =
+# define FE_OVERFLOW_ENABLE (1 << (31 - 25))
+ FE_OVERFLOW_ENABLE,
+
+ /* Enable underflow exception. */
+ FE_UNDERFLOW_ENABLE =
+# define FE_UNDERFLOW_ENABLE (1 << (31 - 26))
+ FE_UNDERFLOW_ENABLE,
+
+ /* Enable zero divide exception. */
+ FE_DIVBYZERO_ENABLE =
+# define FE_DIVBYZERO_ENABLE (1 << (31 - 27))
+ FE_DIVBYZERO_ENABLE,
+
+ /* Enable inexact operation exception. */
+ FE_INEXACT_ENABLE =
+# define FE_INEXACT_ENABLE (1 << (31 - 28))
+ FE_INEXACT_ENABLE
#endif
};
@@ -1,5 +1,6 @@
ifeq ($(subdir),math)
libm-support += fenv_const fe_nomask fe_mask t_sqrt
+tests += test-ppc-fenv-bits
endif
ifeq ($(subdir),stdlib)
new file mode 100644
@@ -0,0 +1,68 @@
+/* Test if feenableexcept() does match with FPSCR registers.
+ Copyright (C) 2018 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <fenv.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <support/check.h>
+
+typedef union
+{
+ double f;
+ uint64_t l;
+} fpscr_t;
+
+
+#define get_fpscr() \
+ ({ fpscr_t fpscr; asm volatile ("mffs %0" : "=f" (fpscr.f)); fpscr.l; })
+
+void
+test_flag (uint64_t fpscr_flag, int fe_flag, const char * flag_name)
+{
+ uint64_t fpscr;
+ feenableexcept (fe_flag);
+ fpscr = get_fpscr ();
+ if (fpscr == fpscr_flag)
+ printf ("Pass: Flag \"%s\" is set\n", flag_name);
+ else
+ {
+ support_record_failure ();
+ printf ("Fail: Flag \"%s\" is not set\n", flag_name);
+ }
+ fedisableexcept (fe_flag);
+}
+
+int
+do_test (void)
+{
+ uint64_t fpscr;
+
+ fpscr = get_fpscr ();
+ if (fpscr != 0)
+ FAIL_EXIT (1, "Fail: The FPSCR is not 0\n");
+
+ test_flag (FE_INVALID_ENABLE, FE_INVALID, "INVALID_ENABLE");
+ test_flag (FE_OVERFLOW_ENABLE, FE_OVERFLOW, "OVERFLOW_ENABLE");
+ test_flag (FE_UNDERFLOW_ENABLE, FE_UNDERFLOW, "UNDERFLOW_ENABLE");
+ test_flag (FE_DIVBYZERO_ENABLE, FE_DIVBYZERO, "DIVBYZERO_ENABLE");
+ test_flag (FE_INEXACT_ENABLE, FE_INEXACT, "INEXACT_ENABLE");
+ return 0;
+}
+
+#include <support/test-driver.c>
The POWER ISA defines bits 56:60 (bits 24:28 in a 32-bit FPSCR) as control for the 5 exceptions available: invalid operation, overflow, underflow, zero divide and inexact. 2018-06-27 Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> * sysdeps/powerpc/bits/fenv.h [__USE_GNU]: Add FE_INVALID_ENABLE, FE_OVERFLOW_ENABLE, FE_UNDERFLOW_ENABLE, FE_DIVBYZERO_ENABLE and FE_INEXACT_ENABLE. * sysdeps/powerpc/fpu/Makefile [$(subdir) == math](tests): Add test-ppc-fenv-bits. * sysdeps/powerpc/fpu/test-ppc-fenv-bits.c: New file. Signed-off-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> --- sysdeps/powerpc/bits/fenv.h | 27 ++++++++++++- sysdeps/powerpc/fpu/Makefile | 1 + sysdeps/powerpc/fpu/test-ppc-fenv-bits.c | 68 ++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 sysdeps/powerpc/fpu/test-ppc-fenv-bits.c