Message ID | 1529497429-8576-2-git-send-email-abel.vesa@nxp.com |
---|---|
State | New |
Headers | show |
Series | pinctrl: imx: Add driver for i.MX8MQ | expand |
> -----Original Message----- > From: Abel Vesa > Sent: Wednesday, June 20, 2018 8:24 PM > To: Lucas Stach <l.stach@pengutronix.de>; A.s. Dong > <aisheng.dong@nxp.com> > Cc: linux-gpio@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Shawn > Guo <shawnguo@kernel.org>; Pengutronix Kernel Team > <kernel@pengutronix.de>; Linus Walleij <linus.walleij@linaro.org>; Rob > Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Abel Vesa > <abelvesa@linux.com>; Abel Vesa <abel.vesa@nxp.com> > Subject: [PATCH v4 1/2] dt-bindings: add binding for i.MX8MQ IOMUXC > > This adds the binding for the i.MX8MQ pin controller, in the same fashion as > earlier i.MX SoCs. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 29 > ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt > > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt > new file mode 100644 > index 0000000..f11a3f0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt > @@ -0,0 +1,29 @@ > +* Freescale IMX8MQ IOMUX Controller > + > +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this > +directory for common binding part and usage. > + > +Required properties: > +- compatible: "fsl,imx8mq-iomuxc" > +- fsl,pins: each entry consists of 6 integers and represents the mux > +and config > + setting for one pin. The first 5 integers <mux_reg conf_reg > +input_reg mux_val > + input_val> are specified using a PIN_FUNC_ID macro, which can be > +found in > + imx8mq-pinfunc.h under device tree source folder. The last integer > +CONFIG is > + the pad setting value like pull-up on this pin. Please refer to > +i.MX8M Quad > + Reference Manual for detailed CONFIG settings. > + > +Examples: > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > +}; > + > +&iomuxc { > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX > 0x49 > + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX > 0x49 > + >; > + }; > +}; How about giving more detailed information in the example as it only shows show the pinctrl group part. e.g. iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x0 0x30330000 0x0 0x10000>; pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 >; }; }; Other than that: Acked-by: Dong Aisheng <Aisheng.dong@nxp.com> Regards Dong Aisheng > -- > 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt new file mode 100644 index 0000000..f11a3f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt @@ -0,0 +1,29 @@ +* Freescale IMX8MQ IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +Required properties: +- compatible: "fsl,imx8mq-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad + Reference Manual for detailed CONFIG settings. + +Examples: + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; +};
This adds the binding for the i.MX8MQ pin controller, in the same fashion as earlier i.MX SoCs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt