| Message ID | b3706a51-27a4-d78b-998d-9440637ac216@cogentembedded.com |
|---|---|
| Headers | show |
| Series | sh_eth: unify the SoC feature checks | expand |
Should have been 0/5 in the subject. Sorry. :-)
On 03/24/2018 11:14 PM, Sergei Shtylyov wrote:
> Should have been 0/5 in the subject. Sorry. :-)
Oh, and I forgot 'net-next' inside [], sorry again! :-)
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Date: Sat, 24 Mar 2018 23:04:53 +0300 > Here's a set of 5 patches against DaveM's 'net-next.git' repo. > > The Ether driver sometimes uses the bit fields in 'struct sh_eth_cpu_data' > to check which Ether registers exist in a certain SoC and sometimes it uses > sh_eth_is_{gether|rz_fast_ether}() which basically compares 2 pointers (1 of > them being constant) -- the latter is definitely not a strongest feature of > the RISC CPUs (be it SH or ARM), so I decided to get rid of this type of > the feature checks in favour of the bit fields (I've also made use of a > 32-bit value and method pointer where appropriate)... Series applied with patch #4 subject fixed up. Thank you.
Hello! Here's a set of 5 patches against DaveM's 'net-next.git' repo. The Ether driver sometimes uses the bit fields in 'struct sh_eth_cpu_data' to check which Ether registers exist in a certain SoC and sometimes it uses sh_eth_is_{gether|rz_fast_ether}() which basically compares 2 pointers (1 of them being constant) -- the latter is definitely not a strongest feature of the RISC CPUs (be it SH or ARM), so I decided to get rid of this type of the feature checks in favour of the bit fields (I've also made use of a 32-bit value and method pointer where appropriate)... [1/5] sh_eth: add sh_eth_cpu_data::soft_reset() method [2/5] sh_eth: add sh_eth_cpu_data::edtrr_trns value [3/5] sh_eth: add sh_eth_cpu_data::xdfar_rw flag [4/5] sh_eth: add sh_eth_cpu_data::no_tx_cntr flag [5/5] sh_eth: add sh_eth_cpu_data::cexcr flag MBR, Sergei