| Message ID | 20171215062443.23059-1-joel@jms.id.au |
|---|---|
| Headers | show |
| Series | ARM: dts: aspeed: updates and new machines | expand |
On Fri, Dec 15, 2017 at 04:54:25PM +1030, Joel Stanley wrote: > These will be merged as part of the clock driver. This commit is > included so the tree will build without the clock series being applied. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > v2: > - remove NUM_CLKS define. There's no need for it to be part of ABI > --- > include/dt-bindings/clock/aspeed-clock.h | 52 ++++++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 include/dt-bindings/clock/aspeed-clock.h Reviewed-by: Rob Herring <robh@kernel.org>
On Fri, Dec 15, 2017 at 04:54:26PM +1030, Joel Stanley wrote: > These are used to by the device tree to map pin numbers to constants > required by the GPIO bindings. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 1 + > arch/arm/boot/dts/aspeed-g5.dtsi | 1 + > include/dt-bindings/gpio/aspeed-gpio.h | 49 ++++++++++++++++++++++++++++++++++ > 3 files changed, 51 insertions(+) > create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 45d815a86d42..100d092e6c07 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > #include "skeleton.dtsi" > +#include <dt-bindings/gpio/aspeed-gpio.h> Don't you need to use the defines? Probably should be a separate patch. Rob
On 12/15/2017 07:24 AM, Joel Stanley wrote: > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++ > arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index cf407b4db630..2e3666d4fbeb 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -177,11 +177,13 @@ > wdt1: watchdog@1e785000 { > compatible = "aspeed,ast2400-wdt"; > reg = <0x1e785000 0x1c>; > + clocks = <&syscon ASPEED_CLK_APB>; > }; > > wdt2: watchdog@1e785020 { > compatible = "aspeed,ast2400-wdt"; > reg = <0x1e785020 0x1c>; > + clocks = <&syscon ASPEED_CLK_APB>; > }; > > vuart: serial@1e787000 { > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index ab26156d6822..24bb2d16b900 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -219,16 +219,19 @@ > wdt1: watchdog@1e785000 { > compatible = "aspeed,ast2500-wdt"; > reg = <0x1e785000 0x20>; > + clocks = <&syscon ASPEED_CLK_APB>; > }; > > wdt2: watchdog@1e785020 { > compatible = "aspeed,ast2500-wdt"; > reg = <0x1e785020 0x20>; > + clocks = <&syscon ASPEED_CLK_APB>; > }; > > wdt3: watchdog@1e785040 { > compatible = "aspeed,ast2500-wdt"; > reg = <0x1e785040 0x20>; > + clocks = <&syscon ASPEED_CLK_APB>; > status = "disabled"; > }; > >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++ > arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 2e3666d4fbeb..afac0ca0cb10 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -56,6 +56,7 @@ > #address-cells = <1>; > #size-cells = <0>; > compatible = "aspeed,ast2400-fmc"; > + clocks = <&syscon ASPEED_CLK_AHB>; > status = "disabled"; > interrupts = <19>; > flash@0 { > @@ -71,6 +72,7 @@ > #address-cells = <1>; > #size-cells = <0>; > compatible = "aspeed,ast2400-spi"; > + clocks = <&syscon ASPEED_CLK_AHB>; > status = "disabled"; > flash@0 { > reg = < 0 >; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 24bb2d16b900..f3689caf6fe2 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -56,6 +56,7 @@ > #address-cells = <1>; > #size-cells = <0>; > compatible = "aspeed,ast2500-fmc"; > + clocks = <&syscon ASPEED_CLK_AHB>; > status = "disabled"; > interrupts = <19>; > flash@0 { > @@ -81,6 +82,7 @@ > #address-cells = <1>; > #size-cells = <0>; > compatible = "aspeed,ast2500-spi"; > + clocks = <&syscon ASPEED_CLK_AHB>; > status = "disabled"; > flash@0 { > reg = < 0 >; > @@ -100,6 +102,7 @@ > #address-cells = <1>; > #size-cells = <0>; > compatible = "aspeed,ast2500-spi"; > + clocks = <&syscon ASPEED_CLK_AHB>; > status = "disabled"; > flash@0 { > reg = < 0 >; >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > This is a layout used by OpenBMC systems. It describes the fixed flash > layout of a 32MB mtd device. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 +++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi > > diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi > new file mode 100644 > index 000000000000..63ad8db7a431 > --- /dev/null > +++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + u-boot@0 { > + reg = <0x0 0x60000>; > + label = "u-boot"; > + }; > + > + u-boot-env@60000 { > + reg = <0x60000 0x20000>; > + label = "u-boot-env"; > + }; > + > + kernel@80000 { > + reg = <0x80000 0x440000>; > + label = "kernel"; > + }; > + > + rofs@0c0000 { > + reg = <0x4c0000 0x1740000>; > + label = "rofs"; > + }; > + > + rwfs@1c00000 { > + reg = <0x1c00000 0x400000>; > + label = "rwfs"; > + }; > +}; >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > In b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier > to files with no license") these files had the GPL-2.0 licence added > automatically. Update them to be GPL 2.0+ in line with other IBM kernel > contributions. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +- > arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +- > arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 +- > arch/arm/boot/dts/aspeed-g4.dtsi | 2 +- > arch/arm/boot/dts/aspeed-g5.dtsi | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts > index 602bc10fdaf4..3e6f38e5d5d0 100644 > --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts > +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts > @@ -1,4 +1,4 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0+ > /dts-v1/; > > #include "aspeed-g5.dtsi" > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > index c786bc2f2919..a8f0c046e83e 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > @@ -1,4 +1,4 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0+ > /dts-v1/; > > #include "aspeed-g4.dtsi" > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts > index 8067793129ea..a7a9386f964d 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts > @@ -1,4 +1,4 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0+ > /dts-v1/; > > #include "aspeed-g5.dtsi" > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 2d7ac577d6b5..9c175832babc 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -1,4 +1,4 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0+ > #include <dt-bindings/clock/aspeed-clock.h> > #include <dt-bindings/gpio/aspeed-gpio.h> > > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 030a760696fd..360329eab7c3 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -1,4 +1,4 @@ > -// SPDX-License-Identifier: GPL-2.0 > +// SPDX-License-Identifier: GPL-2.0+ > #include <dt-bindings/clock/aspeed-clock.h> > #include <dt-bindings/gpio/aspeed-gpio.h> > >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > In preperation for adding more boards. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > arch/arm/boot/dts/Makefile | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index d0381e9caf21..5d1e9d37bf3a 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1101,7 +1101,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ > mt8127-moose.dtb \ > mt8135-evbp1.dtb > dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb > -dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \ > - aspeed-bmc-opp-romulus.dtb \ > - aspeed-ast2500-evb.dtb > +dtb-$(CONFIG_ARCH_ASPEED) += \ > + aspeed-ast2500-evb.dtb \ > + aspeed-bmc-opp-palmetto.dtb \ > + aspeed-bmc-opp-romulus.dtb > endif >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > We don't require it for any of the ASPEED systems. Reviewed-by: Cédric Le Goater <clg@kaod.org> > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 1 - > arch/arm/boot/dts/aspeed-g5.dtsi | 1 - > 2 files changed, 2 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index b3580f37f507..2d7ac577d6b5 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -1,5 +1,4 @@ > // SPDX-License-Identifier: GPL-2.0 > -#include "skeleton.dtsi" > #include <dt-bindings/clock/aspeed-clock.h> > #include <dt-bindings/gpio/aspeed-gpio.h> > > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 50766f0629f8..030a760696fd 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -1,5 +1,4 @@ > // SPDX-License-Identifier: GPL-2.0 > -#include "skeleton.dtsi" > #include <dt-bindings/clock/aspeed-clock.h> > #include <dt-bindings/gpio/aspeed-gpio.h> > >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > The OpenBMC flash layout is used by Palmetto systems. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > index a8f0c046e83e..cc18137386f2 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > @@ -34,6 +34,7 @@ > status = "okay"; > m25p,fast-read; > label = "bmc"; > +#include "openbmc-flash-layout.dtsi" > }; > }; > >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > LPC snoop hardware on the ASPEED BMC, used for monitoring > host I/O port activity. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++ > arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index f6fee40c04c0..b3580f37f507 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -236,6 +236,13 @@ > status = "disabled"; > }; > > + lpc_snoop: lpc-snoop@0 { > + compatible = "aspeed,ast2500-lpc-snoop"; it should be : aspeed,ast2400-lpc-snoop a part from that : Reviewed-by: Cédric Le Goater <clg@kaod.org> > + reg = <0x0 0x80>; > + interrupts = <8>; > + status = "disabled"; > + }; > + > lhc: lhc@20 { > compatible = "aspeed,ast2500-lhc"; > reg = <0x20 0x24 0x48 0x8>; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 96a9d2fe3f0d..50766f0629f8 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -287,6 +287,12 @@ > status = "disabled"; > }; > > + lpc_snoop: lpc-snoop@0 { > + compatible = "aspeed,ast2500-lpc-snoop"; > + reg = <0x0 0x80>; > + interrupts = <8>; > + status = "disabled"; > + }; > > lhc: lhc@20 { > compatible = "aspeed,ast2500-lhc"; >
On 12/15/2017 07:24 AM, Joel Stanley wrote: > From: Andrew Jeffery <andrew@aj.id.au> > > Ensure the ordering is correct and add all of the children in the SoC > device trees for the ast2400 and ast2500. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++---------- > 2 files changed, 52 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 100d092e6c07..a3bc5da7d42c 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -226,6 +226,41 @@ > status = "disabled"; > }; > > + lpc: lpc@1e789000 { > + compatible = "aspeed,ast2400-lpc", "simple-mfd"; > + reg = <0x1e789000 0x1000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x1e789000 0x1000>; > + > + lpc_bmc: lpc-bmc@0 { > + compatible = "aspeed,ast2400-lpc-bmc"; > + reg = <0x0 0x80>; > + }; > + > + lpc_host: lpc-host@80 { > + compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; > + reg = <0x80 0x1e0>; > + reg-io-width = <4>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x80 0x1e0>; > + > + lpc_ctrl: lpc-ctrl@0 { > + compatible = "aspeed,ast2400-lpc-ctrl"; > + reg = <0x0 0x80>; > + status = "disabled"; > + }; > + > + lhc: lhc@20 { > + compatible = "aspeed,ast2500-lhc"; aspeed,ast2400-lhc The layout of the registers are the same but there a couple of differences in the bit definitions between the two SoCs. a part from that : Reviewed-by: Cédric Le Goater <clg@kaod.org> C. > + reg = <0x20 0x24 0x48 0x8>; > + }; > + }; > + }; > + > uart2: serial@1e78d000 { > compatible = "ns16550a"; > reg = <0x1e78d000 0x20>; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 1f9d28313f82..7861631940fe 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -266,6 +266,16 @@ > status = "disabled"; > }; > > + vuart: serial@1e787000 { > + compatible = "aspeed,ast2500-vuart"; > + reg = <0x1e787000 0x40>; > + reg-shift = <2>; > + interrupts = <10>; > + clocks = <&clk_uart>; > + no-loopback-test; > + status = "disabled"; > + }; > + > lpc: lpc@1e789000 { > compatible = "aspeed,ast2500-lpc", "simple-mfd"; > reg = <0x1e789000 0x1000>; > @@ -289,6 +299,13 @@ > > reg-io-width = <4>; > > + lpc_ctrl: lpc-ctrl@0 { > + compatible = "aspeed,ast2500-lpc-ctrl"; > + reg = <0x0 0x80>; > + status = "disabled"; > + }; > + > + > lhc: lhc@20 { > compatible = "aspeed,ast2500-lhc"; > reg = <0x20 0x24 0x48 0x8>; > @@ -296,16 +313,6 @@ > }; > }; > > - vuart: serial@1e787000 { > - compatible = "aspeed,ast2500-vuart"; > - reg = <0x1e787000 0x40>; > - reg-shift = <2>; > - interrupts = <10>; > - clocks = <&clk_uart>; > - no-loopback-test; > - status = "disabled"; > - }; > - > uart2: serial@1e78d000 { > compatible = "ns16550a"; > reg = <0x1e78d000 0x20>; >
Some comments below, On 12/15/2017 07:24 AM, Joel Stanley wrote: > - Fix incorrect RAM size > - Remove alias; these are now specified in the dtsi > - Add newly upstreamed devices > - Include OpenBMC flash layout > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 153 ++++++++++++++++++++++++++- > 1 file changed, 148 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts > index a7a9386f964d..bfdf643584df 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts > @@ -7,17 +7,13 @@ > model = "Romulus BMC"; > compatible = "ibm,romulus-bmc", "aspeed,ast2500"; > > - aliases { > - serial4 = &uart5; > - }; > - > chosen { > stdout-path = &uart5; > bootargs = "console=ttyS4,115200 earlyprintk"; > }; > > memory { > - reg = <0x80000000 0x40000000>; > + reg = <0x80000000 0x20000000>; > }; > > reserved-memory { > @@ -29,6 +25,73 @@ > no-map; > reg = <0xbf000000 0x01000000>; /* 16M */ > }; > + > + flash_memory: region@98000000 { > + no-map; > + reg = <0x98000000 0x04000000>; /* 64M */ > + }; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + fault { > + gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>; > + }; > + > + identify { > + gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>; > + }; > + > + power { > + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; > + }; > + }; > + > + fsi: gpio-fsi { > + compatible = "fsi-master-gpio", "fsi-master"; > + #address-cells = <2>; > + #size-cells = <0>; > + > + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; > + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; > + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; > + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; > + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + > + checkstop { > + label = "checkstop"; > + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; > + linux,code = <ASPEED_GPIO(J, 2)>; > + }; > + }; > +}; > + > +&fmc { > + status = "okay"; > + > + flash@0 { > + status = "okay"; > + label = "pnor"; > + m25p,fast-read; > +#include "openbmc-flash-layout.dtsi" > + }; > +}; > + > +&spi1 { > + status = "okay"; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_spi1_default>; > + > + flash@0 { > + status = "okay"; > + label = "pnor"; > + m25p,fast-read; > }; > }; hmm, the fmc and spi1 bindings were already added in commit 1142aea9ff9d. > @@ -38,6 +101,7 @@ > status = "okay"; > m25p,fast-read; > label = "bmc"; > +#include "openbmc-flash-layout.dtsi" This looks like an extra "fmc" node ? > }; > }; > > @@ -53,6 +117,12 @@ > }; > }; > > +&lpc_ctrl { > + status = "okay"; > + memory-region = <&flash_memory>; > + flash = <&spi1>; > +}; > + > &uart1 { > /* Rear RS-232 connector */ > status = "okay"; > @@ -81,6 +151,10 @@ > pinctrl-0 = <&pinctrl_rmii1_default>; > }; > > +&i2c1 { > + status = "okay"; > +}; > + > &i2c2 { > status = "okay"; > }; > @@ -133,8 +207,77 @@ > > &i2c12 { > status = "okay"; > + > + max31785@52 { > + compatible = "maxim,max31785"; > + reg = <0x52>; > + }; > +}; > + > +&gpio { > + nic_func_mode0 { > + gpio-hog; > + gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>; > + output-low; > + line-name = "nic_func_mode0"; > + }; > + nic_func_mode1 { > + gpio-hog; > + gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>; > + output-low; > + line-name = "nic_func_mode1"; > + }; > }; > > &vuart { > status = "okay"; > }; > + > +&gfx { > + status = "okay"; > +}; > + > +&pinctrl { > + aspeed,external-nodes = <&gfx &lhc>; > +}; > + > +&pwm_tacho { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; > + > + fan@0 { > + reg = <0x00>; > + aspeed,fan-tach-ch = /bits/ 8 <0x08>; > + }; > + > + fan@1 { > + reg = <0x00>; > + aspeed,fan-tach-ch = /bits/ 8 <0x09>; > + }; > + > + fan@2 { > + reg = <0x01>; > + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; > + }; > + > + fan@3 { > + reg = <0x01>; > + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; > + }; > + > + fan@4 { > + reg = <0x00>; > + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; > + }; > + > + fan@5 { > + reg = <0x00>; > + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; > + }; > + > + fan@6 { > + reg = <0x01>; > + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; > + }; > +}; >
On Mon, Dec 18, 2017 at 7:46 PM, Cédric Le Goater <clg@kaod.org> wrote: > On 12/15/2017 07:24 AM, Joel Stanley wrote: >> LPC snoop hardware on the ASPEED BMC, used for monitoring >> host I/O port activity. >> >> Signed-off-by: Joel Stanley <joel@jms.id.au> >> --- >> arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++ >> arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++ >> 2 files changed, 13 insertions(+) >> >> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi >> index f6fee40c04c0..b3580f37f507 100644 >> --- a/arch/arm/boot/dts/aspeed-g4.dtsi >> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi >> @@ -236,6 +236,13 @@ >> status = "disabled"; >> }; >> >> + lpc_snoop: lpc-snoop@0 { >> + compatible = "aspeed,ast2500-lpc-snoop"; > > it should be : > > aspeed,ast2400-lpc-snoop > > a part from that : > > Reviewed-by: Cédric Le Goater <clg@kaod.org> Fixed in v3. Cheers, Joel
j On Mon, Dec 18, 2017 at 7:55 PM, Cédric Le Goater <clg@kaod.org> wrote: > On 12/15/2017 07:24 AM, Joel Stanley wrote: >> From: Andrew Jeffery <andrew@aj.id.au> >> >> Ensure the ordering is correct and add all of the children in the SoC >> device trees for the ast2400 and ast2500. >> >> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> >> Signed-off-by: Joel Stanley <joel@jms.id.au> >> --- >> arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++ >> arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++---------- >> 2 files changed, 52 insertions(+), 10 deletions(-) >> >> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi >> index 100d092e6c07..a3bc5da7d42c 100644 >> --- a/arch/arm/boot/dts/aspeed-g4.dtsi >> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi >> @@ -226,6 +226,41 @@ >> status = "disabled"; >> }; >> >> + lpc: lpc@1e789000 { >> + compatible = "aspeed,ast2400-lpc", "simple-mfd"; >> + reg = <0x1e789000 0x1000>; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x0 0x1e789000 0x1000>; >> + >> + lpc_bmc: lpc-bmc@0 { >> + compatible = "aspeed,ast2400-lpc-bmc"; >> + reg = <0x0 0x80>; >> + }; >> + >> + lpc_host: lpc-host@80 { >> + compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; >> + reg = <0x80 0x1e0>; >> + reg-io-width = <4>; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x0 0x80 0x1e0>; >> + >> + lpc_ctrl: lpc-ctrl@0 { >> + compatible = "aspeed,ast2400-lpc-ctrl"; >> + reg = <0x0 0x80>; >> + status = "disabled"; >> + }; >> + >> + lhc: lhc@20 { >> + compatible = "aspeed,ast2500-lhc"; > > aspeed,ast2400-lhc > > The layout of the registers are the same but there a couple of differences > in the bit definitions between the two SoCs. > > a part from that : > > Reviewed-by: Cédric Le Goater <clg@kaod.org> Good catch. Fixed in v3. Cheers, Joel
On Mon, Dec 18, 2017 at 8:02 PM, Cédric Le Goater <clg@kaod.org> wrote: >> +}; >> + >> +&fmc { >> + status = "okay"; >> + >> + flash@0 { >> + status = "okay"; >> + label = "pnor"; >> + m25p,fast-read; >> +#include "openbmc-flash-layout.dtsi" >> + }; >> +}; >> + >> +&spi1 { >> + status = "okay"; >> + >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_spi1_default>; >> + >> + flash@0 { >> + status = "okay"; >> + label = "pnor"; >> + m25p,fast-read; >> }; >> }; > > > hmm, the fmc and spi1 bindings were already added in commit 1142aea9ff9d. > > >> @@ -38,6 +101,7 @@ >> status = "okay"; >> m25p,fast-read; >> label = "bmc"; >> +#include "openbmc-flash-layout.dtsi" > > > This looks like an extra "fmc" node ? You're right. It still built and booted too. Good catch. Cheers, Joel
This series of device tree patches for the ASPEED BMC machines moves all systems to use the soon to be merged clk driver, and updates machines to use all of the drivers we have upstream. v2: Address review from Arnd - Remove NUM_CLKS from dt header - Send VUART patch as a fix, drop it from this series - Add reasoning for breaking old kernel in the 'proper clock references' patch In addition it adds three new OpenBMC systems that have been developed in the OpenBMC kernel tree over the past year: two Power9 OpenPower systems, and a port by Google to a Quanta x86 server. I have boot tested these on Romulus and Palmetto, as well as boot tested all device trees in Qemu. Please review the boards you are familiar with. I will merge these in to the ASPEED ARM SoC tree for inclusion in 4.16. Andrew Jeffery (1): ARM: dts: aspeed: Add LPC and child devices Joel Stanley (16): dt-bindings: clock: Add ASPEED constants dt-bindings: gpio: Add ASPEED constants ARM: dts: aspeed: Add proper clock references ARM: dts: aspeed: Add MAC clocks ARM: dts: aspeed: Add watchdog clocks ARM: dts: aspeed: Add flash controller clocks ARM: dts: aspeed: Add clock phandle to GPIO ARM: dts: aspeed: Add PWM and tachometer node ARM: dts: aspeed: Add LPC Snoop device ARM: dts: aspeed: Remove skeleton.dtsi ARM: dts: aspeed: Update license headers ARM: dts: Add OpenBMC flash layout ARM: dts: aspeed: Sort ASPEED entries in makefile ARM: dts: aspeed: Add Witherspoon BMC machine ARM: dts: aspeed-romulus: Update Romulus system ARM: dts: aspeed-plametto: Add flash layout Rick Altherr (1): ARM: dts: aspeed: Add Qanta Q71L BMC machine Xo Wang (1): ARM: dts: aspeed: Add Ingrasys Zaius BMC machine arch/arm/boot/dts/Makefile | 8 +- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 3 +- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 155 ++++++- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 547 +++++++++++++++++++++++ arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 427 ++++++++++++++++++ arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 458 +++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 164 ++++--- arch/arm/boot/dts/aspeed-g5.dtsi | 155 ++++--- arch/arm/boot/dts/openbmc-flash-layout.dtsi | 32 ++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ include/dt-bindings/gpio/aspeed-gpio.h | 49 ++ 12 files changed, 1906 insertions(+), 146 deletions(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts create mode 100644 arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts create mode 100644 arch/arm/boot/dts/openbmc-flash-layout.dtsi create mode 100644 include/dt-bindings/clock/aspeed-clock.h create mode 100644 include/dt-bindings/gpio/aspeed-gpio.h