Message ID | 20171031165805.25803-1-lukma@denx.de |
---|---|
State | Accepted |
Commit | a3eec24ad382090097b206a4d4e5f01435e9aca5 |
Delegated to: | Stefano Babic |
Headers | show |
Series | [U-Boot,v4] imx:display5: Add support for LWN's DISPLAY5 board (for v2017.11-rc2+) | expand |
Hi Lukasz, On 31/10/2017 17:58, Lukasz Majewski wrote: > This commit provides support for LWN's IMX6Q based DISPLAY5 board. > I would merge it, but why the commit message is still "(for v2017.11-rc2+)" ? This goes into git history if I merge it. Can I drop it by merging ? Best regards, Stefano > Signed-off-by: Lukasz Majewski <lukma@denx.de> > > --- > > Changes in v4: > - Refactor obscure sw/hw rev code for display5 board > - replace get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); with imx_ddr_size() > - remove PHYS_SDRAM_SIZE from display5.h > - Replace non generic setup of RGMII pins voltage levels with a generic > function > - Move displ5_set_iomux_uart() - non console UART init to board_init() > - Disable board_early_init_f() calls (prod/factory) > - Move mtdparts to Kconfig for production and flash u-boot > > Changes in v3: > - Remove ip custom data > - Cleanup SPL code > > Changes in v2: > - Update to newest mainline u-boot > > arch/arm/dts/imx6q-display5.dts | 18 ++ > arch/arm/mach-imx/mx6/Kconfig | 7 + > board/liebherr/display5/Kconfig | 18 ++ > board/liebherr/display5/MAINTAINERS | 7 + > board/liebherr/display5/Makefile | 11 + > board/liebherr/display5/common.c | 111 ++++++++++ > board/liebherr/display5/common.h | 42 ++++ > board/liebherr/display5/display5.c | 384 +++++++++++++++++++++++++++++++++ > board/liebherr/display5/spl.c | 247 ++++++++++++++++++++++ > configs/display5_defconfig | 62 ++++++ > configs/display5_factory_defconfig | 76 +++++++ > include/configs/display5.h | 408 ++++++++++++++++++++++++++++++++++++ > 12 files changed, 1391 insertions(+) > create mode 100644 arch/arm/dts/imx6q-display5.dts > create mode 100644 board/liebherr/display5/Kconfig > create mode 100644 board/liebherr/display5/MAINTAINERS > create mode 100644 board/liebherr/display5/Makefile > create mode 100644 board/liebherr/display5/common.c > create mode 100644 board/liebherr/display5/common.h > create mode 100644 board/liebherr/display5/display5.c > create mode 100644 board/liebherr/display5/spl.c > create mode 100644 configs/display5_defconfig > create mode 100644 configs/display5_factory_defconfig > create mode 100644 include/configs/display5.h > > diff --git a/arch/arm/dts/imx6q-display5.dts b/arch/arm/dts/imx6q-display5.dts > new file mode 100644 > index 0000000000..50347ff26b > --- /dev/null > +++ b/arch/arm/dts/imx6q-display5.dts > @@ -0,0 +1,18 @@ > +/* > + * Copyright 2017 > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +/dts-v1/; > + > +#include "imx6q.dtsi" > + > +/ { > + model = "Liebherr (LWN) display5 i.MX6 Quad Board"; > + compatible = "lwn,display5", "fsl,imx6q"; > +}; > diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig > index b82db3af22..fd73c67fde 100644 > --- a/arch/arm/mach-imx/mx6/Kconfig > +++ b/arch/arm/mach-imx/mx6/Kconfig > @@ -138,6 +138,12 @@ config TARGET_DHCOMIMX6 > select DM_THERMAL > imply CMD_SPL > > +config TARGET_DISPLAY5 > + bool "LWN DISPLAY5 board" > + select SUPPORT_SPL > + select DM > + select DM_SERIAL > + > config TARGET_EMBESTMX6BOARDS > bool "embestmx6boards" > select BOARD_LATE_INIT > @@ -459,6 +465,7 @@ source "board/phytec/pfla02/Kconfig" > source "board/gateworks/gw_ventana/Kconfig" > source "board/kosagi/novena/Kconfig" > source "board/samtec/vining_2000/Kconfig" > +source "board/liebherr/display5/Kconfig" > source "board/liebherr/mccmon6/Kconfig" > source "board/logicpd/imx6/Kconfig" > source "board/seco/Kconfig" > diff --git a/board/liebherr/display5/Kconfig b/board/liebherr/display5/Kconfig > new file mode 100644 > index 0000000000..b096c8917a > --- /dev/null > +++ b/board/liebherr/display5/Kconfig > @@ -0,0 +1,18 @@ > +if TARGET_DISPLAY5 > + > +config SYS_CPU > + default "armv7" > + > +config SYS_BOARD > + default "display5" > + > +config SYS_VENDOR > + default "liebherr" > + > +config SYS_SOC > + default "mx6" > + > +config SYS_CONFIG_NAME > + default "display5" > + > +endif > diff --git a/board/liebherr/display5/MAINTAINERS b/board/liebherr/display5/MAINTAINERS > new file mode 100644 > index 0000000000..52178318b5 > --- /dev/null > +++ b/board/liebherr/display5/MAINTAINERS > @@ -0,0 +1,7 @@ > +DISPLAY5 BOARD > +M: Lukasz Majewski <lukma@denx.de> > +S: Maintained > +F: board/liebherr/display5/ > +F: include/configs/display5.h > +F: configs/display5_defconfig > +F: configs/display5_factory_defconfig > diff --git a/board/liebherr/display5/Makefile b/board/liebherr/display5/Makefile > new file mode 100644 > index 0000000000..f934672428 > --- /dev/null > +++ b/board/liebherr/display5/Makefile > @@ -0,0 +1,11 @@ > +# > +# Copyright (C) 2017, DENX Software Engineering > +# Lukasz Majewski <lukma@denx.de> > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > +ifdef CONFIG_SPL_BUILD > +obj-y = common.o spl.o > +else > +obj-y := common.o display5.o > +endif > diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c > new file mode 100644 > index 0000000000..03f585b3aa > --- /dev/null > +++ b/board/liebherr/display5/common.c > @@ -0,0 +1,111 @@ > +/* > + * Copyright (C) 2017 DENX Software Engineering > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm/arch/mx6-pins.h> > +#include "common.h" > + > +iomux_v3_cfg_t const uart_pads[] = { > + /* UART4 */ > + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const uart_console_pads[] = { > + /* UART5 */ > + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +void displ5_set_iomux_uart_spl(void) > +{ > + SETUP_IOMUX_PADS(uart_console_pads); > +} > + > +void displ5_set_iomux_uart(void) > +{ > + SETUP_IOMUX_PADS(uart_pads); > +} > + > +#ifdef CONFIG_MXC_SPI > +iomux_v3_cfg_t const ecspi_pads[] = { > + /* SPI3 */ > + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const ecspi2_pads[] = { > + /* SPI2, NOR Flash nWP, CS0 */ > + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) > +{ > + if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8)) > + return -EINVAL; > + > + return IMX_GPIO_NR(5, 29); > +} > + > +void displ5_set_iomux_ecspi_spl(void) > +{ > + SETUP_IOMUX_PADS(ecspi2_pads); > +} > + > +void displ5_set_iomux_ecspi(void) > +{ > + SETUP_IOMUX_PADS(ecspi_pads); > +} > + > +#else > +void displ5_set_iomux_ecspi_spl(void) {} > +void displ5_set_iomux_ecspi(void) {} > +#endif > + > +#ifdef CONFIG_FSL_ESDHC > +iomux_v3_cfg_t const usdhc4_pads[] = { > + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +void displ5_set_iomux_usdhc_spl(void) > +{ > + SETUP_IOMUX_PADS(usdhc4_pads); > +} > + > +void displ5_set_iomux_usdhc(void) > +{ > + SETUP_IOMUX_PADS(usdhc4_pads); > +} > + > +#else > +void displ5_set_iomux_usdhc_spl(void) {} > +void displ5_set_iomux_usdhc(void) {} > +#endif > diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h > new file mode 100644 > index 0000000000..6019e90c61 > --- /dev/null > +++ b/board/liebherr/display5/common.h > @@ -0,0 +1,42 @@ > +/* > + * Copyright (C) 2017 DENX Software Engineering > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __DISPL5_COMMON_H_ > +#define __DISPL5_COMMON_H_ > + > +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ > + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) > + > +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ > + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > + > +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ > + PAD_CTL_ODE | PAD_CTL_SRE_FAST) > + > +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ > + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > + > +void displ5_set_iomux_uart_spl(void); > +void displ5_set_iomux_uart(void); > +void displ5_set_iomux_ecspi_spl(void); > +void displ5_set_iomux_ecspi(void); > +void displ5_set_iomux_usdhc_spl(void); > +void displ5_set_iomux_usdhc(void); > + > +#endif /* __DISPL5_COMMON_H_ */ > diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c > new file mode 100644 > index 0000000000..5414ef77d3 > --- /dev/null > +++ b/board/liebherr/display5/display5.c > @@ -0,0 +1,384 @@ > +/* > + * Copyright (C) 2017 DENX Software Engineering > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/arch/mx6-ddr.h> > +#include <asm/arch/sys_proto.h> > +#include <errno.h> > +#include <asm/gpio.h> > +#include <malloc.h> > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm/mach-imx/mxc_i2c.h> > +#include <asm/mach-imx/boot_mode.h> > +#include <asm/mach-imx/spi.h> > +#include <mmc.h> > +#include <fsl_esdhc.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <i2c.h> > + > +#include <dm.h> > +#include <dm/platform_data/serial_mxc.h> > +#include <dm/platdata.h> > + > +#ifndef CONFIG_MXC_SPI > +#error "CONFIG_SPI must be set for this board" > +#error "Please check your config file" > +#endif > + > +#include "common.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static bool hw_ids_valid; > +static bool sw_ids_valid; > +static u32 cpu_id; > +static u32 unit_id; > + > +#define SW0 IMX_GPIO_NR(2, 4) > +#define SW1 IMX_GPIO_NR(2, 5) > +#define SW2 IMX_GPIO_NR(2, 6) > +#define SW3 IMX_GPIO_NR(2, 7) > +#define HW0 IMX_GPIO_NR(6, 7) > +#define HW1 IMX_GPIO_NR(6, 9) > +#define HW2 IMX_GPIO_NR(6, 10) > +#define HW3 IMX_GPIO_NR(6, 11) > +#define HW4 IMX_GPIO_NR(4, 7) > +#define HW5 IMX_GPIO_NR(4, 11) > +#define HW6 IMX_GPIO_NR(4, 13) > +#define HW7 IMX_GPIO_NR(4, 15) > + > +int gpio_table_sw_ids[] = { > + SW0, SW1, SW2, SW3 > +}; > + > +const char *gpio_table_sw_ids_names[] = { > + "sw0", "sw1", "sw2", "sw3" > +}; > + > +int gpio_table_hw_ids[] = { > + HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 > +}; > + > +const char *gpio_table_hw_ids_names[] = { > + "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" > +}; > + > +static int get_board_id(int *ids, const char **c, int size, > + bool *valid, u32 *id) > +{ > + int i, ret, val; > + > + *valid = false; > + > + for (i = 0; i < size; i++) { > + ret = gpio_request(ids[i], c[i]); > + if (ret) { > + printf("Can't request SWx gpios\n"); > + return ret; > + } > + } > + > + for (i = 0; i < size; i++) { > + ret = gpio_direction_input(ids[i]); > + if (ret) { > + printf("Can't set SWx gpios direction\n"); > + return ret; > + } > + } > + > + for (i = 0; i < size; i++) { > + val = gpio_get_value(ids[i]); > + if (val < 0) { > + printf("Can't get SW%d ID\n", i); > + *id = 0; > + return val; > + } > + *id |= val << i; > + } > + *valid = true; > + > + return 0; > +} > + > +int dram_init(void) > +{ > + gd->ram_size = imx_ddr_size(); > + > + return 0; > +} > + > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > +/* I2C1: TFA9879 */ > +struct i2c_pads_info i2c_pad_info0 = { > + .scl = { > + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, > + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, > + .gp = IMX_GPIO_NR(3, 21) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, > + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, > + .gp = IMX_GPIO_NR(3, 28) > + } > +}; > + > +/* I2C2: TIVO TM4C123 */ > +struct i2c_pads_info i2c_pad_info1 = { > + .scl = { > + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, > + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, > + .gp = IMX_GPIO_NR(2, 30) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, > + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, > + .gp = IMX_GPIO_NR(3, 16) > + } > +}; > + > +/* I2C3: PMIC PF0100, EEPROM AT24C256C */ > +struct i2c_pads_info i2c_pad_info2 = { > + .scl = { > + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, > + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, > + .gp = IMX_GPIO_NR(3, 17) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, > + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, > + .gp = IMX_GPIO_NR(3, 18) > + } > +}; > + > +iomux_v3_cfg_t const misc_pads[] = { > + /* Prod ID GPIO pins */ > + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), > + > + /* HW revision GPIO pins */ > + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), > + > + /* XTALOSC */ > + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +#ifdef CONFIG_FSL_ESDHC > +struct fsl_esdhc_cfg usdhc_cfg[1] = { > + { USDHC4_BASE_ADDR, 0, 8, }, > +}; > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + return 1; > +} > + > +int board_mmc_init(bd_t *bis) > +{ > + displ5_set_iomux_usdhc(); > + > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); > + > + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); > +} > +#endif /* CONFIG_FSL_ESDHC */ > + > +static void displ5_setup_ecspi(void) > +{ > + int ret; > + > + displ5_set_iomux_ecspi(); > + > + ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); > + if (!ret) > + gpio_direction_output(IMX_GPIO_NR(5, 29), 1); > + > + ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); > + if (!ret) > + gpio_direction_output(IMX_GPIO_NR(7, 0), 1); > +} > + > +#ifdef CONFIG_FEC_MXC > +iomux_v3_cfg_t const enet_pads[] = { > + MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), > + > + /* for old evalboard with R159 present and R160 not populated */ > + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), > + > + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > + > + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > + /*INT#_GBE*/ > + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +static void setup_iomux_enet(void) > +{ > + SETUP_IOMUX_PADS(enet_pads); > + gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ > +} > + > +int board_eth_init(bd_t *bd) > +{ > + struct phy_device *phydev; > + struct mii_dev *bus; > + int ret; > + > + setup_iomux_enet(); > + > + iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); > + > + ret = enable_fec_anatop_clock(0, ENET_125MHZ); > + if (ret) > + return ret; > + > + bus = fec_get_miibus(IMX_FEC_BASE, -1); > + if (!bus) > + return -ENODEV; > + > + /* > + * We use here the "rgmii-id" mode of operation and allow M88E1512 > + * PHY to use its internally callibrated RX/TX delays > + */ > + phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, > + PHY_INTERFACE_MODE_RGMII_ID); > + if (!phydev) { > + ret = -ENODEV; > + goto err_phy; > + } > + > + /* display5 due to PCB routing can only work with 100 Mbps */ > + phydev->advertising &= ~(ADVERTISED_1000baseX_Half | > + ADVERTISED_1000baseX_Full | > + SUPPORTED_1000baseT_Half | > + SUPPORTED_1000baseT_Full); > + > + ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); > + if (ret) > + goto err_sw; > + > + return 0; > + > +err_sw: > + free(phydev); > +err_phy: > + mdio_unregister(bus); > + free(bus); > + return ret; > +} > +#endif /* CONFIG_FEC_MXC */ > + > +/* > + * Do not overwrite the console > + * Always use serial for U-Boot console > + */ > +int overwrite_console(void) > +{ > + return 1; > +} > + > +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) > +int ft_board_setup(void *blob, bd_t *bd) > +{ > + fdt_fixup_ethernet(blob); > + return 0; > +} > +#endif > + > +int board_init(void) > +{ > + debug("board init\n"); > + /* address of boot parameters */ > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + > + /* Setup iomux for non console UARTS */ > + displ5_set_iomux_uart(); > + > + displ5_setup_ecspi(); > + > + SETUP_IOMUX_PADS(misc_pads); > + > + get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], > + ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id); > + debug("SWx unit_id 0x%x\n", unit_id); > + > + get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0], > + ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id); > + debug("HWx cpu_id 0x%x\n", cpu_id); > + > + if (hw_ids_valid && sw_ids_valid) > + printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id); > + > + udelay(25); > + > + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); > + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); > + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); > + > + return 0; > +} > + > +#ifdef CONFIG_CMD_BMODE > +static const struct boot_mode board_boot_modes[] = { > + /* eMMC, USDHC-4, 8-bit bus width */ > + /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */ > + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, > + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)}, > + {NULL, 0}, > +}; > + > +static void setup_boot_modes(void) > +{ > + add_board_boot_modes(board_boot_modes); > +} > +#else > +static inline void setup_boot_modes(void) {} > +#endif > + > +int misc_init_r(void) > +{ > + setup_boot_modes(); > + return 0; > +} > + > +static struct mxc_serial_platdata mxc_serial_plat = { > + .reg = (struct mxc_uart *)UART5_BASE, > +}; > + > +U_BOOT_DEVICE(mxc_serial) = { > + .name = "serial_mxc", > + .platdata = &mxc_serial_plat, > +}; > diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c > new file mode 100644 > index 0000000000..0a36e656c0 > --- /dev/null > +++ b/board/liebherr/display5/spl.c > @@ -0,0 +1,247 @@ > +/* > + * Copyright (C) 2017 DENX Software Engineering > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <spl.h> > +#include <libfdt.h> > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/mx6-ddr.h> > +#include <asm/arch/mx6-pins.h> > +#include "asm/arch/crm_regs.h" > +#include <asm/arch/sys_proto.h> > +#include <asm/arch/imx-regs.h> > +#include "asm/arch/iomux.h" > +#include <asm/mach-imx/iomux-v3.h> > +#include <environment.h> > +#include <fsl_esdhc.h> > +#include <netdev.h> > +#include "common.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { > + .dram_sdclk_0 = 0x00000030, > + .dram_sdclk_1 = 0x00000030, > + .dram_cas = 0x00000030, > + .dram_ras = 0x00000030, > + .dram_reset = 0x00000030, > + .dram_sdcke0 = 0x00003000, > + .dram_sdcke1 = 0x00003000, > + .dram_sdba2 = 0x00000000, > + .dram_sdodt0 = 0x00000030, > + .dram_sdodt1 = 0x00000030, > + > + .dram_sdqs0 = 0x00000030, > + .dram_sdqs1 = 0x00000030, > + .dram_sdqs2 = 0x00000030, > + .dram_sdqs3 = 0x00000030, > + .dram_sdqs4 = 0x00000030, > + .dram_sdqs5 = 0x00000030, > + .dram_sdqs6 = 0x00000030, > + .dram_sdqs7 = 0x00000030, > + > + .dram_dqm0 = 0x00000030, > + .dram_dqm1 = 0x00000030, > + .dram_dqm2 = 0x00000030, > + .dram_dqm3 = 0x00000030, > + .dram_dqm4 = 0x00000030, > + .dram_dqm5 = 0x00000030, > + .dram_dqm6 = 0x00000030, > + .dram_dqm7 = 0x00000030, > +}; > + > +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { > + .grp_ddr_type = 0x000c0000, > + .grp_ddrmode_ctl = 0x00020000, > + .grp_ddrpke = 0x00000000, > + .grp_addds = 0x00000030, > + .grp_ctlds = 0x00000030, > + .grp_ddrmode = 0x00020000, > + .grp_b0ds = 0x00000030, > + .grp_b1ds = 0x00000030, > + .grp_b2ds = 0x00000030, > + .grp_b3ds = 0x00000030, > + .grp_b4ds = 0x00000030, > + .grp_b5ds = 0x00000030, > + .grp_b6ds = 0x00000030, > + .grp_b7ds = 0x00000030, > +}; > + > +/* 4x128Mx16.cfg */ > +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { > + .p0_mpwldectrl0 = 0x002D0028, > + .p0_mpwldectrl1 = 0x0032002D, > + .p1_mpwldectrl0 = 0x00210036, > + .p1_mpwldectrl1 = 0x0019002E, > + .p0_mpdgctrl0 = 0x4349035C, > + .p0_mpdgctrl1 = 0x0348033D, > + .p1_mpdgctrl0 = 0x43550362, > + .p1_mpdgctrl1 = 0x03520316, > + .p0_mprddlctl = 0x41393940, > + .p1_mprddlctl = 0x3F3A3C47, > + .p0_mpwrdlctl = 0x413A423A, > + .p1_mpwrdlctl = 0x4042483E, > +}; > + > +/* MT41K128M16JT-125 (2Gb density) */ > +static const struct mx6_ddr3_cfg mt41k128m16jt_125 = { > + .mem_speed = 1600, > + .density = 2, > + .width = 16, > + .banks = 8, > + .rowaddr = 14, > + .coladdr = 10, > + .pagesz = 2, > + .trcd = 1375, > + .trcmin = 4875, > + .trasmin = 3500, > +}; > + > +static void ccgr_init(void) > +{ > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + > + writel(0x00C03F3F, &ccm->CCGR0); > + writel(0x0030FC3F, &ccm->CCGR1); > + writel(0x0FFFCFC0, &ccm->CCGR2); > + writel(0x3FF00000, &ccm->CCGR3); > + writel(0x00FFF300, &ccm->CCGR4); > + writel(0x0F0000C3, &ccm->CCGR5); > + writel(0x000003FF, &ccm->CCGR6); > +} > + > +static void spl_dram_init(void) > +{ > + struct mx6_ddr_sysinfo sysinfo = { > + /* width of data bus:0=16,1=32,2=64 */ > + .dsize = 2, > + /* config for full 4GB range so that get_mem_size() works */ > + .cs_density = 32, /* 32Gb per CS */ > + /* single chip select */ > + .ncs = 1, > + .cs1_mirror = 0, > + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ > + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ > + .walat = 1, /* Write additional latency */ > + .ralat = 5, /* Read additional latency */ > + .mif3_mode = 3, /* Command prediction working mode */ > + .bi_on = 1, /* Bank interleaving enabled */ > + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ > + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ > + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ > + .ddr_type = DDR_TYPE_DDR3, > + .refsel = 1, /* Refresh cycles at 32KHz */ > + .refr = 7, /* 8 refresh commands per refresh cycle */ > + }; > + > + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); > + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); > +} > + > +#ifdef CONFIG_SPL_SPI_SUPPORT > +static void displ5_init_ecspi(void) > +{ > + displ5_set_iomux_ecspi_spl(); > + enable_spi_clk(1, 1); > +} > +#else > +static inline void displ5_init_ecspi(void) { } > +#endif > + > +#ifdef CONFIG_SPL_MMC_SUPPORT > +static struct fsl_esdhc_cfg usdhc_cfg = { > + .esdhc_base = USDHC4_BASE_ADDR, > + .max_bus_width = 8, > +}; > + > +int board_mmc_init(bd_t *bd) > +{ > + displ5_set_iomux_usdhc_spl(); > + > + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); > + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; > + > + return fsl_esdhc_initialize(bd, &usdhc_cfg); > +} > +#endif > + > +void board_init_f(ulong dummy) > +{ > + ccgr_init(); > + > + arch_cpu_init(); > + > + gpr_init(); > + > + /* setup GP timer */ > + timer_init(); > + > + displ5_set_iomux_uart_spl(); > + > + /* UART clocks enabled and gd valid - init serial console */ > + preloader_console_init(); > + > + displ5_init_ecspi(); > + > + /* DDR initialization */ > + spl_dram_init(); > + > + /* Clear the BSS. */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + /* load/boot image from boot device */ > + board_init_r(NULL, 0); > +} > + > +void board_boot_order(u32 *spl_boot_list) > +{ > + /* Default boot sequence SPI -> MMC */ > + spl_boot_list[0] = spl_boot_device(); > + spl_boot_list[1] = BOOT_DEVICE_MMC1; > + spl_boot_list[2] = BOOT_DEVICE_UART; > + spl_boot_list[3] = BOOT_DEVICE_NONE; > + > +#ifdef CONFIG_SPL_ENV_SUPPORT > + /* 'fastboot' */ > + const char *s; > + > + env_init(); > + env_load(); > + > + s = env_get("BOOT_FROM"); > + if (s && strcmp(s, "ACTIVE") == 0) { > + spl_boot_list[0] = BOOT_DEVICE_MMC1; > + spl_boot_list[1] = spl_boot_device(); > + } > +#endif > +} > + > +void reset_cpu(ulong addr) {} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > + return 0; > +} > +#endif > + > +#ifdef CONFIG_SPL_OS_BOOT > +/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */ > +int spl_start_uboot(void) > +{ > + /* break into full u-boot on 'c' */ > + if (serial_tstc() && serial_getc() == 'c') > + return 1; > + > +#ifdef CONFIG_SPL_ENV_SUPPORT > + if (env_get_yesno("boot_os") != 1) > + return 1; > +#endif > + return 0; > +} > +#endif > diff --git a/configs/display5_defconfig b/configs/display5_defconfig > new file mode 100644 > index 0000000000..dfd9c2c298 > --- /dev/null > +++ b/configs/display5_defconfig > @@ -0,0 +1,62 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_MX6=y > +CONFIG_SPL_GPIO_SUPPORT=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_TARGET_DISPLAY5=y > +CONFIG_SPL_MMC_SUPPORT=y > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > +CONFIG_SPL_SPI_SUPPORT=y > +CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" > +CONFIG_FIT=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_OF_BOARD_SETUP=y > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" > +CONFIG_SPL=y > +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set > +CONFIG_SPL_DMA_SUPPORT=y > +CONFIG_SPL_ENV_SUPPORT=y > +CONFIG_SPL_SAVEENV=y > +CONFIG_SPL_I2C_SUPPORT=y > +CONFIG_SPL_OS_BOOT=y > +CONFIG_HUSH_PARSER=y > +CONFIG_SYS_PROMPT="display5 > " > +CONFIG_CMD_BOOTZ=y > +# CONFIG_CMD_ELF is not set > +CONFIG_CMD_ASKENV=y > +CONFIG_CRC32_VERIFY=y > +CONFIG_CMD_EEPROM=y > +# CONFIG_CMD_FPGA is not set > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PART=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_DHCP=y > +CONFIG_CMD_MII=y > +CONFIG_CMD_PING=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIME=y > +CONFIG_CMD_EXT2=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_FS_GENERIC=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" > +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" > +CONFIG_EFI_PARTITION=y > +# CONFIG_SPL_EFI_PARTITION is not set > +CONFIG_OF_CONTROL=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_BAR=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_MARVELL=y > +CONFIG_NETDEVICES=y > +CONFIG_FEC_MXC=y > +# CONFIG_SPL_DM_SERIAL is not set > +CONFIG_MXC_UART=y > diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig > new file mode 100644 > index 0000000000..3f10ffad03 > --- /dev/null > +++ b/configs/display5_factory_defconfig > @@ -0,0 +1,76 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_MX6=y > +CONFIG_SPL_GPIO_SUPPORT=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_TARGET_DISPLAY5=y > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > +CONFIG_SPL_SPI_SUPPORT=y > +CONFIG_FIT=y > +CONFIG_OF_BOARD_SETUP=y > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" > +CONFIG_BOOTDELAY=3 > +CONFIG_SPL=y > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set > +CONFIG_SPL_DMA_SUPPORT=y > +CONFIG_SPL_I2C_SUPPORT=y > +CONFIG_SPL_OS_BOOT=y > +CONFIG_SPL_USB_HOST_SUPPORT=y > +CONFIG_SPL_USB_GADGET_SUPPORT=y > +CONFIG_SPL_USB_SDP_SUPPORT=y > +CONFIG_HUSH_PARSER=y > +CONFIG_SYS_PROMPT="display5 factory > " > +CONFIG_BOOTCMD_OVERRIDE=y > +CONFIG_BOOTCOMMAND="run factory" > +CONFIG_CMD_BOOTZ=y > +# CONFIG_CMD_ELF is not set > +CONFIG_CMD_ASKENV=y > +CONFIG_CRC32_VERIFY=y > +CONFIG_CMD_EEPROM=y > +CONFIG_CMD_DFU=y > +# CONFIG_CMD_FPGA is not set > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PART=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_USB_SDP=y > +CONFIG_CMD_DHCP=y > +CONFIG_CMD_MII=y > +CONFIG_CMD_PING=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_TIME=y > +CONFIG_CMD_EXT2=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_FS_GENERIC=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" > +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" > +# CONFIG_SPL_EFI_PARTITION is not set > +CONFIG_PARTITION_TYPE_GUID=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_DFU_MMC=y > +CONFIG_DFU_SF=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_BAR=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_PHYLIB=y > +CONFIG_NETDEVICES=y > +CONFIG_FEC_MXC=y > +# CONFIG_SPL_DM_SERIAL is not set > +CONFIG_MXC_UART=y > +CONFIG_USB=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_MANUFACTURER="Liebherr" > +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 > +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 > +CONFIG_CI_UDC=y > +CONFIG_USB_GADGET_DOWNLOAD=y > +CONFIG_OF_LIBFDT=y > diff --git a/include/configs/display5.h b/include/configs/display5.h > new file mode 100644 > index 0000000000..c41ab8b5e2 > --- /dev/null > +++ b/include/configs/display5.h > @@ -0,0 +1,408 @@ > +/* > + * Copyright (C) 2017 > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include "mx6_common.h" > + > +/* Falcon Mode */ > +#define CONFIG_CMD_SPL > +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 > +#define CONFIG_CMD_SPL_WRITE_SIZE (44 * SZ_1K) > + > +/* Falcon Mode - MMC support */ > +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 > +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ > + (CONFIG_CMD_SPL_WRITE_SIZE / 512) > +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x100 /* 128KiB */ > + > +/* > + * display5 SPI-NOR memory layout > + * > + * The definition can be found in Kconfig's > + * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT > + * > + * 0x000000 - 0x020000 : SPI.SPL (128KiB) > + * 0x020000 - 0x120000 : SPI.u-boot (1MiB) > + * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB) > + * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB) > + * 0x140000 - 0x940000 : SPI.fitImage-recovery (8MiB) > + * 0x940000 - 0xD40000 : SPI.swupdate-kernel-FIT (4MiB) > + * 0xD40000 - 0x1540000 : SPI.swupdate-initramfs (8MiB) > + */ > + > +#ifndef CONFIG_SPL_BUILD > +#define CONFIG_MTD_DEVICE > +#define CONFIG_SPI_FLASH_MTD > +#define CONFIG_MTD_PARTITIONS > +#endif > + > +/* Below values are "dummy" - only to avoid build break */ > +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 > +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 > +#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 > + > +#include "imx6_spl.h" > +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 > +#define CONFIG_SPL_SPI_LOAD > + > +#define CONFIG_CMDLINE_TAG > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > +#define CONFIG_REVISION_TAG > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) > +#define CONFIG_MISC_INIT_R > + > +/*#define CONFIG_MXC_UART*/ > +#define CONFIG_MXC_UART_BASE UART5_BASE > + > +/* SPI NOR Flash */ > +#ifdef CONFIG_CMD_SF > +#define CONFIG_MXC_SPI > +#define CONFIG_SF_DEFAULT_BUS 1 > +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(5, 29) << 8)) > +#define CONFIG_SF_DEFAULT_SPEED 50000000 > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 > +#endif > + > +/* I2C Configs */ > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_MXC > +#define CONFIG_SYS_I2C_MXC_I2C1 > +#define CONFIG_SYS_I2C_MXC_I2C2 > +#define CONFIG_SYS_I2C_MXC_I2C3 > +#define CONFIG_I2C_MULTI_BUS > +#define CONFIG_SYS_I2C_SPEED 100000 > +#define CONFIG_I2C_EDID > +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 > + > +/* Ethernet */ > +#ifdef CONFIG_FEC_MXC > +#define IMX_FEC_BASE ENET_BASE_ADDR > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define CONFIG_ETHPRIME "FEC" > +#define CONFIG_FEC_MXC_PHYADDR 0 > +#define CONFIG_MII > +#endif > + > +/* MMC Configs */ > +#define CONFIG_FSL_ESDHC > +#define CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > +#define CONFIG_SUPPORT_EMMC_BOOT > + > +/* allow to overwrite serial and ethaddr */ > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_BAUDRATE 115200 > + > +#ifndef CONFIG_BOOTCOMMAND > +#define CONFIG_BOOTCOMMAND "run boot_mmc" > +#endif > + > +#define PARTS_DEFAULT \ > + /* Linux partitions */ \ > + "partitions=" \ > + "uuid_disk=${uuid_gpt_disk};" \ > + "name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \ > + "name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \ > + "name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \ > + "name=rootfs2,size=1528M,uuid=${uuid_gpt_rootfs2};" \ > + "name=data,size=-,uuid=${uuid_gpt_data}\0" > + > +#define FACTORY_PROCEDURE \ > + "echo '#######################';" \ > + "echo '# Factory Boot #';" \ > + "echo '#######################';" \ > + "env default -a;" \ > + "saveenv;" \ > + "gpt write mmc ${mmcdev} ${partitions};" \ > + "run tftp_sf_SPL;" \ > + "run tftp_sf_uboot;" \ > + TFTP_UPDATE_KERNEL \ > + "run tftp_sf_fitImg_recovery;" \ > + "run tftp_sf_fitImg_SWU;" \ > + "run tftp_sf_initramfs_SWU;" \ > + TFTP_UPDATE_ROOTFS \ > + "echo '#######################';" \ > + "echo '# END - OK #';" \ > + "echo '#######################';" \ > + "setenv bootcmd 'env default -a; saveenv; run falcon_setup; reset';" \ > + "setenv boot_os 'n';" \ > + "saveenv;" \ > + "reset;" > + > +#define SWUPDATE_RECOVERY_PROCEDURE \ > + "echo '#######################';" \ > + "echo '# RECOVERY SWUupdate #';" \ > + "echo '#######################';" \ > + "setenv loadaddr_swu_initramfs 0x14000000;" \ > + "setenv bootargs console=${console} " \ > + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ > + ":${hostname}::off root=/dev/ram rw;" \ > + "sf probe;" \ > + "sf read ${loadaddr} swu-kernel;" \ > + "sf read ${loadaddr_swu_initramfs} swu-initramfs;" \ > + "bootm ${loadaddr} ${loadaddr_swu_initramfs};" > + > +#define KERNEL_RECOVERY_PROCEDURE \ > + "echo '#######################';" \ > + "echo '# RECOVERY KERNEL IMG #';" \ > + "echo '#######################';" \ > + "sf probe;" \ > + "sf read ${loadaddr} lin-recovery;" \ > + "bootm;" > + > +#define SETUP_BOOTARGS \ > + "run set_rootfs_part;" \ > + "setenv bootargs ${bootargs} console=${console} " \ > + "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \ > + "rootwait rootfstype=ext4 rw; " \ > + "run set_kernel_part;" \ > + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ > + "mmc read ${loadaddr} ${lba_start} 0x2000; " \ > + "setenv fdt_conf imx6q-${board}-${display}.dtb; " > + > +/* All the numbers are in LBAs */ > +#define __TFTP_UPDATE_KERNEL \ > + "tftp_mmc_fitImg=" \ > + "if test ! -n ${kernel_part}; then " \ > + "setenv kernel_part ${kernel_part_active};" \ > + "fi;" \ > + "if tftp ${loadaddr} ${kernel_file}; then " \ > + "setexpr fw_sz ${filesize} / 0x200; " \ > + "setexpr fw_sz ${fw_sz} + 1; " \ > + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ > + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ > + "; fi\0" \ > + > +#define TFTP_UPDATE_KERNEL \ > + "setenv kernel_part ${kernel_part_active};" \ > + "run tftp_mmc_fitImg;" \ > + "setenv kernel_part ${kernel_part_backup};" \ > + "run tftp_mmc_fitImg;" \ > + > +#define __TFTP_UPDATE_ROOTFS \ > + "tftp_mmc_rootfs=" \ > + "if test ! -n ${rootfs_part}; then " \ > + "setenv rootfs_part ${rootfs_part_active};" \ > + "fi;" \ > + "if tftp ${loadaddr} ${rootfs_file}; then " \ > + "setexpr fw_sz ${filesize} / 0x200; " \ > + "setexpr fw_sz ${fw_sz} + 1; " \ > + "part start mmc ${mmcdev} ${rootfs_part} lba_start; " \ > + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ > + "; fi\0" \ > + > +/* To save some considerable time, we only once download the rootfs image */ > +/* and store it on 'active' and 'backup' rootfs partitions */ > +#define TFTP_UPDATE_ROOTFS \ > + "setenv rootfs_part ${rootfs_part_active};" \ > + "run tftp_mmc_rootfs;" \ > + "part start mmc ${mmcdev} ${rootfs_part_backup} lba_start;" \ > + "mmc write ${loadaddr} ${lba_start} ${fw_sz};" \ > + > +#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \ > + "tftp_sf_fitImg_SWU=" \ > + "if tftp ${loadaddr} ${kernel_file}; then " \ > + "sf probe;" \ > + "sf erase swu-kernel +${filesize};" \ > + "sf write ${loadaddr} swu-kernel ${filesize};" \ > + "; fi\0" \ > + > +#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ > + "swu_initramfs_file=swupdate-image-display5.ext3.gz.u-boot\0" \ > + "tftp_sf_initramfs_SWU=" \ > + "if tftp ${loadaddr} ${swu_initramfs_file}; then " \ > + "sf probe;" \ > + "sf erase swu-initramfs +${filesize};" \ > + "sf write ${loadaddr} swu-initramfs ${filesize};" \ > + "; fi\0" \ > + > +#define TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ > + "kernel_recovery_file=fitImage-initramfs\0" \ > + "tftp_sf_fitImg_recovery=" \ > + "if tftp ${loadaddr} ${kernel_recovery_file}; then " \ > + "sf probe;" \ > + "sf erase lin-recovery +${filesize};" \ > + "sf write ${loadaddr} lin-recovery ${filesize};" \ > + "; fi\0" \ > + > +#define TFTP_UPDATE_BOOTLOADER \ > + "ubootfile=u-boot.img\0" \ > + "ubootfileSPL=SPL\0" \ > + "tftp_sf_uboot=" \ > + "if tftp ${loadaddr} ${ubootfile}; then " \ > + "sf probe;" \ > + "sf erase u-boot +${filesize};" \ > + "sf write ${loadaddr} u-boot ${filesize}" \ > + "; fi\0" \ > + "tftp_sf_SPL=" \ > + "if tftp ${loadaddr} ${ubootfileSPL}; then " \ > + "sf probe;" \ > + "setexpr uboot_SPL_size ${filesize} + 0x400;" \ > + "sf erase 0x0 +${uboot_SPL_size};" \ > + "sf write ${loadaddr} 0x400 ${filesize};" \ > + "fi\0" \ > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + PARTS_DEFAULT \ > + "display=tianma-tm070-800x480\0" \ > + "board=display5\0" \ > + "mmcdev=0\0" \ > + "altbootcmd=run recovery\0" \ > + "bootdelay=1\0" \ > + "baudrate=115200\0" \ > + "bootcmd=" CONFIG_BOOTCOMMAND "\0" \ > + "factory=" FACTORY_PROCEDURE "\0" \ > + "bootlimit=3\0" \ > + "ethact=FEC\0" \ > + "netdev=eth0\0" \ > + "boot_os=y\0" \ > + "hostname=display5\0" \ > + "loadaddr=0x12000000\0" \ > + "fdtaddr=0x12800000\0" \ > + "console=ttymxc4,115200 quiet\0" \ > + "fdtfile=imx6q-display5.dtb\0" \ > + "fdt_high=0xffffffff\0" \ > + "initrd_high=0xffffffff\0" \ > + "kernel_file=fitImage\0" \ > + "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ > + "download_kernel=" \ > + "tftpboot ${loadaddr} ${kernel_file};\0" \ > + "boot_kernel_recovery=" KERNEL_RECOVERY_PROCEDURE "\0" \ > + "boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \ > + "recovery=" \ > + "if test ${BOOT_FROM_RECOVERY} = SWU; then " \ > + "echo BOOT: RECOVERY: SWU;" \ > + "run boot_swu_recovery;" \ > + "else " \ > + "echo BOOT: RECOVERY: Linux;" \ > + "run boot_kernel_recovery;" \ > + "fi\0" \ > + "boot_tftp=" \ > + "if run download_kernel; then " \ > + "setenv bootargs console=${console} " \ > + "root=/dev/mmcblk0p2 rootwait;" \ > + "bootm ${loadaddr} - ${fdtaddr};" \ > + "fi\0" \ > + "addip=setenv bootargs ${bootargs} " \ > + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ > + "${hostname}:eth0:on" \ > + "\0" \ > + "nfsargs=setenv bootargs " \ > + "root=/dev/nfs rw " \ > + "nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \ > + "\0" \ > + "rootpath=/srv/tftp/DISP5/rootfs\0" \ > + "boot_nfs=" \ > + "if run download_kernel; then " \ > + "run nfsargs;" \ > + "run addip;" \ > + "setenv bootargs ${bootargs} console=${console};" \ > + "setenv fdt_conf imx6q-${board}-${display}.dtb; " \ > + "bootm ${loadaddr}#conf@${fdt_conf};" \ > + "fi\0" \ > + "falcon_setup=" \ > + "if mmc dev ${mmcdev}; then " \ > + SETUP_BOOTARGS \ > + "spl export fdt ${loadaddr}#conf@${fdt_conf};" \ > + "setexpr fw_sz ${fdtargslen} / 0x200; " \ > + "setexpr fw_sz ${fw_sz} + 1; " \ > + "mmc write ${fdtargsaddr} " \ > + __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" ${fw_sz}; " \ > + "fi\0" \ > + "boot_mmc=" \ > + "if mmc dev ${mmcdev}; then " \ > + SETUP_BOOTARGS \ > + "bootm ${loadaddr}#conf@${fdt_conf};" \ > + "fi\0" \ > + "set_kernel_part=" \ > + "if test ${BOOT_FROM} = ACTIVE; then " \ > + "setenv kernel_part ${kernel_part_active};" \ > + "echo BOOT: ACTIVE;" \ > + "else if test ${BOOT_FROM} = BACKUP; then " \ > + "setenv kernel_part ${kernel_part_backup};" \ > + "echo BOOT: BACKUP;" \ > + "else " \ > + "run recovery;" \ > + "fi;fi\0" \ > + "set_rootfs_part=" \ > + "if test ${BOOT_FROM} = ACTIVE; then " \ > + "setenv rootfs_part ${rootfs_part_active};" \ > + "else if test ${BOOT_FROM} = BACKUP; then " \ > + "setenv rootfs_part ${rootfs_part_backup};" \ > + "else " \ > + "run recovery;" \ > + "fi;fi\0" \ > + "BOOT_FROM=ACTIVE\0" \ > + "BOOT_FROM_RECOVERY=Linux\0" \ > + TFTP_UPDATE_BOOTLOADER \ > + "kernel_part_active=1\0" \ > + "kernel_part_backup=3\0" \ > + __TFTP_UPDATE_KERNEL \ > + "rootfs_part_active=2\0" \ > + "rootfs_part_backup=4\0" \ > + "rootfs_file=core-image-lwn-display5.ext4\0" \ > + __TFTP_UPDATE_ROOTFS \ > + TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ > + TFTP_UPDATE_RECOVERY_SWU_KERNEL \ > + TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ > + "\0" \ > + > +/* Miscellaneous configurable options */ > +#undef CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_CBSIZE 2048 > + > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > +#define CONFIG_SYS_MAXARGS 32 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 > +#define CONFIG_SYS_HZ 1000 > + > +/* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > + > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > + > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* Commands */ > +#define CONFIG_MTD_PARTITIONS > +#define CONFIG_MTD_DEVICE > + > +/* ENV config */ > +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH > +#define CONFIG_ENV_SIZE (SZ_64K) > +/* The 0x120000 value corresponds to above SPI-NOR memory MAP */ > +#define CONFIG_ENV_OFFSET (0x120000) > +#define CONFIG_ENV_SECT_SIZE (SZ_64K) > +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT > +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ > + CONFIG_ENV_SECT_SIZE) > +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE > + > +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS > +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS > +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE > +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED > +#endif > + > +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) > +#endif /* __CONFIG_H */ >
Hi Stefano, > Hi Lukasz, > > On 31/10/2017 17:58, Lukasz Majewski wrote: > > This commit provides support for LWN's IMX6Q based DISPLAY5 board. > > > > I would merge it, but why the commit message is still "(for > v2017.11-rc2+)" ? This goes into git history if I merge it. > > Can I drop it by merging ? Yes. Please. (I should not put it there in a first place). Thanks :-) > > Best regards, > Stefano > > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > > > > --- > > > > Changes in v4: > > - Refactor obscure sw/hw rev code for display5 board > > - replace get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > > with imx_ddr_size() > > - remove PHYS_SDRAM_SIZE from display5.h > > - Replace non generic setup of RGMII pins voltage levels with a > > generic function > > - Move displ5_set_iomux_uart() - non console UART init to > > board_init() > > - Disable board_early_init_f() calls (prod/factory) > > - Move mtdparts to Kconfig for production and flash u-boot > > > > Changes in v3: > > - Remove ip custom data > > - Cleanup SPL code > > > > Changes in v2: > > - Update to newest mainline u-boot > > > > arch/arm/dts/imx6q-display5.dts | 18 ++ > > arch/arm/mach-imx/mx6/Kconfig | 7 + > > board/liebherr/display5/Kconfig | 18 ++ > > board/liebherr/display5/MAINTAINERS | 7 + > > board/liebherr/display5/Makefile | 11 + > > board/liebherr/display5/common.c | 111 ++++++++++ > > board/liebherr/display5/common.h | 42 ++++ > > board/liebherr/display5/display5.c | 384 > > +++++++++++++++++++++++++++++++++ > > board/liebherr/display5/spl.c | 247 ++++++++++++++++++++++ > > configs/display5_defconfig | 62 ++++++ > > configs/display5_factory_defconfig | 76 +++++++ > > include/configs/display5.h | 408 > > ++++++++++++++++++++++++++++++++++++ 12 files changed, 1391 > > insertions(+) create mode 100644 arch/arm/dts/imx6q-display5.dts > > create mode 100644 board/liebherr/display5/Kconfig create mode > > 100644 board/liebherr/display5/MAINTAINERS create mode 100644 > > board/liebherr/display5/Makefile create mode 100644 > > board/liebherr/display5/common.c create mode 100644 > > board/liebherr/display5/common.h create mode 100644 > > board/liebherr/display5/display5.c create mode 100644 > > board/liebherr/display5/spl.c create mode 100644 > > configs/display5_defconfig create mode 100644 > > configs/display5_factory_defconfig create mode 100644 > > include/configs/display5.h > > > > diff --git a/arch/arm/dts/imx6q-display5.dts > > b/arch/arm/dts/imx6q-display5.dts new file mode 100644 > > index 0000000000..50347ff26b > > --- /dev/null > > +++ b/arch/arm/dts/imx6q-display5.dts > > @@ -0,0 +1,18 @@ > > +/* > > + * Copyright 2017 > > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > > + * > > + * This program is free software; you can redistribute it and/or > > modify > > + * it under the terms of the GNU General Public License version 2 > > as > > + * published by the Free Software Foundation. > > + * > > + */ > > + > > +/dts-v1/; > > + > > +#include "imx6q.dtsi" > > + > > +/ { > > + model = "Liebherr (LWN) display5 i.MX6 Quad Board"; > > + compatible = "lwn,display5", "fsl,imx6q"; > > +}; > > diff --git a/arch/arm/mach-imx/mx6/Kconfig > > b/arch/arm/mach-imx/mx6/Kconfig index b82db3af22..fd73c67fde 100644 > > --- a/arch/arm/mach-imx/mx6/Kconfig > > +++ b/arch/arm/mach-imx/mx6/Kconfig > > @@ -138,6 +138,12 @@ config TARGET_DHCOMIMX6 > > select DM_THERMAL > > imply CMD_SPL > > > > +config TARGET_DISPLAY5 > > + bool "LWN DISPLAY5 board" > > + select SUPPORT_SPL > > + select DM > > + select DM_SERIAL > > + > > config TARGET_EMBESTMX6BOARDS > > bool "embestmx6boards" > > select BOARD_LATE_INIT > > @@ -459,6 +465,7 @@ source "board/phytec/pfla02/Kconfig" > > source "board/gateworks/gw_ventana/Kconfig" > > source "board/kosagi/novena/Kconfig" > > source "board/samtec/vining_2000/Kconfig" > > +source "board/liebherr/display5/Kconfig" > > source "board/liebherr/mccmon6/Kconfig" > > source "board/logicpd/imx6/Kconfig" > > source "board/seco/Kconfig" > > diff --git a/board/liebherr/display5/Kconfig > > b/board/liebherr/display5/Kconfig new file mode 100644 > > index 0000000000..b096c8917a > > --- /dev/null > > +++ b/board/liebherr/display5/Kconfig > > @@ -0,0 +1,18 @@ > > +if TARGET_DISPLAY5 > > + > > +config SYS_CPU > > + default "armv7" > > + > > +config SYS_BOARD > > + default "display5" > > + > > +config SYS_VENDOR > > + default "liebherr" > > + > > +config SYS_SOC > > + default "mx6" > > + > > +config SYS_CONFIG_NAME > > + default "display5" > > + > > +endif > > diff --git a/board/liebherr/display5/MAINTAINERS > > b/board/liebherr/display5/MAINTAINERS new file mode 100644 > > index 0000000000..52178318b5 > > --- /dev/null > > +++ b/board/liebherr/display5/MAINTAINERS > > @@ -0,0 +1,7 @@ > > +DISPLAY5 BOARD > > +M: Lukasz Majewski <lukma@denx.de> > > +S: Maintained > > +F: board/liebherr/display5/ > > +F: include/configs/display5.h > > +F: configs/display5_defconfig > > +F: configs/display5_factory_defconfig > > diff --git a/board/liebherr/display5/Makefile > > b/board/liebherr/display5/Makefile new file mode 100644 > > index 0000000000..f934672428 > > --- /dev/null > > +++ b/board/liebherr/display5/Makefile > > @@ -0,0 +1,11 @@ > > +# > > +# Copyright (C) 2017, DENX Software Engineering > > +# Lukasz Majewski <lukma@denx.de> > > +# > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > +ifdef CONFIG_SPL_BUILD > > +obj-y = common.o spl.o > > +else > > +obj-y := common.o display5.o > > +endif > > diff --git a/board/liebherr/display5/common.c > > b/board/liebherr/display5/common.c new file mode 100644 > > index 0000000000..03f585b3aa > > --- /dev/null > > +++ b/board/liebherr/display5/common.c > > @@ -0,0 +1,111 @@ > > +/* > > + * Copyright (C) 2017 DENX Software Engineering > > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <asm/mach-imx/iomux-v3.h> > > +#include <asm/arch/mx6-pins.h> > > +#include "common.h" > > + > > +iomux_v3_cfg_t const uart_pads[] = { > > + /* UART4 */ > > + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > + MX6_PAD_CSI0_DAT16__UART4_RTS_B | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > + MX6_PAD_CSI0_DAT17__UART4_CTS_B | > > MUX_PAD_CTRL(UART_PAD_CTRL), +}; > > + > > +iomux_v3_cfg_t const uart_console_pads[] = { > > + /* UART5 */ > > + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > + MX6_PAD_CSI0_DAT18__UART5_RTS_B | > > MUX_PAD_CTRL(UART_PAD_CTRL), > > + MX6_PAD_CSI0_DAT19__UART5_CTS_B | > > MUX_PAD_CTRL(UART_PAD_CTRL), +}; > > + > > +void displ5_set_iomux_uart_spl(void) > > +{ > > + SETUP_IOMUX_PADS(uart_console_pads); > > +} > > + > > +void displ5_set_iomux_uart(void) > > +{ > > + SETUP_IOMUX_PADS(uart_pads); > > +} > > + > > +#ifdef CONFIG_MXC_SPI > > +iomux_v3_cfg_t const ecspi_pads[] = { > > + /* SPI3 */ > > + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | > > MUX_PAD_CTRL(SPI_PAD_CTRL), > > + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | > > MUX_PAD_CTRL(SPI_PAD_CTRL), > > + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | > > MUX_PAD_CTRL(SPI_PAD_CTRL), > > + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_DISP0_DAT5__ECSPI3_SS2 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_DISP0_DAT6__ECSPI3_SS3 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_DISP0_DAT7__ECSPI3_RDY | > > MUX_PAD_CTRL(NO_PAD_CTRL), +}; > > + > > +iomux_v3_cfg_t const ecspi2_pads[] = { > > + /* SPI2, NOR Flash nWP, CS0 */ > > + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | > > MUX_PAD_CTRL(SPI_PAD_CTRL), > > + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | > > MUX_PAD_CTRL(SPI_PAD_CTRL), > > + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | > > MUX_PAD_CTRL(SPI_PAD_CTRL), > > + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_SD3_DAT5__GPIO7_IO00 | > > MUX_PAD_CTRL(NO_PAD_CTRL), +}; > > + > > +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) > > +{ > > + if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8)) > > + return -EINVAL; > > + > > + return IMX_GPIO_NR(5, 29); > > +} > > + > > +void displ5_set_iomux_ecspi_spl(void) > > +{ > > + SETUP_IOMUX_PADS(ecspi2_pads); > > +} > > + > > +void displ5_set_iomux_ecspi(void) > > +{ > > + SETUP_IOMUX_PADS(ecspi_pads); > > +} > > + > > +#else > > +void displ5_set_iomux_ecspi_spl(void) {} > > +void displ5_set_iomux_ecspi(void) {} > > +#endif > > + > > +#ifdef CONFIG_FSL_ESDHC > > +iomux_v3_cfg_t const usdhc4_pads[] = { > > + MX6_PAD_SD4_CLK__SD4_CLK | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_CMD__SD4_CMD | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT0__SD4_DATA0 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT1__SD4_DATA1 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT2__SD4_DATA2 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT3__SD4_DATA3 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT4__SD4_DATA4 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT5__SD4_DATA5 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT6__SD4_DATA6 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_SD4_DAT7__SD4_DATA7 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NANDF_ALE__SD4_RESET | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; > > + > > +void displ5_set_iomux_usdhc_spl(void) > > +{ > > + SETUP_IOMUX_PADS(usdhc4_pads); > > +} > > + > > +void displ5_set_iomux_usdhc(void) > > +{ > > + SETUP_IOMUX_PADS(usdhc4_pads); > > +} > > + > > +#else > > +void displ5_set_iomux_usdhc_spl(void) {} > > +void displ5_set_iomux_usdhc(void) {} > > +#endif > > diff --git a/board/liebherr/display5/common.h > > b/board/liebherr/display5/common.h new file mode 100644 > > index 0000000000..6019e90c61 > > --- /dev/null > > +++ b/board/liebherr/display5/common.h > > @@ -0,0 +1,42 @@ > > +/* > > + * Copyright (C) 2017 DENX Software Engineering > > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#ifndef __DISPL5_COMMON_H_ > > +#define __DISPL5_COMMON_H_ > > + > > +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > > + > > +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > > + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ > > + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) > > + > > +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | > > \ > > + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED > > | \ > > + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) > > + > > +#define SPI_PAD_CTRL (PAD_CTL_HYS | > > \ > > + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | > > \ > > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > > + > > +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE > > | \ > > + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ > > + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ > > + PAD_CTL_ODE | PAD_CTL_SRE_FAST) > > + > > +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | > > \ > > + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > > + > > +void displ5_set_iomux_uart_spl(void); > > +void displ5_set_iomux_uart(void); > > +void displ5_set_iomux_ecspi_spl(void); > > +void displ5_set_iomux_ecspi(void); > > +void displ5_set_iomux_usdhc_spl(void); > > +void displ5_set_iomux_usdhc(void); > > + > > +#endif /* __DISPL5_COMMON_H_ */ > > diff --git a/board/liebherr/display5/display5.c > > b/board/liebherr/display5/display5.c new file mode 100644 > > index 0000000000..5414ef77d3 > > --- /dev/null > > +++ b/board/liebherr/display5/display5.c > > @@ -0,0 +1,384 @@ > > +/* > > + * Copyright (C) 2017 DENX Software Engineering > > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <dm.h> > > +#include <asm/io.h> > > +#include <asm/arch/clock.h> > > +#include <asm/arch/imx-regs.h> > > +#include <asm/arch/iomux.h> > > +#include <asm/arch/mx6-pins.h> > > +#include <asm/arch/mx6-ddr.h> > > +#include <asm/arch/sys_proto.h> > > +#include <errno.h> > > +#include <asm/gpio.h> > > +#include <malloc.h> > > +#include <asm/mach-imx/iomux-v3.h> > > +#include <asm/mach-imx/mxc_i2c.h> > > +#include <asm/mach-imx/boot_mode.h> > > +#include <asm/mach-imx/spi.h> > > +#include <mmc.h> > > +#include <fsl_esdhc.h> > > +#include <miiphy.h> > > +#include <netdev.h> > > +#include <i2c.h> > > + > > +#include <dm.h> > > +#include <dm/platform_data/serial_mxc.h> > > +#include <dm/platdata.h> > > + > > +#ifndef CONFIG_MXC_SPI > > +#error "CONFIG_SPI must be set for this board" > > +#error "Please check your config file" > > +#endif > > + > > +#include "common.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static bool hw_ids_valid; > > +static bool sw_ids_valid; > > +static u32 cpu_id; > > +static u32 unit_id; > > + > > +#define SW0 IMX_GPIO_NR(2, 4) > > +#define SW1 IMX_GPIO_NR(2, 5) > > +#define SW2 IMX_GPIO_NR(2, 6) > > +#define SW3 IMX_GPIO_NR(2, 7) > > +#define HW0 IMX_GPIO_NR(6, 7) > > +#define HW1 IMX_GPIO_NR(6, 9) > > +#define HW2 IMX_GPIO_NR(6, 10) > > +#define HW3 IMX_GPIO_NR(6, 11) > > +#define HW4 IMX_GPIO_NR(4, 7) > > +#define HW5 IMX_GPIO_NR(4, 11) > > +#define HW6 IMX_GPIO_NR(4, 13) > > +#define HW7 IMX_GPIO_NR(4, 15) > > + > > +int gpio_table_sw_ids[] = { > > + SW0, SW1, SW2, SW3 > > +}; > > + > > +const char *gpio_table_sw_ids_names[] = { > > + "sw0", "sw1", "sw2", "sw3" > > +}; > > + > > +int gpio_table_hw_ids[] = { > > + HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 > > +}; > > + > > +const char *gpio_table_hw_ids_names[] = { > > + "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" > > +}; > > + > > +static int get_board_id(int *ids, const char **c, int size, > > + bool *valid, u32 *id) > > +{ > > + int i, ret, val; > > + > > + *valid = false; > > + > > + for (i = 0; i < size; i++) { > > + ret = gpio_request(ids[i], c[i]); > > + if (ret) { > > + printf("Can't request SWx gpios\n"); > > + return ret; > > + } > > + } > > + > > + for (i = 0; i < size; i++) { > > + ret = gpio_direction_input(ids[i]); > > + if (ret) { > > + printf("Can't set SWx gpios direction\n"); > > + return ret; > > + } > > + } > > + > > + for (i = 0; i < size; i++) { > > + val = gpio_get_value(ids[i]); > > + if (val < 0) { > > + printf("Can't get SW%d ID\n", i); > > + *id = 0; > > + return val; > > + } > > + *id |= val << i; > > + } > > + *valid = true; > > + > > + return 0; > > +} > > + > > +int dram_init(void) > > +{ > > + gd->ram_size = imx_ddr_size(); > > + > > + return 0; > > +} > > + > > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > > +/* I2C1: TFA9879 */ > > +struct i2c_pads_info i2c_pad_info0 = { > > + .scl = { > > + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, > > + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, > > + .gp = IMX_GPIO_NR(3, 21) > > + }, > > + .sda = { > > + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, > > + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, > > + .gp = IMX_GPIO_NR(3, 28) > > + } > > +}; > > + > > +/* I2C2: TIVO TM4C123 */ > > +struct i2c_pads_info i2c_pad_info1 = { > > + .scl = { > > + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, > > + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, > > + .gp = IMX_GPIO_NR(2, 30) > > + }, > > + .sda = { > > + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, > > + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, > > + .gp = IMX_GPIO_NR(3, 16) > > + } > > +}; > > + > > +/* I2C3: PMIC PF0100, EEPROM AT24C256C */ > > +struct i2c_pads_info i2c_pad_info2 = { > > + .scl = { > > + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, > > + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, > > + .gp = IMX_GPIO_NR(3, 17) > > + }, > > + .sda = { > > + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, > > + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, > > + .gp = IMX_GPIO_NR(3, 18) > > + } > > +}; > > + > > +iomux_v3_cfg_t const misc_pads[] = { > > + /* Prod ID GPIO pins */ > > + MX6_PAD_NANDF_D4__GPIO2_IO04 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_NANDF_D5__GPIO2_IO05 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_NANDF_D6__GPIO2_IO06 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_NANDF_D7__GPIO2_IO07 | > > MUX_PAD_CTRL(NO_PAD_CTRL), + > > + /* HW revision GPIO pins */ > > + MX6_PAD_NANDF_CLE__GPIO6_IO07 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_NANDF_RB0__GPIO6_IO10 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_NANDF_CS0__GPIO6_IO11 | > > MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), > > + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), > > + > > + /* XTALOSC */ > > + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | > > MUX_PAD_CTRL(NO_PAD_CTRL), +}; > > + > > +#ifdef CONFIG_FSL_ESDHC > > +struct fsl_esdhc_cfg usdhc_cfg[1] = { > > + { USDHC4_BASE_ADDR, 0, 8, }, > > +}; > > + > > +int board_mmc_getcd(struct mmc *mmc) > > +{ > > + return 1; > > +} > > + > > +int board_mmc_init(bd_t *bis) > > +{ > > + displ5_set_iomux_usdhc(); > > + > > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); > > + > > + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); > > +} > > +#endif /* CONFIG_FSL_ESDHC */ > > + > > +static void displ5_setup_ecspi(void) > > +{ > > + int ret; > > + > > + displ5_set_iomux_ecspi(); > > + > > + ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); > > + if (!ret) > > + gpio_direction_output(IMX_GPIO_NR(5, 29), 1); > > + > > + ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); > > + if (!ret) > > + gpio_direction_output(IMX_GPIO_NR(7, 0), 1); > > +} > > + > > +#ifdef CONFIG_FEC_MXC > > +iomux_v3_cfg_t const enet_pads[] = { > > + MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_ENET_MDIO__ENET_MDIO | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_ENET_MDC__ENET_MDC | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | > > MUX_PAD_CTRL(ENET_PAD_CTRL), + > > + /* for old evalboard with R159 present and R160 not > > populated */ > > + MX6_PAD_GPIO_16__ENET_REF_CLK | > > MUX_PAD_CTRL(NO_PAD_CTRL), + > > + MX6_PAD_RGMII_TXC__RGMII_TXC | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_TD0__RGMII_TD0 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_TD1__RGMII_TD1 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_TD2__RGMII_TD2 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_TD3__RGMII_TD3 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | > > MUX_PAD_CTRL(ENET_PAD_CTRL), + > > + MX6_PAD_RGMII_RXC__RGMII_RXC | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_RD0__RGMII_RD0 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_RD1__RGMII_RD1 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_RD2__RGMII_RD2 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_RD3__RGMII_RD3 | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | > > MUX_PAD_CTRL(ENET_PAD_CTRL), > > + /*INT#_GBE*/ > > + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | > > MUX_PAD_CTRL(NO_PAD_CTRL), +}; > > + > > +static void setup_iomux_enet(void) > > +{ > > + SETUP_IOMUX_PADS(enet_pads); > > + gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ > > +} > > + > > +int board_eth_init(bd_t *bd) > > +{ > > + struct phy_device *phydev; > > + struct mii_dev *bus; > > + int ret; > > + > > + setup_iomux_enet(); > > + > > + iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); > > + > > + ret = enable_fec_anatop_clock(0, ENET_125MHZ); > > + if (ret) > > + return ret; > > + > > + bus = fec_get_miibus(IMX_FEC_BASE, -1); > > + if (!bus) > > + return -ENODEV; > > + > > + /* > > + * We use here the "rgmii-id" mode of operation and allow > > M88E1512 > > + * PHY to use its internally callibrated RX/TX delays > > + */ > > + phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, > > + PHY_INTERFACE_MODE_RGMII_ID); > > + if (!phydev) { > > + ret = -ENODEV; > > + goto err_phy; > > + } > > + > > + /* display5 due to PCB routing can only work with 100 Mbps > > */ > > + phydev->advertising &= ~(ADVERTISED_1000baseX_Half | > > + ADVERTISED_1000baseX_Full | > > + SUPPORTED_1000baseT_Half | > > + SUPPORTED_1000baseT_Full); > > + > > + ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); > > + if (ret) > > + goto err_sw; > > + > > + return 0; > > + > > +err_sw: > > + free(phydev); > > +err_phy: > > + mdio_unregister(bus); > > + free(bus); > > + return ret; > > +} > > +#endif /* CONFIG_FEC_MXC */ > > + > > +/* > > + * Do not overwrite the console > > + * Always use serial for U-Boot console > > + */ > > +int overwrite_console(void) > > +{ > > + return 1; > > +} > > + > > +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) > > +int ft_board_setup(void *blob, bd_t *bd) > > +{ > > + fdt_fixup_ethernet(blob); > > + return 0; > > +} > > +#endif > > + > > +int board_init(void) > > +{ > > + debug("board init\n"); > > + /* address of boot parameters */ > > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > > + > > + /* Setup iomux for non console UARTS */ > > + displ5_set_iomux_uart(); > > + > > + displ5_setup_ecspi(); > > + > > + SETUP_IOMUX_PADS(misc_pads); > > + > > + get_board_id(gpio_table_sw_ids, > > &gpio_table_sw_ids_names[0], > > + ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, > > &unit_id); > > + debug("SWx unit_id 0x%x\n", unit_id); > > + > > + get_board_id(gpio_table_hw_ids, > > &gpio_table_hw_ids_names[0], > > + ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, > > &cpu_id); > > + debug("HWx cpu_id 0x%x\n", cpu_id); > > + > > + if (hw_ids_valid && sw_ids_valid) > > + printf("ID: unit type 0x%x rev 0x%x\n", > > unit_id, cpu_id); + > > + udelay(25); > > + > > + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); > > + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); > > + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); > > + > > + return 0; > > +} > > + > > +#ifdef CONFIG_CMD_BMODE > > +static const struct boot_mode board_boot_modes[] = { > > + /* eMMC, USDHC-4, 8-bit bus width */ > > + /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */ > > + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, > > + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)}, > > + {NULL, 0}, > > +}; > > + > > +static void setup_boot_modes(void) > > +{ > > + add_board_boot_modes(board_boot_modes); > > +} > > +#else > > +static inline void setup_boot_modes(void) {} > > +#endif > > + > > +int misc_init_r(void) > > +{ > > + setup_boot_modes(); > > + return 0; > > +} > > + > > +static struct mxc_serial_platdata mxc_serial_plat = { > > + .reg = (struct mxc_uart *)UART5_BASE, > > +}; > > + > > +U_BOOT_DEVICE(mxc_serial) = { > > + .name = "serial_mxc", > > + .platdata = &mxc_serial_plat, > > +}; > > diff --git a/board/liebherr/display5/spl.c > > b/board/liebherr/display5/spl.c new file mode 100644 > > index 0000000000..0a36e656c0 > > --- /dev/null > > +++ b/board/liebherr/display5/spl.c > > @@ -0,0 +1,247 @@ > > +/* > > + * Copyright (C) 2017 DENX Software Engineering > > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <spl.h> > > +#include <libfdt.h> > > +#include <asm/io.h> > > +#include <asm/arch/clock.h> > > +#include <asm/arch/mx6-ddr.h> > > +#include <asm/arch/mx6-pins.h> > > +#include "asm/arch/crm_regs.h" > > +#include <asm/arch/sys_proto.h> > > +#include <asm/arch/imx-regs.h> > > +#include "asm/arch/iomux.h" > > +#include <asm/mach-imx/iomux-v3.h> > > +#include <environment.h> > > +#include <fsl_esdhc.h> > > +#include <netdev.h> > > +#include "common.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { > > + .dram_sdclk_0 = 0x00000030, > > + .dram_sdclk_1 = 0x00000030, > > + .dram_cas = 0x00000030, > > + .dram_ras = 0x00000030, > > + .dram_reset = 0x00000030, > > + .dram_sdcke0 = 0x00003000, > > + .dram_sdcke1 = 0x00003000, > > + .dram_sdba2 = 0x00000000, > > + .dram_sdodt0 = 0x00000030, > > + .dram_sdodt1 = 0x00000030, > > + > > + .dram_sdqs0 = 0x00000030, > > + .dram_sdqs1 = 0x00000030, > > + .dram_sdqs2 = 0x00000030, > > + .dram_sdqs3 = 0x00000030, > > + .dram_sdqs4 = 0x00000030, > > + .dram_sdqs5 = 0x00000030, > > + .dram_sdqs6 = 0x00000030, > > + .dram_sdqs7 = 0x00000030, > > + > > + .dram_dqm0 = 0x00000030, > > + .dram_dqm1 = 0x00000030, > > + .dram_dqm2 = 0x00000030, > > + .dram_dqm3 = 0x00000030, > > + .dram_dqm4 = 0x00000030, > > + .dram_dqm5 = 0x00000030, > > + .dram_dqm6 = 0x00000030, > > + .dram_dqm7 = 0x00000030, > > +}; > > + > > +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { > > + .grp_ddr_type = 0x000c0000, > > + .grp_ddrmode_ctl = 0x00020000, > > + .grp_ddrpke = 0x00000000, > > + .grp_addds = 0x00000030, > > + .grp_ctlds = 0x00000030, > > + .grp_ddrmode = 0x00020000, > > + .grp_b0ds = 0x00000030, > > + .grp_b1ds = 0x00000030, > > + .grp_b2ds = 0x00000030, > > + .grp_b3ds = 0x00000030, > > + .grp_b4ds = 0x00000030, > > + .grp_b5ds = 0x00000030, > > + .grp_b6ds = 0x00000030, > > + .grp_b7ds = 0x00000030, > > +}; > > + > > +/* 4x128Mx16.cfg */ > > +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib > > = { > > + .p0_mpwldectrl0 = 0x002D0028, > > + .p0_mpwldectrl1 = 0x0032002D, > > + .p1_mpwldectrl0 = 0x00210036, > > + .p1_mpwldectrl1 = 0x0019002E, > > + .p0_mpdgctrl0 = 0x4349035C, > > + .p0_mpdgctrl1 = 0x0348033D, > > + .p1_mpdgctrl0 = 0x43550362, > > + .p1_mpdgctrl1 = 0x03520316, > > + .p0_mprddlctl = 0x41393940, > > + .p1_mprddlctl = 0x3F3A3C47, > > + .p0_mpwrdlctl = 0x413A423A, > > + .p1_mpwrdlctl = 0x4042483E, > > +}; > > + > > +/* MT41K128M16JT-125 (2Gb density) */ > > +static const struct mx6_ddr3_cfg mt41k128m16jt_125 = { > > + .mem_speed = 1600, > > + .density = 2, > > + .width = 16, > > + .banks = 8, > > + .rowaddr = 14, > > + .coladdr = 10, > > + .pagesz = 2, > > + .trcd = 1375, > > + .trcmin = 4875, > > + .trasmin = 3500, > > +}; > > + > > +static void ccgr_init(void) > > +{ > > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg > > *)CCM_BASE_ADDR; + > > + writel(0x00C03F3F, &ccm->CCGR0); > > + writel(0x0030FC3F, &ccm->CCGR1); > > + writel(0x0FFFCFC0, &ccm->CCGR2); > > + writel(0x3FF00000, &ccm->CCGR3); > > + writel(0x00FFF300, &ccm->CCGR4); > > + writel(0x0F0000C3, &ccm->CCGR5); > > + writel(0x000003FF, &ccm->CCGR6); > > +} > > + > > +static void spl_dram_init(void) > > +{ > > + struct mx6_ddr_sysinfo sysinfo = { > > + /* width of data bus:0=16,1=32,2=64 */ > > + .dsize = 2, > > + /* config for full 4GB range so that > > get_mem_size() works */ > > + .cs_density = 32, /* 32Gb per CS */ > > + /* single chip select */ > > + .ncs = 1, > > + .cs1_mirror = 0, > > + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr > > = RZQ/4 */ > > + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* > > RTT_Nom = RZQ/2 */ > > + .walat = 1, /* Write additional latency */ > > + .ralat = 5, /* Read additional latency */ > > + .mif3_mode = 3, /* Command prediction > > working mode */ > > + .bi_on = 1, /* Bank interleaving enabled */ > > + .sde_to_rst = 0x10, /* 14 cycles, 200us > > (JEDEC default) */ > > + .rst_to_cke = 0x23, /* 33 cycles, 500us > > (JEDEC default) */ > > + .pd_fast_exit = 1, /* enable precharge power-down > > fast exit */ > > + .ddr_type = DDR_TYPE_DDR3, > > + .refsel = 1, /* Refresh cycles at 32KHz */ > > + .refr = 7, /* 8 refresh commands per > > refresh cycle */ > > + }; > > + > > + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); > > + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, > > &mt41k128m16jt_125); +} > > + > > +#ifdef CONFIG_SPL_SPI_SUPPORT > > +static void displ5_init_ecspi(void) > > +{ > > + displ5_set_iomux_ecspi_spl(); > > + enable_spi_clk(1, 1); > > +} > > +#else > > +static inline void displ5_init_ecspi(void) { } > > +#endif > > + > > +#ifdef CONFIG_SPL_MMC_SUPPORT > > +static struct fsl_esdhc_cfg usdhc_cfg = { > > + .esdhc_base = USDHC4_BASE_ADDR, > > + .max_bus_width = 8, > > +}; > > + > > +int board_mmc_init(bd_t *bd) > > +{ > > + displ5_set_iomux_usdhc_spl(); > > + > > + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); > > + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; > > + > > + return fsl_esdhc_initialize(bd, &usdhc_cfg); > > +} > > +#endif > > + > > +void board_init_f(ulong dummy) > > +{ > > + ccgr_init(); > > + > > + arch_cpu_init(); > > + > > + gpr_init(); > > + > > + /* setup GP timer */ > > + timer_init(); > > + > > + displ5_set_iomux_uart_spl(); > > + > > + /* UART clocks enabled and gd valid - init serial console > > */ > > + preloader_console_init(); > > + > > + displ5_init_ecspi(); > > + > > + /* DDR initialization */ > > + spl_dram_init(); > > + > > + /* Clear the BSS. */ > > + memset(__bss_start, 0, __bss_end - __bss_start); > > + > > + /* load/boot image from boot device */ > > + board_init_r(NULL, 0); > > +} > > + > > +void board_boot_order(u32 *spl_boot_list) > > +{ > > + /* Default boot sequence SPI -> MMC */ > > + spl_boot_list[0] = spl_boot_device(); > > + spl_boot_list[1] = BOOT_DEVICE_MMC1; > > + spl_boot_list[2] = BOOT_DEVICE_UART; > > + spl_boot_list[3] = BOOT_DEVICE_NONE; > > + > > +#ifdef CONFIG_SPL_ENV_SUPPORT > > + /* 'fastboot' */ > > + const char *s; > > + > > + env_init(); > > + env_load(); > > + > > + s = env_get("BOOT_FROM"); > > + if (s && strcmp(s, "ACTIVE") == 0) { > > + spl_boot_list[0] = BOOT_DEVICE_MMC1; > > + spl_boot_list[1] = spl_boot_device(); > > + } > > +#endif > > +} > > + > > +void reset_cpu(ulong addr) {} > > + > > +#ifdef CONFIG_SPL_LOAD_FIT > > +int board_fit_config_name_match(const char *name) > > +{ > > + return 0; > > +} > > +#endif > > + > > +#ifdef CONFIG_SPL_OS_BOOT > > +/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */ > > +int spl_start_uboot(void) > > +{ > > + /* break into full u-boot on 'c' */ > > + if (serial_tstc() && serial_getc() == 'c') > > + return 1; > > + > > +#ifdef CONFIG_SPL_ENV_SUPPORT > > + if (env_get_yesno("boot_os") != 1) > > + return 1; > > +#endif > > + return 0; > > +} > > +#endif > > diff --git a/configs/display5_defconfig b/configs/display5_defconfig > > new file mode 100644 > > index 0000000000..dfd9c2c298 > > --- /dev/null > > +++ b/configs/display5_defconfig > > @@ -0,0 +1,62 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_MX6=y > > +CONFIG_SPL_GPIO_SUPPORT=y > > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > > +CONFIG_TARGET_DISPLAY5=y > > +CONFIG_SPL_MMC_SUPPORT=y > > +CONFIG_SPL_SERIAL_SUPPORT=y > > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > > +CONFIG_SPL_SPI_SUPPORT=y > > +CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" > > +CONFIG_FIT=y > > +CONFIG_SPL_LOAD_FIT=y > > +CONFIG_OF_BOARD_SETUP=y > > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" > > +CONFIG_SPL=y > > +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set > > +CONFIG_SPL_DMA_SUPPORT=y > > +CONFIG_SPL_ENV_SUPPORT=y > > +CONFIG_SPL_SAVEENV=y > > +CONFIG_SPL_I2C_SUPPORT=y > > +CONFIG_SPL_OS_BOOT=y > > +CONFIG_HUSH_PARSER=y > > +CONFIG_SYS_PROMPT="display5 > " > > +CONFIG_CMD_BOOTZ=y > > +# CONFIG_CMD_ELF is not set > > +CONFIG_CMD_ASKENV=y > > +CONFIG_CRC32_VERIFY=y > > +CONFIG_CMD_EEPROM=y > > +# CONFIG_CMD_FPGA is not set > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_PART=y > > +CONFIG_CMD_SF=y > > +CONFIG_CMD_SPI=y > > +CONFIG_CMD_DHCP=y > > +CONFIG_CMD_MII=y > > +CONFIG_CMD_PING=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_CMD_TIME=y > > +CONFIG_CMD_EXT2=y > > +CONFIG_CMD_EXT4=y > > +CONFIG_CMD_FAT=y > > +CONFIG_CMD_FS_GENERIC=y > > +CONFIG_CMD_MTDPARTS=y > > +CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" > > +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" > > +CONFIG_EFI_PARTITION=y > > +# CONFIG_SPL_EFI_PARTITION is not set > > +CONFIG_OF_CONTROL=y > > +CONFIG_ENV_IS_IN_SPI_FLASH=y > > +CONFIG_SPI_FLASH=y > > +CONFIG_SPI_FLASH_BAR=y > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_PHYLIB=y > > +CONFIG_PHY_MARVELL=y > > +CONFIG_NETDEVICES=y > > +CONFIG_FEC_MXC=y > > +# CONFIG_SPL_DM_SERIAL is not set > > +CONFIG_MXC_UART=y > > diff --git a/configs/display5_factory_defconfig > > b/configs/display5_factory_defconfig new file mode 100644 > > index 0000000000..3f10ffad03 > > --- /dev/null > > +++ b/configs/display5_factory_defconfig > > @@ -0,0 +1,76 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_MX6=y > > +CONFIG_SPL_GPIO_SUPPORT=y > > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > > +CONFIG_TARGET_DISPLAY5=y > > +CONFIG_SPL_SERIAL_SUPPORT=y > > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > > +CONFIG_SPL_SPI_SUPPORT=y > > +CONFIG_FIT=y > > +CONFIG_OF_BOARD_SETUP=y > > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" > > +CONFIG_BOOTDELAY=3 > > +CONFIG_SPL=y > > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set > > +CONFIG_SPL_DMA_SUPPORT=y > > +CONFIG_SPL_I2C_SUPPORT=y > > +CONFIG_SPL_OS_BOOT=y > > +CONFIG_SPL_USB_HOST_SUPPORT=y > > +CONFIG_SPL_USB_GADGET_SUPPORT=y > > +CONFIG_SPL_USB_SDP_SUPPORT=y > > +CONFIG_HUSH_PARSER=y > > +CONFIG_SYS_PROMPT="display5 factory > " > > +CONFIG_BOOTCMD_OVERRIDE=y > > +CONFIG_BOOTCOMMAND="run factory" > > +CONFIG_CMD_BOOTZ=y > > +# CONFIG_CMD_ELF is not set > > +CONFIG_CMD_ASKENV=y > > +CONFIG_CRC32_VERIFY=y > > +CONFIG_CMD_EEPROM=y > > +CONFIG_CMD_DFU=y > > +# CONFIG_CMD_FPGA is not set > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_GPT=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_PART=y > > +CONFIG_CMD_SF=y > > +CONFIG_CMD_SPI=y > > +CONFIG_CMD_USB_SDP=y > > +CONFIG_CMD_DHCP=y > > +CONFIG_CMD_MII=y > > +CONFIG_CMD_PING=y > > +CONFIG_CMD_CACHE=y > > +CONFIG_CMD_TIME=y > > +CONFIG_CMD_EXT2=y > > +CONFIG_CMD_EXT4=y > > +CONFIG_CMD_EXT4_WRITE=y > > +CONFIG_CMD_FAT=y > > +CONFIG_CMD_FS_GENERIC=y > > +CONFIG_CMD_MTDPARTS=y > > +CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" > > +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" > > +# CONFIG_SPL_EFI_PARTITION is not set > > +CONFIG_PARTITION_TYPE_GUID=y > > +CONFIG_ENV_IS_IN_SPI_FLASH=y > > +CONFIG_DFU_MMC=y > > +CONFIG_DFU_SF=y > > +CONFIG_SPI_FLASH=y > > +CONFIG_SPI_FLASH_BAR=y > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_PHYLIB=y > > +CONFIG_NETDEVICES=y > > +CONFIG_FEC_MXC=y > > +# CONFIG_SPL_DM_SERIAL is not set > > +CONFIG_MXC_UART=y > > +CONFIG_USB=y > > +CONFIG_USB_GADGET=y > > +CONFIG_USB_GADGET_MANUFACTURER="Liebherr" > > +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 > > +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 > > +CONFIG_CI_UDC=y > > +CONFIG_USB_GADGET_DOWNLOAD=y > > +CONFIG_OF_LIBFDT=y > > diff --git a/include/configs/display5.h b/include/configs/display5.h > > new file mode 100644 > > index 0000000000..c41ab8b5e2 > > --- /dev/null > > +++ b/include/configs/display5.h > > @@ -0,0 +1,408 @@ > > +/* > > + * Copyright (C) 2017 > > + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#ifndef __CONFIG_H > > +#define __CONFIG_H > > + > > +#include "mx6_common.h" > > + > > +/* Falcon Mode */ > > +#define CONFIG_CMD_SPL > > +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 > > +#define CONFIG_CMD_SPL_WRITE_SIZE (44 * SZ_1K) > > + > > +/* Falcon Mode - MMC support */ > > +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 > > +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ > > + (CONFIG_CMD_SPL_WRITE_SIZE / 512) > > +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR > > 0x100 /* 128KiB */ + > > +/* > > + * display5 SPI-NOR memory layout > > + * > > + * The definition can be found in Kconfig's > > + * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT > > + * > > + * 0x000000 - 0x020000 : SPI.SPL (128KiB) > > + * 0x020000 - 0x120000 : SPI.u-boot (1MiB) > > + * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB) > > + * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB) > > + * 0x140000 - 0x940000 : SPI.fitImage-recovery (8MiB) > > + * 0x940000 - 0xD40000 : SPI.swupdate-kernel-FIT (4MiB) > > + * 0xD40000 - 0x1540000 : SPI.swupdate-initramfs (8MiB) > > + */ > > + > > +#ifndef CONFIG_SPL_BUILD > > +#define CONFIG_MTD_DEVICE > > +#define CONFIG_SPI_FLASH_MTD > > +#define CONFIG_MTD_PARTITIONS > > +#endif > > + > > +/* Below values are "dummy" - only to avoid build break */ > > +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 > > +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 > > +#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 > > + > > +#include "imx6_spl.h" > > +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 > > +#define CONFIG_SPL_SPI_LOAD > > + > > +#define CONFIG_CMDLINE_TAG > > +#define CONFIG_SETUP_MEMORY_TAGS > > +#define CONFIG_INITRD_TAG > > +#define CONFIG_REVISION_TAG > > + > > +/* Size of malloc() pool */ > > +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) > > +#define CONFIG_MISC_INIT_R > > + > > +/*#define CONFIG_MXC_UART*/ > > +#define CONFIG_MXC_UART_BASE UART5_BASE > > + > > +/* SPI NOR Flash */ > > +#ifdef CONFIG_CMD_SF > > +#define CONFIG_MXC_SPI > > +#define CONFIG_SF_DEFAULT_BUS 1 > > +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(5, > > 29) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 50000000 > > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 > > +#endif > > + > > +/* I2C Configs */ > > +#define CONFIG_SYS_I2C > > +#define CONFIG_SYS_I2C_MXC > > +#define CONFIG_SYS_I2C_MXC_I2C1 > > +#define CONFIG_SYS_I2C_MXC_I2C2 > > +#define CONFIG_SYS_I2C_MXC_I2C3 > > +#define CONFIG_I2C_MULTI_BUS > > +#define CONFIG_SYS_I2C_SPEED 100000 > > +#define CONFIG_I2C_EDID > > +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 > > + > > +/* Ethernet */ > > +#ifdef CONFIG_FEC_MXC > > +#define IMX_FEC_BASE ENET_BASE_ADDR > > +#define CONFIG_FEC_XCV_TYPE RGMII > > +#define CONFIG_ETHPRIME "FEC" > > +#define CONFIG_FEC_MXC_PHYADDR 0 > > +#define CONFIG_MII > > +#endif > > + > > +/* MMC Configs */ > > +#define CONFIG_FSL_ESDHC > > +#define CONFIG_FSL_USDHC > > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > > +#define CONFIG_SUPPORT_EMMC_BOOT > > + > > +/* allow to overwrite serial and ethaddr */ > > +#define CONFIG_ENV_OVERWRITE > > +#define CONFIG_BAUDRATE 115200 > > + > > +#ifndef CONFIG_BOOTCOMMAND > > +#define CONFIG_BOOTCOMMAND "run boot_mmc" > > +#endif > > + > > +#define PARTS_DEFAULT \ > > + /* Linux partitions */ \ > > + "partitions=" \ > > + "uuid_disk=${uuid_gpt_disk};" \ > > + "name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" > > \ > > + "name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \ > > + "name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \ > > + "name=rootfs2,size=1528M,uuid=${uuid_gpt_rootfs2};" \ > > + "name=data,size=-,uuid=${uuid_gpt_data}\0" > > + > > +#define FACTORY_PROCEDURE \ > > + "echo '#######################';" \ > > + "echo '# Factory Boot #';" \ > > + "echo '#######################';" \ > > + "env default -a;" \ > > + "saveenv;" \ > > + "gpt write mmc ${mmcdev} ${partitions};" \ > > + "run tftp_sf_SPL;" \ > > + "run tftp_sf_uboot;" \ > > + TFTP_UPDATE_KERNEL \ > > + "run tftp_sf_fitImg_recovery;" \ > > + "run tftp_sf_fitImg_SWU;" \ > > + "run tftp_sf_initramfs_SWU;" \ > > + TFTP_UPDATE_ROOTFS \ > > + "echo '#######################';" \ > > + "echo '# END - OK #';" \ > > + "echo '#######################';" \ > > + "setenv bootcmd 'env default -a; saveenv; run > > falcon_setup; reset';" \ > > + "setenv boot_os 'n';" \ > > + "saveenv;" \ > > + "reset;" > > + > > +#define SWUPDATE_RECOVERY_PROCEDURE \ > > + "echo '#######################';" \ > > + "echo '# RECOVERY SWUupdate #';" \ > > + "echo '#######################';" \ > > + "setenv loadaddr_swu_initramfs 0x14000000;" \ > > + "setenv bootargs console=${console} " \ > > + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" > > \ > > + ":${hostname}::off root=/dev/ram rw;" \ > > + "sf probe;" \ > > + "sf read ${loadaddr} swu-kernel;" \ > > + "sf read ${loadaddr_swu_initramfs} swu-initramfs;" \ > > + "bootm ${loadaddr} ${loadaddr_swu_initramfs};" > > + > > +#define KERNEL_RECOVERY_PROCEDURE \ > > + "echo '#######################';" \ > > + "echo '# RECOVERY KERNEL IMG #';" \ > > + "echo '#######################';" \ > > + "sf probe;" \ > > + "sf read ${loadaddr} lin-recovery;" \ > > + "bootm;" > > + > > +#define SETUP_BOOTARGS \ > > + "run set_rootfs_part;" \ > > + "setenv bootargs ${bootargs} console=${console} " > > \ > > + "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \ > > + "rootwait rootfstype=ext4 rw; " \ > > + "run set_kernel_part;" \ > > + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ > > + "mmc read ${loadaddr} ${lba_start} 0x2000; " \ > > + "setenv fdt_conf imx6q-${board}-${display}.dtb; " > > + > > +/* All the numbers are in LBAs */ > > +#define __TFTP_UPDATE_KERNEL \ > > + "tftp_mmc_fitImg=" \ > > + "if test ! -n ${kernel_part}; then " \ > > + "setenv kernel_part ${kernel_part_active};" \ > > + "fi;" \ > > + "if tftp ${loadaddr} ${kernel_file}; then " \ > > + "setexpr fw_sz ${filesize} / 0x200; " \ > > + "setexpr fw_sz ${fw_sz} + 1; " \ > > + "part start mmc ${mmcdev} ${kernel_part} lba_start; > > " \ > > + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ > > + "; fi\0" \ > > + > > +#define TFTP_UPDATE_KERNEL \ > > + "setenv kernel_part ${kernel_part_active};" \ > > + "run tftp_mmc_fitImg;" \ > > + "setenv kernel_part ${kernel_part_backup};" \ > > + "run tftp_mmc_fitImg;" \ > > + > > +#define __TFTP_UPDATE_ROOTFS \ > > + "tftp_mmc_rootfs=" \ > > + "if test ! -n ${rootfs_part}; then " \ > > + "setenv rootfs_part ${rootfs_part_active};" \ > > + "fi;" \ > > + "if tftp ${loadaddr} ${rootfs_file}; then " \ > > + "setexpr fw_sz ${filesize} / 0x200; " \ > > + "setexpr fw_sz ${fw_sz} + 1; " \ > > + "part start mmc ${mmcdev} ${rootfs_part} lba_start; > > " \ > > + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ > > + "; fi\0" \ > > + > > +/* To save some considerable time, we only once download the > > rootfs image */ +/* and store it on 'active' and 'backup' rootfs > > partitions */ +#define TFTP_UPDATE_ROOTFS \ > > + "setenv rootfs_part ${rootfs_part_active};" \ > > + "run tftp_mmc_rootfs;" \ > > + "part start mmc ${mmcdev} ${rootfs_part_backup} > > lba_start;" \ > > + "mmc write ${loadaddr} ${lba_start} ${fw_sz};" \ > > + > > +#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \ > > + "tftp_sf_fitImg_SWU=" \ > > + "if tftp ${loadaddr} ${kernel_file}; then " \ > > + "sf probe;" \ > > + "sf erase swu-kernel +${filesize};" \ > > + "sf write ${loadaddr} swu-kernel ${filesize};" \ > > + "; fi\0" \ > > + > > +#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ > > + "swu_initramfs_file=swupdate-image-display5.ext3.gz.u-boot\0" > > \ > > + "tftp_sf_initramfs_SWU=" \ > > + "if tftp ${loadaddr} ${swu_initramfs_file}; then " \ > > + "sf probe;" \ > > + "sf erase swu-initramfs +${filesize};" \ > > + "sf write ${loadaddr} swu-initramfs ${filesize};" \ > > + "; fi\0" \ > > + > > +#define TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ > > + "kernel_recovery_file=fitImage-initramfs\0" \ > > + "tftp_sf_fitImg_recovery=" \ > > + "if tftp ${loadaddr} ${kernel_recovery_file}; then " \ > > + "sf probe;" \ > > + "sf erase lin-recovery +${filesize};" \ > > + "sf write ${loadaddr} lin-recovery ${filesize};" \ > > + "; fi\0" \ > > + > > +#define TFTP_UPDATE_BOOTLOADER \ > > + "ubootfile=u-boot.img\0" \ > > + "ubootfileSPL=SPL\0" \ > > + "tftp_sf_uboot=" \ > > + "if tftp ${loadaddr} ${ubootfile}; then " \ > > + "sf probe;" \ > > + "sf erase u-boot +${filesize};" \ > > + "sf write ${loadaddr} u-boot ${filesize}" \ > > + "; fi\0" \ > > + "tftp_sf_SPL=" \ > > + "if tftp ${loadaddr} ${ubootfileSPL}; then " \ > > + "sf probe;" \ > > + "setexpr uboot_SPL_size ${filesize} + 0x400;" \ > > + "sf erase 0x0 +${uboot_SPL_size};" \ > > + "sf write ${loadaddr} 0x400 ${filesize};" \ > > + "fi\0" \ > > + > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + PARTS_DEFAULT \ > > + "display=tianma-tm070-800x480\0" \ > > + "board=display5\0" \ > > + "mmcdev=0\0" \ > > + "altbootcmd=run recovery\0" \ > > + "bootdelay=1\0" \ > > + "baudrate=115200\0" \ > > + "bootcmd=" CONFIG_BOOTCOMMAND "\0" \ > > + "factory=" FACTORY_PROCEDURE "\0" \ > > + "bootlimit=3\0" \ > > + "ethact=FEC\0" \ > > + "netdev=eth0\0" \ > > + "boot_os=y\0" \ > > + "hostname=display5\0" \ > > + "loadaddr=0x12000000\0" \ > > + "fdtaddr=0x12800000\0" \ > > + "console=ttymxc4,115200 quiet\0" \ > > + "fdtfile=imx6q-display5.dtb\0" \ > > + "fdt_high=0xffffffff\0" \ > > + "initrd_high=0xffffffff\0" \ > > + "kernel_file=fitImage\0" \ > > + "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ > > + "download_kernel=" \ > > + "tftpboot ${loadaddr} ${kernel_file};\0" \ > > + "boot_kernel_recovery=" KERNEL_RECOVERY_PROCEDURE "\0" \ > > + "boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \ > > + "recovery=" \ > > + "if test ${BOOT_FROM_RECOVERY} = SWU; then " \ > > + "echo BOOT: RECOVERY: SWU;" \ > > + "run boot_swu_recovery;" \ > > + "else " \ > > + "echo BOOT: RECOVERY: Linux;" \ > > + "run boot_kernel_recovery;" \ > > + "fi\0" \ > > + "boot_tftp=" \ > > + "if run download_kernel; then " \ > > + "setenv bootargs console=${console} " \ > > + "root=/dev/mmcblk0p2 rootwait;" \ > > + "bootm ${loadaddr} - ${fdtaddr};" \ > > + "fi\0" \ > > + "addip=setenv bootargs ${bootargs} " \ > > + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ > > + "${hostname}:eth0:on" \ > > + "\0" \ > > + "nfsargs=setenv bootargs " \ > > + "root=/dev/nfs rw " \ > > + "nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \ > > + "\0" \ > > + "rootpath=/srv/tftp/DISP5/rootfs\0" \ > > + "boot_nfs=" \ > > + "if run download_kernel; then " \ > > + "run nfsargs;" \ > > + "run addip;" \ > > + "setenv bootargs ${bootargs} > > console=${console};" \ > > + "setenv fdt_conf imx6q-${board}-${display}.dtb; " \ > > + "bootm ${loadaddr}#conf@${fdt_conf};" \ > > + "fi\0" \ > > + "falcon_setup=" \ > > + "if mmc dev ${mmcdev}; then " \ > > + SETUP_BOOTARGS \ > > + "spl export fdt ${loadaddr}#conf@${fdt_conf};" \ > > + "setexpr fw_sz ${fdtargslen} / 0x200; " \ > > + "setexpr fw_sz ${fw_sz} + 1; " \ > > + "mmc write ${fdtargsaddr} " \ > > + __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" > > ${fw_sz}; " \ > > + "fi\0" \ > > + "boot_mmc=" \ > > + "if mmc dev ${mmcdev}; then " \ > > + SETUP_BOOTARGS \ > > + "bootm ${loadaddr}#conf@${fdt_conf};" \ > > + "fi\0" \ > > + "set_kernel_part=" \ > > + "if test ${BOOT_FROM} = ACTIVE; then " \ > > + "setenv kernel_part ${kernel_part_active};" \ > > + "echo BOOT: ACTIVE;" \ > > + "else if test ${BOOT_FROM} = BACKUP; then " \ > > + "setenv kernel_part ${kernel_part_backup};" \ > > + "echo BOOT: BACKUP;" \ > > + "else " \ > > + "run recovery;" \ > > + "fi;fi\0" \ > > + "set_rootfs_part=" \ > > + "if test ${BOOT_FROM} = ACTIVE; then " \ > > + "setenv rootfs_part ${rootfs_part_active};" \ > > + "else if test ${BOOT_FROM} = BACKUP; then " \ > > + "setenv rootfs_part ${rootfs_part_backup};" \ > > + "else " \ > > + "run recovery;" \ > > + "fi;fi\0" \ > > + "BOOT_FROM=ACTIVE\0" \ > > + "BOOT_FROM_RECOVERY=Linux\0" \ > > + TFTP_UPDATE_BOOTLOADER \ > > + "kernel_part_active=1\0" \ > > + "kernel_part_backup=3\0" \ > > + __TFTP_UPDATE_KERNEL \ > > + "rootfs_part_active=2\0" \ > > + "rootfs_part_backup=4\0" \ > > + "rootfs_file=core-image-lwn-display5.ext4\0" \ > > + __TFTP_UPDATE_ROOTFS \ > > + TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ > > + TFTP_UPDATE_RECOVERY_SWU_KERNEL \ > > + TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ > > + "\0" \ > > + > > +/* Miscellaneous configurable options */ > > +#undef CONFIG_SYS_CBSIZE > > +#define CONFIG_SYS_CBSIZE 2048 > > + > > +/* Print Buffer Size */ > > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > > + sizeof(CONFIG_SYS_PROMPT) > > + 16) +#define CONFIG_SYS_MAXARGS 32 > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > > + > > +#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 > > +#define CONFIG_SYS_HZ 1000 > > + > > +/* Physical Memory Map */ > > +#define CONFIG_NR_DRAM_BANKS 1 > > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > > + > > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > > + > > +#define CONFIG_SYS_INIT_SP_OFFSET \ > > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > > +#define CONFIG_SYS_INIT_SP_ADDR \ > > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > > + > > +/* Commands */ > > +#define CONFIG_MTD_PARTITIONS > > +#define CONFIG_MTD_DEVICE > > + > > +/* ENV config */ > > +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH > > +#define CONFIG_ENV_SIZE (SZ_64K) > > +/* The 0x120000 value corresponds to above SPI-NOR memory MAP */ > > +#define CONFIG_ENV_OFFSET (0x120000) > > +#define CONFIG_ENV_SECT_SIZE (SZ_64K) > > +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT > > +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ > > + > > CONFIG_ENV_SECT_SIZE) +#define > > CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + > > +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS > > +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS > > +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE > > +#define CONFIG_ENV_SPI_MAX_HZ > > CONFIG_SF_DEFAULT_SPEED +#endif > > + > > +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | > > PORT_PTS_PTW) +#endif /* __CONFIG_H */ > > > > Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
diff --git a/arch/arm/dts/imx6q-display5.dts b/arch/arm/dts/imx6q-display5.dts new file mode 100644 index 0000000000..50347ff26b --- /dev/null +++ b/arch/arm/dts/imx6q-display5.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "imx6q.dtsi" + +/ { + model = "Liebherr (LWN) display5 i.MX6 Quad Board"; + compatible = "lwn,display5", "fsl,imx6q"; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index b82db3af22..fd73c67fde 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -138,6 +138,12 @@ config TARGET_DHCOMIMX6 select DM_THERMAL imply CMD_SPL +config TARGET_DISPLAY5 + bool "LWN DISPLAY5 board" + select SUPPORT_SPL + select DM + select DM_SERIAL + config TARGET_EMBESTMX6BOARDS bool "embestmx6boards" select BOARD_LATE_INIT @@ -459,6 +465,7 @@ source "board/phytec/pfla02/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" +source "board/liebherr/display5/Kconfig" source "board/liebherr/mccmon6/Kconfig" source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" diff --git a/board/liebherr/display5/Kconfig b/board/liebherr/display5/Kconfig new file mode 100644 index 0000000000..b096c8917a --- /dev/null +++ b/board/liebherr/display5/Kconfig @@ -0,0 +1,18 @@ +if TARGET_DISPLAY5 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "display5" + +config SYS_VENDOR + default "liebherr" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "display5" + +endif diff --git a/board/liebherr/display5/MAINTAINERS b/board/liebherr/display5/MAINTAINERS new file mode 100644 index 0000000000..52178318b5 --- /dev/null +++ b/board/liebherr/display5/MAINTAINERS @@ -0,0 +1,7 @@ +DISPLAY5 BOARD +M: Lukasz Majewski <lukma@denx.de> +S: Maintained +F: board/liebherr/display5/ +F: include/configs/display5.h +F: configs/display5_defconfig +F: configs/display5_factory_defconfig diff --git a/board/liebherr/display5/Makefile b/board/liebherr/display5/Makefile new file mode 100644 index 0000000000..f934672428 --- /dev/null +++ b/board/liebherr/display5/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2017, DENX Software Engineering +# Lukasz Majewski <lukma@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# +ifdef CONFIG_SPL_BUILD +obj-y = common.o spl.o +else +obj-y := common.o display5.o +endif diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c new file mode 100644 index 0000000000..03f585b3aa --- /dev/null +++ b/board/liebherr/display5/common.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2017 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch/mx6-pins.h> +#include "common.h" + +iomux_v3_cfg_t const uart_pads[] = { + /* UART4 */ + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart_console_pads[] = { + /* UART5 */ + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void displ5_set_iomux_uart_spl(void) +{ + SETUP_IOMUX_PADS(uart_console_pads); +} + +void displ5_set_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart_pads); +} + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi_pads[] = { + /* SPI3 */ + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + /* SPI2, NOR Flash nWP, CS0 */ + MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8)) + return -EINVAL; + + return IMX_GPIO_NR(5, 29); +} + +void displ5_set_iomux_ecspi_spl(void) +{ + SETUP_IOMUX_PADS(ecspi2_pads); +} + +void displ5_set_iomux_ecspi(void) +{ + SETUP_IOMUX_PADS(ecspi_pads); +} + +#else +void displ5_set_iomux_ecspi_spl(void) {} +void displ5_set_iomux_ecspi(void) {} +#endif + +#ifdef CONFIG_FSL_ESDHC +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +void displ5_set_iomux_usdhc_spl(void) +{ + SETUP_IOMUX_PADS(usdhc4_pads); +} + +void displ5_set_iomux_usdhc(void) +{ + SETUP_IOMUX_PADS(usdhc4_pads); +} + +#else +void displ5_set_iomux_usdhc_spl(void) {} +void displ5_set_iomux_usdhc(void) {} +#endif diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h new file mode 100644 index 0000000000..6019e90c61 --- /dev/null +++ b/board/liebherr/display5/common.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2017 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DISPL5_COMMON_H_ +#define __DISPL5_COMMON_H_ + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +void displ5_set_iomux_uart_spl(void); +void displ5_set_iomux_uart(void); +void displ5_set_iomux_ecspi_spl(void); +void displ5_set_iomux_ecspi(void); +void displ5_set_iomux_usdhc_spl(void); +void displ5_set_iomux_usdhc(void); + +#endif /* __DISPL5_COMMON_H_ */ diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c new file mode 100644 index 0000000000..5414ef77d3 --- /dev/null +++ b/board/liebherr/display5/display5.c @@ -0,0 +1,384 @@ +/* + * Copyright (C) 2017 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/sys_proto.h> +#include <errno.h> +#include <asm/gpio.h> +#include <malloc.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/spi.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <i2c.h> + +#include <dm.h> +#include <dm/platform_data/serial_mxc.h> +#include <dm/platdata.h> + +#ifndef CONFIG_MXC_SPI +#error "CONFIG_SPI must be set for this board" +#error "Please check your config file" +#endif + +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static bool hw_ids_valid; +static bool sw_ids_valid; +static u32 cpu_id; +static u32 unit_id; + +#define SW0 IMX_GPIO_NR(2, 4) +#define SW1 IMX_GPIO_NR(2, 5) +#define SW2 IMX_GPIO_NR(2, 6) +#define SW3 IMX_GPIO_NR(2, 7) +#define HW0 IMX_GPIO_NR(6, 7) +#define HW1 IMX_GPIO_NR(6, 9) +#define HW2 IMX_GPIO_NR(6, 10) +#define HW3 IMX_GPIO_NR(6, 11) +#define HW4 IMX_GPIO_NR(4, 7) +#define HW5 IMX_GPIO_NR(4, 11) +#define HW6 IMX_GPIO_NR(4, 13) +#define HW7 IMX_GPIO_NR(4, 15) + +int gpio_table_sw_ids[] = { + SW0, SW1, SW2, SW3 +}; + +const char *gpio_table_sw_ids_names[] = { + "sw0", "sw1", "sw2", "sw3" +}; + +int gpio_table_hw_ids[] = { + HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7 +}; + +const char *gpio_table_hw_ids_names[] = { + "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7" +}; + +static int get_board_id(int *ids, const char **c, int size, + bool *valid, u32 *id) +{ + int i, ret, val; + + *valid = false; + + for (i = 0; i < size; i++) { + ret = gpio_request(ids[i], c[i]); + if (ret) { + printf("Can't request SWx gpios\n"); + return ret; + } + } + + for (i = 0; i < size; i++) { + ret = gpio_direction_input(ids[i]); + if (ret) { + printf("Can't set SWx gpios direction\n"); + return ret; + } + } + + for (i = 0; i < size; i++) { + val = gpio_get_value(ids[i]); + if (val < 0) { + printf("Can't get SW%d ID\n", i); + *id = 0; + return val; + } + *id |= val << i; + } + *valid = true; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1: TFA9879 */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2: TIVO TM4C123 */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* I2C3: PMIC PF0100, EEPROM AT24C256C */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +iomux_v3_cfg_t const misc_pads[] = { + /* Prod ID GPIO pins */ + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* HW revision GPIO pins */ + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* XTALOSC */ + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC4_BASE_ADDR, 0, 8, }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + displ5_set_iomux_usdhc(); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif /* CONFIG_FSL_ESDHC */ + +static void displ5_setup_ecspi(void) +{ + int ret; + + displ5_set_iomux_ecspi(); + + ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0"); + if (!ret) + gpio_direction_output(IMX_GPIO_NR(5, 29), 1); + + ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp"); + if (!ret) + gpio_direction_output(IMX_GPIO_NR(7, 0), 1); +} + +#ifdef CONFIG_FEC_MXC +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* for old evalboard with R159 present and R160 not populated */ + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /*INT#_GBE*/ + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/ +} + +int board_eth_init(bd_t *bd) +{ + struct phy_device *phydev; + struct mii_dev *bus; + int ret; + + setup_iomux_enet(); + + iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + + bus = fec_get_miibus(IMX_FEC_BASE, -1); + if (!bus) + return -ENODEV; + + /* + * We use here the "rgmii-id" mode of operation and allow M88E1512 + * PHY to use its internally callibrated RX/TX delays + */ + phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */, + PHY_INTERFACE_MODE_RGMII_ID); + if (!phydev) { + ret = -ENODEV; + goto err_phy; + } + + /* display5 due to PCB routing can only work with 100 Mbps */ + phydev->advertising &= ~(ADVERTISED_1000baseX_Half | + ADVERTISED_1000baseX_Full | + SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + + ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev); + if (ret) + goto err_sw; + + return 0; + +err_sw: + free(phydev); +err_phy: + mdio_unregister(bus); + free(bus); + return ret; +} +#endif /* CONFIG_FEC_MXC */ + +/* + * Do not overwrite the console + * Always use serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_ethernet(blob); + return 0; +} +#endif + +int board_init(void) +{ + debug("board init\n"); + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Setup iomux for non console UARTS */ + displ5_set_iomux_uart(); + + displ5_setup_ecspi(); + + SETUP_IOMUX_PADS(misc_pads); + + get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0], + ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id); + debug("SWx unit_id 0x%x\n", unit_id); + + get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0], + ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id); + debug("HWx cpu_id 0x%x\n", cpu_id); + + if (hw_ids_valid && sw_ids_valid) + printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id); + + udelay(25); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* eMMC, USDHC-4, 8-bit bus width */ + /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */ + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)}, + {NULL, 0}, +}; + +static void setup_boot_modes(void) +{ + add_board_boot_modes(board_boot_modes); +} +#else +static inline void setup_boot_modes(void) {} +#endif + +int misc_init_r(void) +{ + setup_boot_modes(); + return 0; +} + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART5_BASE, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c new file mode 100644 index 0000000000..0a36e656c0 --- /dev/null +++ b/board/liebherr/display5/spl.c @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2017 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <libfdt.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include "asm/arch/crm_regs.h" +#include <asm/arch/sys_proto.h> +#include <asm/arch/imx-regs.h> +#include "asm/arch/iomux.h" +#include <asm/mach-imx/iomux-v3.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <netdev.h> +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, +}; + +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* 4x128Mx16.cfg */ +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { + .p0_mpwldectrl0 = 0x002D0028, + .p0_mpwldectrl1 = 0x0032002D, + .p1_mpwldectrl0 = 0x00210036, + .p1_mpwldectrl1 = 0x0019002E, + .p0_mpdgctrl0 = 0x4349035C, + .p0_mpdgctrl1 = 0x0348033D, + .p1_mpdgctrl0 = 0x43550362, + .p1_mpdgctrl1 = 0x03520316, + .p0_mprddlctl = 0x41393940, + .p1_mprddlctl = 0x3F3A3C47, + .p0_mpwrdlctl = 0x413A423A, + .p1_mpwrdlctl = 0x4042483E, +}; + +/* MT41K128M16JT-125 (2Gb density) */ +static const struct mx6_ddr3_cfg mt41k128m16jt_125 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC3F, &ccm->CCGR1); + writel(0x0FFFCFC0, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); +} + +#ifdef CONFIG_SPL_SPI_SUPPORT +static void displ5_init_ecspi(void) +{ + displ5_set_iomux_ecspi_spl(); + enable_spi_clk(1, 1); +} +#else +static inline void displ5_init_ecspi(void) { } +#endif + +#ifdef CONFIG_SPL_MMC_SUPPORT +static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC4_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_init(bd_t *bd) +{ + displ5_set_iomux_usdhc_spl(); + + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; + + return fsl_esdhc_initialize(bd, &usdhc_cfg); +} +#endif + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + arch_cpu_init(); + + gpr_init(); + + /* setup GP timer */ + timer_init(); + + displ5_set_iomux_uart_spl(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + displ5_init_ecspi(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + /* Default boot sequence SPI -> MMC */ + spl_boot_list[0] = spl_boot_device(); + spl_boot_list[1] = BOOT_DEVICE_MMC1; + spl_boot_list[2] = BOOT_DEVICE_UART; + spl_boot_list[3] = BOOT_DEVICE_NONE; + +#ifdef CONFIG_SPL_ENV_SUPPORT + /* 'fastboot' */ + const char *s; + + env_init(); + env_load(); + + s = env_get("BOOT_FROM"); + if (s && strcmp(s, "ACTIVE") == 0) { + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = spl_boot_device(); + } +#endif +} + +void reset_cpu(ulong addr) {} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#ifdef CONFIG_SPL_OS_BOOT +/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */ +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + if (env_get_yesno("boot_os") != 1) + return 1; +#endif + return 0; +} +#endif diff --git a/configs/display5_defconfig b/configs/display5_defconfig new file mode 100644 index 0000000000..dfd9c2c298 --- /dev/null +++ b/configs/display5_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_DISPLAY5=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" +CONFIG_SPL=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_SAVEENV=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="display5 > " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_ASKENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig new file mode 100644 index 0000000000..3f10ffad03 --- /dev/null +++ b/configs/display5_factory_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_DISPLAY5=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" +CONFIG_BOOTDELAY=3 +CONFIG_SPL=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="display5 factory > " +CONFIG_BOOTCMD_OVERRIDE=y +CONFIG_BOOTCOMMAND="run factory" +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_ASKENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1" +CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),8m(lin-recovery),4m(swu-kernel),8m(swu-initramfs),-(reserved)" +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Liebherr" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/display5.h b/include/configs/display5.h new file mode 100644 index 0000000000..c41ab8b5e2 --- /dev/null +++ b/include/configs/display5.h @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +/* Falcon Mode */ +#define CONFIG_CMD_SPL +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 +#define CONFIG_CMD_SPL_WRITE_SIZE (44 * SZ_1K) + +/* Falcon Mode - MMC support */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ + (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x100 /* 128KiB */ + +/* + * display5 SPI-NOR memory layout + * + * The definition can be found in Kconfig's + * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT + * + * 0x000000 - 0x020000 : SPI.SPL (128KiB) + * 0x020000 - 0x120000 : SPI.u-boot (1MiB) + * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB) + * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB) + * 0x140000 - 0x940000 : SPI.fitImage-recovery (8MiB) + * 0x940000 - 0xD40000 : SPI.swupdate-kernel-FIT (4MiB) + * 0xD40000 - 0x1540000 : SPI.swupdate-initramfs (8MiB) + */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_MTD_DEVICE +#define CONFIG_SPI_FLASH_MTD +#define CONFIG_MTD_PARTITIONS +#endif + +/* Below values are "dummy" - only to avoid build break */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 + +#include "imx6_spl.h" +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SPL_SPI_LOAD + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#define CONFIG_MISC_INIT_R + +/*#define CONFIG_MXC_UART*/ +#define CONFIG_MXC_UART_BASE UART5_BASE + +/* SPI NOR Flash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(5, 29) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_EDID +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_MII +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SUPPORT_EMMC_BOOT + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 + +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run boot_mmc" +#endif + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \ + "name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \ + "name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \ + "name=rootfs2,size=1528M,uuid=${uuid_gpt_rootfs2};" \ + "name=data,size=-,uuid=${uuid_gpt_data}\0" + +#define FACTORY_PROCEDURE \ + "echo '#######################';" \ + "echo '# Factory Boot #';" \ + "echo '#######################';" \ + "env default -a;" \ + "saveenv;" \ + "gpt write mmc ${mmcdev} ${partitions};" \ + "run tftp_sf_SPL;" \ + "run tftp_sf_uboot;" \ + TFTP_UPDATE_KERNEL \ + "run tftp_sf_fitImg_recovery;" \ + "run tftp_sf_fitImg_SWU;" \ + "run tftp_sf_initramfs_SWU;" \ + TFTP_UPDATE_ROOTFS \ + "echo '#######################';" \ + "echo '# END - OK #';" \ + "echo '#######################';" \ + "setenv bootcmd 'env default -a; saveenv; run falcon_setup; reset';" \ + "setenv boot_os 'n';" \ + "saveenv;" \ + "reset;" + +#define SWUPDATE_RECOVERY_PROCEDURE \ + "echo '#######################';" \ + "echo '# RECOVERY SWUupdate #';" \ + "echo '#######################';" \ + "setenv loadaddr_swu_initramfs 0x14000000;" \ + "setenv bootargs console=${console} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}::off root=/dev/ram rw;" \ + "sf probe;" \ + "sf read ${loadaddr} swu-kernel;" \ + "sf read ${loadaddr_swu_initramfs} swu-initramfs;" \ + "bootm ${loadaddr} ${loadaddr_swu_initramfs};" + +#define KERNEL_RECOVERY_PROCEDURE \ + "echo '#######################';" \ + "echo '# RECOVERY KERNEL IMG #';" \ + "echo '#######################';" \ + "sf probe;" \ + "sf read ${loadaddr} lin-recovery;" \ + "bootm;" + +#define SETUP_BOOTARGS \ + "run set_rootfs_part;" \ + "setenv bootargs ${bootargs} console=${console} " \ + "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \ + "rootwait rootfstype=ext4 rw; " \ + "run set_kernel_part;" \ + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ + "mmc read ${loadaddr} ${lba_start} 0x2000; " \ + "setenv fdt_conf imx6q-${board}-${display}.dtb; " + +/* All the numbers are in LBAs */ +#define __TFTP_UPDATE_KERNEL \ + "tftp_mmc_fitImg=" \ + "if test ! -n ${kernel_part}; then " \ + "setenv kernel_part ${kernel_part_active};" \ + "fi;" \ + "if tftp ${loadaddr} ${kernel_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ + "; fi\0" \ + +#define TFTP_UPDATE_KERNEL \ + "setenv kernel_part ${kernel_part_active};" \ + "run tftp_mmc_fitImg;" \ + "setenv kernel_part ${kernel_part_backup};" \ + "run tftp_mmc_fitImg;" \ + +#define __TFTP_UPDATE_ROOTFS \ + "tftp_mmc_rootfs=" \ + "if test ! -n ${rootfs_part}; then " \ + "setenv rootfs_part ${rootfs_part_active};" \ + "fi;" \ + "if tftp ${loadaddr} ${rootfs_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "part start mmc ${mmcdev} ${rootfs_part} lba_start; " \ + "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ + "; fi\0" \ + +/* To save some considerable time, we only once download the rootfs image */ +/* and store it on 'active' and 'backup' rootfs partitions */ +#define TFTP_UPDATE_ROOTFS \ + "setenv rootfs_part ${rootfs_part_active};" \ + "run tftp_mmc_rootfs;" \ + "part start mmc ${mmcdev} ${rootfs_part_backup} lba_start;" \ + "mmc write ${loadaddr} ${lba_start} ${fw_sz};" \ + +#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \ + "tftp_sf_fitImg_SWU=" \ + "if tftp ${loadaddr} ${kernel_file}; then " \ + "sf probe;" \ + "sf erase swu-kernel +${filesize};" \ + "sf write ${loadaddr} swu-kernel ${filesize};" \ + "; fi\0" \ + +#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ + "swu_initramfs_file=swupdate-image-display5.ext3.gz.u-boot\0" \ + "tftp_sf_initramfs_SWU=" \ + "if tftp ${loadaddr} ${swu_initramfs_file}; then " \ + "sf probe;" \ + "sf erase swu-initramfs +${filesize};" \ + "sf write ${loadaddr} swu-initramfs ${filesize};" \ + "; fi\0" \ + +#define TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ + "kernel_recovery_file=fitImage-initramfs\0" \ + "tftp_sf_fitImg_recovery=" \ + "if tftp ${loadaddr} ${kernel_recovery_file}; then " \ + "sf probe;" \ + "sf erase lin-recovery +${filesize};" \ + "sf write ${loadaddr} lin-recovery ${filesize};" \ + "; fi\0" \ + +#define TFTP_UPDATE_BOOTLOADER \ + "ubootfile=u-boot.img\0" \ + "ubootfileSPL=SPL\0" \ + "tftp_sf_uboot=" \ + "if tftp ${loadaddr} ${ubootfile}; then " \ + "sf probe;" \ + "sf erase u-boot +${filesize};" \ + "sf write ${loadaddr} u-boot ${filesize}" \ + "; fi\0" \ + "tftp_sf_SPL=" \ + "if tftp ${loadaddr} ${ubootfileSPL}; then " \ + "sf probe;" \ + "setexpr uboot_SPL_size ${filesize} + 0x400;" \ + "sf erase 0x0 +${uboot_SPL_size};" \ + "sf write ${loadaddr} 0x400 ${filesize};" \ + "fi\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + PARTS_DEFAULT \ + "display=tianma-tm070-800x480\0" \ + "board=display5\0" \ + "mmcdev=0\0" \ + "altbootcmd=run recovery\0" \ + "bootdelay=1\0" \ + "baudrate=115200\0" \ + "bootcmd=" CONFIG_BOOTCOMMAND "\0" \ + "factory=" FACTORY_PROCEDURE "\0" \ + "bootlimit=3\0" \ + "ethact=FEC\0" \ + "netdev=eth0\0" \ + "boot_os=y\0" \ + "hostname=display5\0" \ + "loadaddr=0x12000000\0" \ + "fdtaddr=0x12800000\0" \ + "console=ttymxc4,115200 quiet\0" \ + "fdtfile=imx6q-display5.dtb\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_file=fitImage\0" \ + "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ + "download_kernel=" \ + "tftpboot ${loadaddr} ${kernel_file};\0" \ + "boot_kernel_recovery=" KERNEL_RECOVERY_PROCEDURE "\0" \ + "boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \ + "recovery=" \ + "if test ${BOOT_FROM_RECOVERY} = SWU; then " \ + "echo BOOT: RECOVERY: SWU;" \ + "run boot_swu_recovery;" \ + "else " \ + "echo BOOT: RECOVERY: Linux;" \ + "run boot_kernel_recovery;" \ + "fi\0" \ + "boot_tftp=" \ + "if run download_kernel; then " \ + "setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rootwait;" \ + "bootm ${loadaddr} - ${fdtaddr};" \ + "fi\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:eth0:on" \ + "\0" \ + "nfsargs=setenv bootargs " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \ + "\0" \ + "rootpath=/srv/tftp/DISP5/rootfs\0" \ + "boot_nfs=" \ + "if run download_kernel; then " \ + "run nfsargs;" \ + "run addip;" \ + "setenv bootargs ${bootargs} console=${console};" \ + "setenv fdt_conf imx6q-${board}-${display}.dtb; " \ + "bootm ${loadaddr}#conf@${fdt_conf};" \ + "fi\0" \ + "falcon_setup=" \ + "if mmc dev ${mmcdev}; then " \ + SETUP_BOOTARGS \ + "spl export fdt ${loadaddr}#conf@${fdt_conf};" \ + "setexpr fw_sz ${fdtargslen} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${fdtargsaddr} " \ + __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" ${fw_sz}; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmc dev ${mmcdev}; then " \ + SETUP_BOOTARGS \ + "bootm ${loadaddr}#conf@${fdt_conf};" \ + "fi\0" \ + "set_kernel_part=" \ + "if test ${BOOT_FROM} = ACTIVE; then " \ + "setenv kernel_part ${kernel_part_active};" \ + "echo BOOT: ACTIVE;" \ + "else if test ${BOOT_FROM} = BACKUP; then " \ + "setenv kernel_part ${kernel_part_backup};" \ + "echo BOOT: BACKUP;" \ + "else " \ + "run recovery;" \ + "fi;fi\0" \ + "set_rootfs_part=" \ + "if test ${BOOT_FROM} = ACTIVE; then " \ + "setenv rootfs_part ${rootfs_part_active};" \ + "else if test ${BOOT_FROM} = BACKUP; then " \ + "setenv rootfs_part ${rootfs_part_backup};" \ + "else " \ + "run recovery;" \ + "fi;fi\0" \ + "BOOT_FROM=ACTIVE\0" \ + "BOOT_FROM_RECOVERY=Linux\0" \ + TFTP_UPDATE_BOOTLOADER \ + "kernel_part_active=1\0" \ + "kernel_part_backup=3\0" \ + __TFTP_UPDATE_KERNEL \ + "rootfs_part_active=2\0" \ + "rootfs_part_backup=4\0" \ + "rootfs_file=core-image-lwn-display5.ext4\0" \ + __TFTP_UPDATE_ROOTFS \ + TFTP_UPDATE_RECOVERY_KERNEL_INITRAMFS \ + TFTP_UPDATE_RECOVERY_SWU_KERNEL \ + TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ + "\0" \ + +/* Miscellaneous configurable options */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 2048 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE + +/* ENV config */ +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (SZ_64K) +/* The 0x120000 value corresponds to above SPI-NOR memory MAP */ +#define CONFIG_ENV_OFFSET (0x120000) +#define CONFIG_ENV_SECT_SIZE (SZ_64K) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif /* __CONFIG_H */
This commit provides support for LWN's IMX6Q based DISPLAY5 board. Signed-off-by: Lukasz Majewski <lukma@denx.de> --- Changes in v4: - Refactor obscure sw/hw rev code for display5 board - replace get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); with imx_ddr_size() - remove PHYS_SDRAM_SIZE from display5.h - Replace non generic setup of RGMII pins voltage levels with a generic function - Move displ5_set_iomux_uart() - non console UART init to board_init() - Disable board_early_init_f() calls (prod/factory) - Move mtdparts to Kconfig for production and flash u-boot Changes in v3: - Remove ip custom data - Cleanup SPL code Changes in v2: - Update to newest mainline u-boot arch/arm/dts/imx6q-display5.dts | 18 ++ arch/arm/mach-imx/mx6/Kconfig | 7 + board/liebherr/display5/Kconfig | 18 ++ board/liebherr/display5/MAINTAINERS | 7 + board/liebherr/display5/Makefile | 11 + board/liebherr/display5/common.c | 111 ++++++++++ board/liebherr/display5/common.h | 42 ++++ board/liebherr/display5/display5.c | 384 +++++++++++++++++++++++++++++++++ board/liebherr/display5/spl.c | 247 ++++++++++++++++++++++ configs/display5_defconfig | 62 ++++++ configs/display5_factory_defconfig | 76 +++++++ include/configs/display5.h | 408 ++++++++++++++++++++++++++++++++++++ 12 files changed, 1391 insertions(+) create mode 100644 arch/arm/dts/imx6q-display5.dts create mode 100644 board/liebherr/display5/Kconfig create mode 100644 board/liebherr/display5/MAINTAINERS create mode 100644 board/liebherr/display5/Makefile create mode 100644 board/liebherr/display5/common.c create mode 100644 board/liebherr/display5/common.h create mode 100644 board/liebherr/display5/display5.c create mode 100644 board/liebherr/display5/spl.c create mode 100644 configs/display5_defconfig create mode 100644 configs/display5_factory_defconfig create mode 100644 include/configs/display5.h