| Message ID | 20171102003606.19913-2-david.daney@cavium.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | Cavium OCTEON-III network driver. | expand |
On 11/01/2017 05:36 PM, David Daney wrote: > From: Carlos Munoz <cmunoz@cavium.com> > > Add bindings for Common Ethernet Interface (BGX) block. > > Signed-off-by: Carlos Munoz <cmunoz@cavium.com> > Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> > Signed-off-by: David Daney <david.daney@cavium.com> > --- [snip] > +Properties: > + > +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. > + > +- reg: The index of the interface within the BGX block. > + > +- local-mac-address: Mac address for the interface. > + > +- phy-handle: phandle to the phy node connected to the interface. > + > +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. > + Needed by the Micrel PHY. Is not that implied by an appropriate "phy-mode" property already?
On 11/01/2017 06:09 PM, Florian Fainelli wrote: > On 11/01/2017 05:36 PM, David Daney wrote: >> From: Carlos Munoz <cmunoz@cavium.com> >> >> Add bindings for Common Ethernet Interface (BGX) block. >> >> Signed-off-by: Carlos Munoz <cmunoz@cavium.com> >> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> >> Signed-off-by: David Daney <david.daney@cavium.com> >> --- > [snip] >> +Properties: >> + >> +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. >> + >> +- reg: The index of the interface within the BGX block. >> + >> +- local-mac-address: Mac address for the interface. >> + >> +- phy-handle: phandle to the phy node connected to the interface. >> + >> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. >> + Needed by the Micrel PHY. > > Is not that implied by an appropriate "phy-mode" property already? I think you are correct. That string never appears in the source code, so I am going to remove that property from the binding document for the next revision of the patch set. Thanks, David Daney
On Wed, Nov 01, 2017 at 06:09:17PM -0700, Florian Fainelli wrote: > On 11/01/2017 05:36 PM, David Daney wrote: > > From: Carlos Munoz <cmunoz@cavium.com> > > > > Add bindings for Common Ethernet Interface (BGX) block. > > > > Signed-off-by: Carlos Munoz <cmunoz@cavium.com> > > Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> > > Signed-off-by: David Daney <david.daney@cavium.com> > > --- > [snip] > > +Properties: > > + > > +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. > > + > > +- reg: The index of the interface within the BGX block. > > + > > +- local-mac-address: Mac address for the interface. > > + > > +- phy-handle: phandle to the phy node connected to the interface. > > + > > +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. > > + Needed by the Micrel PHY. > > Is not that implied by an appropriate "phy-mode" property already? Hi Florian Looking at the driver patch, phy-mode is not used at all. of_phy_connect() passes a hard coded SGMII value! David, you need to fix this. Andrew
On 11/02/2017 05:47 AM, Andrew Lunn wrote: > On Wed, Nov 01, 2017 at 06:09:17PM -0700, Florian Fainelli wrote: >> On 11/01/2017 05:36 PM, David Daney wrote: >>> From: Carlos Munoz <cmunoz@cavium.com> >>> >>> Add bindings for Common Ethernet Interface (BGX) block. >>> >>> Signed-off-by: Carlos Munoz <cmunoz@cavium.com> >>> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> >>> Signed-off-by: David Daney <david.daney@cavium.com> >>> --- >> [snip] >>> +Properties: >>> + >>> +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. >>> + >>> +- reg: The index of the interface within the BGX block. >>> + >>> +- local-mac-address: Mac address for the interface. >>> + >>> +- phy-handle: phandle to the phy node connected to the interface. >>> + >>> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. >>> + Needed by the Micrel PHY. >> >> Is not that implied by an appropriate "phy-mode" property already? > > Hi Florian > > Looking at the driver patch, phy-mode is not used at > all. of_phy_connect() passes a hard coded SGMII value! > > David, you need to fix this. > Yes, I think you are correct. Thanks for reviewing this, David Daney
diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt b/Documentation/devicetree/bindings/net/cavium-bgx.txt new file mode 100644 index 000000000000..9fb79f8bc17f --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt @@ -0,0 +1,59 @@ +* Common Ethernet Interface (BGX) block + +Properties: + +- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs. + +- reg: The base address of the BGX block. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. BGX addresses have no size component. + +Typically a BGX block has several children each representing an +Ethernet interface. + +Example: + + ethernet-mac-nexus@11800e0000000 { + compatible = "cavium,octeon-7890-bgx"; + reg = <0x00011800 0xe0000000 0x00000000 0x01000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-mac@0 { + ... + reg = <0>; + }; + }; + + +* Ethernet Interface (BGX port) connects to PKI/PKO + +Properties: + +- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all cn7xxx + SOCs. + +- reg: The index of the interface within the BGX block. + +- local-mac-address: Mac address for the interface. + +- phy-handle: phandle to the phy node connected to the interface. + + +* Ethernet Interface (BGX port) connects to XCV + + +Properties: + +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. + +- reg: The index of the interface within the BGX block. + +- local-mac-address: Mac address for the interface. + +- phy-handle: phandle to the phy node connected to the interface. + +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. + Needed by the Micrel PHY.