| Message ID | 20171024175546.27664-1-palmer@dabbelt.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Add Sign/Zero extend patterns for PIC loads | expand |
Committed. On Tue, 24 Oct 2017 10:55:46 PDT (-0700), Palmer Dabbelt wrote: > Loads on RISC-V are sign-extending by default, but we weren't telling > GCC this in our PIC load patterns. This corrects the problem, and adds > a zero-extending pattern as well. > > gcc/ChangeLog > > 2017-10-24 Palmer Dabbelt <palmer@dabbelt.com> > > * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. > * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s, > mark as a sign-extending load. > (local_pic_load_u): Define. > --- > gcc/config/riscv/pic.md | 11 +++++++++-- > gcc/config/riscv/riscv.md | 3 +++ > 2 files changed, 12 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md > index 6a29ead32d36..03b8f9bc669e 100644 > --- a/gcc/config/riscv/pic.md > +++ b/gcc/config/riscv/pic.md > @@ -22,13 +22,20 @@ > ;; Simplify PIC loads to static variables. > ;; These should go away once we figure out how to emit auipc discretely. > > -(define_insn "*local_pic_load<mode>" > +(define_insn "*local_pic_load_s<mode>" > [(set (match_operand:ANYI 0 "register_operand" "=r") > - (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))] > + (sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))] > "USE_LOAD_ADDRESS_MACRO (operands[1])" > "<load>\t%0,%1" > [(set (attr "length") (const_int 8))]) > > +(define_insn "*local_pic_load_u<mode>" > + [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r") > + (zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))] > + "USE_LOAD_ADDRESS_MACRO (operands[1])" > + "<load>u\t%0,%1" > + [(set (attr "length") (const_int 8))]) > + > (define_insn "*local_pic_load<mode>" > [(set (match_operand:ANYF 0 "register_operand" "=f") > (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index fd9236c7c170..9f056bbcda4f 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -259,6 +259,9 @@ > ;; Iterator for QImode extension patterns. > (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) > > +;; Iterator for extending loads. > +(define_mode_iterator ZERO_EXTEND_LOAD [QI HI (SI "TARGET_64BIT")]) > + > ;; Iterator for hardware integer modes narrower than XLEN. > (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])
diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md index 6a29ead32d36..03b8f9bc669e 100644 --- a/gcc/config/riscv/pic.md +++ b/gcc/config/riscv/pic.md @@ -22,13 +22,20 @@ ;; Simplify PIC loads to static variables. ;; These should go away once we figure out how to emit auipc discretely. -(define_insn "*local_pic_load<mode>" +(define_insn "*local_pic_load_s<mode>" [(set (match_operand:ANYI 0 "register_operand" "=r") - (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))] + (sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))] "USE_LOAD_ADDRESS_MACRO (operands[1])" "<load>\t%0,%1" [(set (attr "length") (const_int 8))]) +(define_insn "*local_pic_load_u<mode>" + [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r") + (zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))] + "USE_LOAD_ADDRESS_MACRO (operands[1])" + "<load>u\t%0,%1" + [(set (attr "length") (const_int 8))]) + (define_insn "*local_pic_load<mode>" [(set (match_operand:ANYF 0 "register_operand" "=f") (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index fd9236c7c170..9f056bbcda4f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -259,6 +259,9 @@ ;; Iterator for QImode extension patterns. (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) +;; Iterator for extending loads. +(define_mode_iterator ZERO_EXTEND_LOAD [QI HI (SI "TARGET_64BIT")]) + ;; Iterator for hardware integer modes narrower than XLEN. (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])
Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-10-24 Palmer Dabbelt <palmer@dabbelt.com> * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s, mark as a sign-extending load. (local_pic_load_u): Define. --- gcc/config/riscv/pic.md | 11 +++++++++-- gcc/config/riscv/riscv.md | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-)