| Message ID | 20171016111712.16783-1-alexander.sverdlin@nokia.com |
|---|---|
| State | Rejected |
| Delegated to: | Cyrille Pitchen |
| Headers | show |
| Series | mtd: spi-nor: Enable stateless 4-byte opcodes for N25Q256A/N25Q512A/N25Q00 | expand |
On 10/16/2017 01:17 PM, Alexander Sverdlin wrote: > The datasheets explicitly state that the stateless opcodes are supported > and that they "do not need to be set up in the addressing mode". > > The stateless mode is clearly more beneficial, because there are boot > ROM code versions not able to cope with the chip left in 4-byte state. > > Tested with Micron N25Q512A. > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Can SFDP help here ? > --- > drivers/mtd/spi-nor/spi-nor.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 3128d8c..85670b1b 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1052,12 +1052,12 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, > + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, > > /* PMC */ > { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, >
Hello Marek, On 16/10/17 13:35, Marek Vasut wrote: >> The datasheets explicitly state that the stateless opcodes are supported >> and that they "do not need to be set up in the addressing mode". >> >> The stateless mode is clearly more beneficial, because there are boot >> ROM code versions not able to cope with the chip left in 4-byte state. >> >> Tested with Micron N25Q512A. >> >> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> > Can SFDP help here ? it would be nice, but I've just checked - JESD216 - "TN-25-06: Serial Flash Discovery Parameters for MT25Q Family" - N25Q512A "Serial Flash Discovery Parameter Data Structure" seems, such flag is not provided in the standard. There is a way to figure out if the chip supports entering 4-bytes mode and what is the command to enter such a mode, but nothing for the stateless commands. I would be glad to be wrong in this particular case.
Hi Alexander, Le 16/10/2017 à 14:25, Alexander Sverdlin a écrit : > Hello Marek, > > On 16/10/17 13:35, Marek Vasut wrote: >>> The datasheets explicitly state that the stateless opcodes are supported >>> and that they "do not need to be set up in the addressing mode". >>> I don't totally agree. Micron memories have a little quirk: if you look closely at their datasheets (currently reading the N25Q512A datasheet) the 12h op code doesn't always work as expected. For some memory parts, the 12h op code is used for 4-byte address Page Program 1-1-1 (as it should) whereas for other memory parts, this very same op code means 3-byte address Page Program x-4-4 (non standard usage, should have been 38h/3Eh). See note 18: """ The code 38h is valid only for part numbers N25Q512A83GSF40x, N25Q512A83G1240x, N25Q512A83GSFA0x, N25Q512A83G12A0x and N25Q512A83G12H0x; the code 12h is valid for the other part numbers """ Also about the 4-byte address Page Program 1-1-1 and 1-1-4, see note 17: """ Only available for part numbers N25Q512A83GSF40x, N25Q512A83G1240x, N25Q512A83GSFA0x, N25Q512A83G12A0x and N25Q512A83G12H0x """ So even with the basic Page Program 1-1-1, this patch would introduce regressions with some memory parts. This is a known issue of Micron memories and this is why the SPI_NOR_4B_OPCODES flag was not set before for those memories! >>> The stateless mode is clearly more beneficial, because there are boot >>> ROM code versions not able to cope with the chip left in 4-byte state. >>> I agree with you on that: it was the purpose of patch adding support to the 4-byte address instruction set ;) >>> Tested with Micron N25Q512A. >>> >>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> >> Can SFDP help here ? > > it would be nice, but I've just checked > - JESD216 > - "TN-25-06: Serial Flash Discovery Parameters for MT25Q Family" > - N25Q512A "Serial Flash Discovery Parameter Data Structure" > > seems, such flag is not provided in the standard. There is a way > to figure out if the chip supports entering 4-bytes mode and what > is the command to enter such a mode, but nothing for the stateless commands. > > I would be glad to be wrong in this particular case. > The "4-byte address instruction set" is an optional SFDP table. It is supported by latest Macronix memories but not by the Micron N25Q* memories. Best regards, Cyrille
Hello Cyrille, On 16/10/17 23:27, Cyrille Pitchen wrote: > Hi Alexander, > > Le 16/10/2017 à 14:25, Alexander Sverdlin a écrit : >> Hello Marek, >> >> On 16/10/17 13:35, Marek Vasut wrote: >>>> The datasheets explicitly state that the stateless opcodes are supported >>>> and that they "do not need to be set up in the addressing mode". >>>> > > I don't totally agree. Micron memories have a little quirk: if you look > closely at their datasheets (currently reading the N25Q512A datasheet) > the 12h op code doesn't always work as expected. > > For some memory parts, the 12h op code is used for 4-byte address Page > Program 1-1-1 (as it should) whereas for other memory parts, this very > same op code means 3-byte address Page Program x-4-4 (non standard > usage, should have been 38h/3Eh). > > See note 18: > """ > The code 38h is valid only for part numbers N25Q512A83GSF40x, > N25Q512A83G1240x, > N25Q512A83GSFA0x, N25Q512A83G12A0x and N25Q512A83G12H0x; the code 12h is > valid for the other part numbers > """ > > Also about the 4-byte address Page Program 1-1-1 and 1-1-4, see note 17: > """ > Only available for part numbers N25Q512A83GSF40x, N25Q512A83G1240x, > N25Q512A83GSFA0x, N25Q512A83G12A0x and N25Q512A83G12H0x > """ > > So even with the basic Page Program 1-1-1, this patch would introduce > regressions with some memory parts. > > This is a known issue of Micron memories and this is why the > SPI_NOR_4B_OPCODES flag was not set before for those memories! yes, you are right, while 256/512Mbit variants just potentially have some non-standard variations, in N25Q00AA series 12h command has non-standard mapping in all parts. Seems, we have to just scrap this patch.
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 3128d8c..85670b1b 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1052,12 +1052,12 @@ static const struct flash_info spi_nor_ids[] = { { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
The datasheets explicitly state that the stateless opcodes are supported and that they "do not need to be set up in the addressing mode". The stateless mode is clearly more beneficial, because there are boot ROM code versions not able to cope with the chip left in 4-byte state. Tested with Micron N25Q512A. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> --- drivers/mtd/spi-nor/spi-nor.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)