[2/2] aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat

The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
ctr_el0 register, which tells us the minimum observable cache line
size by userspace.  This typically is the same as the L1 cache line
size, but that may not always be true.  It could be a higher level
cache line size as long as cache cleaning and invalidation work
correctly with that line size in userspace.  The falkor core for
example reports the L2 line size as the dcache line size in CTR_EL0
while also reporting the correct L1 dcache line size via CCSIDR_EL1.

	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
---
 manual/conf.texi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

On 11/10/17 12:53, Siddhesh Poyarekar wrote:
> The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
> ctr_el0 register, which tells us the minimum observable cache line
> size by userspace.  This typically is the same as the L1 cache line
> size, but that may not always be true.  It could be a higher level
> cache line size as long as cache cleaning and invalidation work
> correctly with that line size in userspace.  The falkor core for
> example reports the L2 line size as the dcache line size in CTR_EL0
> while also reporting the correct L1 dcache line size via CCSIDR_EL1.
> 
> 	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
> 	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.

looks ok with the typo fixed below

> ---
>  manual/conf.texi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/manual/conf.texi b/manual/conf.texi
> index 503b240..66a7f35 100644
> --- a/manual/conf.texi
> +++ b/manual/conf.texi
> @@ -690,6 +690,12 @@ Inquire about associativity of the Level 1 instruction cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 instruction cache.
>  
> +On aarch64, the cache line size returned is the minimum instruction cache line
> +size observeable by userspace.  This is typically the same as the L1 icache

*observable

> +size but on some cores it may not be so.  It is specified in the architecture
> +however that operations such as cache line invalidation are consistent with the
> +size reported with this variable.
> +
>  @item _SC_LEVEL1_DCACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 1 data cache.
> @@ -702,6 +708,12 @@ Inquire about associativity of the Level 1 data cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 data cache.
>  
> +On aarch64, the cache line size returned is the minimum data cache line size
> +observeable by userspace.  This is typically the same as the L1 dcache size but
> +on some cores it may not be so.  It is specified in the architecture however
> +that operations such as cache line invalidation are consistent with the size
> +reported with this variable.
> +
>  @item _SC_LEVEL2_CACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 2 cache.
>

I can't speak for the content, but the patch looks OK, save a couple
minor issues.

On 10/11/2017 04:53 AM, Siddhesh Poyarekar wrote:
> The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
> ctr_el0 register, which tells us the minimum observable cache line
> size by userspace.  This typically is the same as the L1 cache line
> size, but that may not always be true.  It could be a higher level
> cache line size as long as cache cleaning and invalidation work
> correctly with that line size in userspace.  The falkor core for
> example reports the L2 line size as the dcache line size in CTR_EL0
> while also reporting the correct L1 dcache line size via CCSIDR_EL1.
> 
> 	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
> 	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
> ---
>  manual/conf.texi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/manual/conf.texi b/manual/conf.texi
> index 503b240..66a7f35 100644
> --- a/manual/conf.texi
> +++ b/manual/conf.texi
> @@ -690,6 +690,12 @@ Inquire about associativity of the Level 1 instruction cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 instruction cache.
>  
> +On aarch64, the cache line size returned is the minimum instruction cache line
> +size observeable by userspace.  This is typically the same as the L1 icache

observable

> +size but on some cores it may not be so.  It is specified in the architecture
> +however that operations such as cache line invalidation are consistent with the

I would write, "...architecture, however, ...", or begin the sentence
with "However, ...".

> +size reported with this variable.
> +
>  @item _SC_LEVEL1_DCACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 1 data cache.
> @@ -702,6 +708,12 @@ Inquire about associativity of the Level 1 data cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 data cache.
>  
> +On aarch64, the cache line size returned is the minimum data cache line size
> +observeable by userspace.  This is typically the same as the L1 dcache size but

observable

> +on some cores it may not be so.  It is specified in the architecture however

Commas here too.

> +that operations such as cache line invalidation are consistent with the size
> +reported with this variable.
> +
>  @item _SC_LEVEL2_CACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 2 cache.

Rical

Thanks, pushed with nits fixed.

Siddhesh