| Message ID | 20101112180521.2755.28346.stgit@localhost6.localdomain6 |
|---|---|
| State | Changes Requested |
| Delegated to: | Minkyu Kang |
| Headers | show |
Dear Darius Augulis, On 13 November 2010 03:05, Darius Augulis <augulis.darius@gmail.com> wrote: > Fix pll divider values to standard ones described > in "S3C6410X RISC Microprocessor User's Manual, > Revision 1.20", p. 3-21. > > Signed-off-by: Darius Augulis <augulis.darius@gmail.com> > --- > arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 17 ++++++----------- > 1 files changed, 6 insertions(+), 11 deletions(-) > Hm, no.. Please consider s3c6400. Those values are fit with s3c6400. Thanks Minkyu Kang
Hi, On Fri, Nov 19, 2010 at 10:32 AM, Minkyu Kang <promsoft@gmail.com> wrote: > Dear Darius Augulis, > > On 13 November 2010 03:05, Darius Augulis <augulis.darius@gmail.com> wrote: >> Fix pll divider values to standard ones described >> in "S3C6410X RISC Microprocessor User's Manual, >> Revision 1.20", p. 3-21. >> >> Signed-off-by: Darius Augulis <augulis.darius@gmail.com> >> --- >> arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 17 ++++++----------- >> 1 files changed, 6 insertions(+), 11 deletions(-) >> > > Hm, no.. > Please consider s3c6400. > Those values are fit with s3c6400. does s3c6400 have different clock controller compared to s3c6410? I have only old manual of s3c6400 and it has the same equation for pll clock setting. Please take a look into arch/arm/cpu/arm1176/s3c64xx/speed.c. There are common functions for both CPU's and they work ok. So i guess my patch should not break s3c6400 operation. Btw, we don't have any working s3c6400 board in main line and it seems nobody is interested to have one. Darius. > > Thanks > Minkyu Kang > -- > from. prom. > www.promsoft.net >
Dear Darius Augulis, On 19 November 2010 17:54, Darius Augulis <augulis.darius@gmail.com> wrote: > Hi, > > On Fri, Nov 19, 2010 at 10:32 AM, Minkyu Kang <promsoft@gmail.com> wrote: >> Dear Darius Augulis, >> >> On 13 November 2010 03:05, Darius Augulis <augulis.darius@gmail.com> wrote: >>> Fix pll divider values to standard ones described >>> in "S3C6410X RISC Microprocessor User's Manual, >>> Revision 1.20", p. 3-21. >>> >>> Signed-off-by: Darius Augulis <augulis.darius@gmail.com> >>> --- >>> arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 17 ++++++----------- >>> 1 files changed, 6 insertions(+), 11 deletions(-) >>> >> >> Hm, no.. >> Please consider s3c6400. >> Those values are fit with s3c6400. > > does s3c6400 have different clock controller compared to s3c6410? > I have only old manual of s3c6400 and it has the same equation for pll > clock setting. > Please take a look into arch/arm/cpu/arm1176/s3c64xx/speed.c. There > are common functions for both CPU's and > they work ok. So i guess my patch should not break s3c6400 operation. According to the TRM... Equations are same. but, recommended values are different. Your patch is no guarantee with s3c6400. Did you tested with s3c6400? > Btw, we don't have any working s3c6400 board in main line and it seems > nobody is interested to have one. We have the SMDK6400. Thanks Minkyu Kang
Hi, On 11/22/2010 10:48 AM, Minkyu Kang wrote: > Dear Darius Augulis, > > On 19 November 2010 17:54, Darius Augulis<augulis.darius@gmail.com> wrote: >> Hi, >> >> On Fri, Nov 19, 2010 at 10:32 AM, Minkyu Kang<promsoft@gmail.com> wrote: >>> Dear Darius Augulis, >>> >>> On 13 November 2010 03:05, Darius Augulis<augulis.darius@gmail.com> wrote: >>>> Fix pll divider values to standard ones described >>>> in "S3C6410X RISC Microprocessor User's Manual, >>>> Revision 1.20", p. 3-21. >>>> >>>> Signed-off-by: Darius Augulis<augulis.darius@gmail.com> >>>> --- >>>> arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 17 ++++++----------- >>>> 1 files changed, 6 insertions(+), 11 deletions(-) >>>> >>> >>> Hm, no.. >>> Please consider s3c6400. >>> Those values are fit with s3c6400. >> >> does s3c6400 have different clock controller compared to s3c6410? >> I have only old manual of s3c6400 and it has the same equation for pll >> clock setting. >> Please take a look into arch/arm/cpu/arm1176/s3c64xx/speed.c. There >> are common functions for both CPU's and >> they work ok. So i guess my patch should not break s3c6400 operation. > > According to the TRM... what does this abbreviation mean? > Equations are same. but, recommended values are different. you are wrong. There is table in s3c6400 manual, but it doesn't contain recommended values, only examples how to calculate. Please find default values in APLL_CON, MPLL_CON and EPLL_CON0 registers. After reset, default frequency of APLL/MPLL for both s3c6400 and s3c6410 are 400MHz/133MHz respectively. But values in table in s3c6400 manual do not fit default register values for these frequencies. And recommended values in s3c6410 manual do. Therefore I suggest to use values from s3c6410 manual. > Your patch is no guarantee with s3c6400. > Did you tested with s3c6400? no. please see next comment below. > >> Btw, we don't have any working s3c6400 board in main line and it seems >> nobody is interested to have one. > > We have the SMDK6400. you are wrong there again. it does not compile at all. for a long time enough. Darius. > > Thanks > Minkyu Kang
Le 22/11/2010 18:44, Darius Augulis a écrit : >> According to the TRM... > > what does this abbreviation mean? Technical Reference Manual. Amicalement,
Dear Darius Augulis, On 23 November 2010 02:44, Darius Augulis <augulis.darius@gmail.com> wrote: > Hi, > > On 11/22/2010 10:48 AM, Minkyu Kang wrote: >> >> Dear Darius Augulis, >> >> On 19 November 2010 17:54, Darius Augulis<augulis.darius@gmail.com> >> wrote: >>> >>> Hi, >>> >>> On Fri, Nov 19, 2010 at 10:32 AM, Minkyu Kang<promsoft@gmail.com> wrote: >>>> >>>> Dear Darius Augulis, >>>> >>>> On 13 November 2010 03:05, Darius Augulis<augulis.darius@gmail.com> >>>> wrote: >>>>> >>>>> Fix pll divider values to standard ones described >>>>> in "S3C6410X RISC Microprocessor User's Manual, >>>>> Revision 1.20", p. 3-21. >>>>> >>>>> Signed-off-by: Darius Augulis<augulis.darius@gmail.com> >>>>> --- >>>>> arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 17 ++++++----------- >>>>> 1 files changed, 6 insertions(+), 11 deletions(-) >>>>> >>>> >>>> Hm, no.. >>>> Please consider s3c6400. >>>> Those values are fit with s3c6400. >>> >>> does s3c6400 have different clock controller compared to s3c6410? >>> I have only old manual of s3c6400 and it has the same equation for pll >>> clock setting. >>> Please take a look into arch/arm/cpu/arm1176/s3c64xx/speed.c. There >>> are common functions for both CPU's and >>> they work ok. So i guess my patch should not break s3c6400 operation. >> >> According to the TRM... > > what does this abbreviation mean? > >> Equations are same. but, recommended values are different. > > you are wrong. There is table in s3c6400 manual, but it doesn't contain > recommended values, only examples how to calculate. Please find default > values in APLL_CON, MPLL_CON and EPLL_CON0 registers. After reset, default > frequency of APLL/MPLL for both s3c6400 and s3c6410 are 400MHz/133MHz > respectively. But values in table in s3c6400 manual do not fit default > register values for these frequencies. And recommended values in s3c6410 > manual do. Therefore I suggest to use values from s3c6410 manual. It's not clear. I didn't said that your patch is wrong. I just asked you please consider s3c6400. If you or someone else do test your patch on s3c6400 then I'll accept your patch. Or, if you separate setup values from s3c6400 then I'll accept your patch. In this case, when somebody test your patch, then we can share values between s3c6400 and s3c6410. > >> Your patch is no guarantee with s3c6400. >> Did you tested with s3c6400? > > no. please see next comment below. > >> >>> Btw, we don't have any working s3c6400 board in main line and it seems >>> nobody is interested to have one. >> >> We have the SMDK6400. > > you are wrong there again. it does not compile at all. for a long time > enough. So we should drop this board? No. I don't think so. We (me or you or someone else) must fix it. Thanks Minkyu Kang
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index 10b3324..a197b4e 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -762,24 +762,19 @@ #define TIMER3_ON (TCON_3_ONOFF * 1) #define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) -#if defined(CONFIG_CLK_400_100_50) +#if defined(CONFIG_CLK_400_133_66) #define STARTUP_AMDIV 400 #define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 +#define STARTUP_PDIV 3 +#define STARTUP_SDIV 2 #elif defined(CONFIG_CLK_533_133_66) #define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 +#define STARTUP_MDIV 266 +#define STARTUP_PDIV 3 #define STARTUP_SDIV 1 #elif defined(CONFIG_CLK_667_133_66) #define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 +#define STARTUP_MDIV 333 #define STARTUP_PDIV 6 #define STARTUP_SDIV 1 #endif
Fix pll divider values to standard ones described in "S3C6410X RISC Microprocessor User's Manual, Revision 1.20", p. 3-21. Signed-off-by: Darius Augulis <augulis.darius@gmail.com> --- arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 17 ++++++----------- 1 files changed, 6 insertions(+), 11 deletions(-)