===================================================================
@@ -5337,7 +5337,7 @@
[(set_attr "type" "bitrw")])
(define_insn "*bsetdreg"
- [(set (match_operand:SI 0 "register_operand" "+d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (ashift:SI (const_int 1)
(and:SI (match_operand:SI 1 "register_operand" "d")
(const_int 31)))
@@ -5350,7 +5350,7 @@
[(set_attr "type" "bitrw")])
(define_insn "*bchgdreg"
- [(set (match_operand:SI 0 "register_operand" "+d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(xor:SI (ashift:SI (const_int 1)
(and:SI (match_operand:SI 1 "register_operand" "d")
(const_int 31)))
@@ -5363,7 +5363,7 @@
[(set_attr "type" "bitrw")])
(define_insn "*bclrdreg"
- [(set (match_operand:SI 0 "register_operand" "+d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (rotate:SI (const_int -2)
(and:SI (match_operand:SI 1 "register_operand" "d")
(const_int 31)))
===================================================================
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+
+int a, b, c, d, e;
+void f ()
+{
+ long g, h;
+ if (c)
+ e = d;
+ g = d & 31;
+ h = 1 << g;
+ a = e | h;
+ b = a;
+}