Message ID | 635dd014238af6f48c4169439b7ac161e80de1b7.1496695540.git.chunkeey@googlemail.com |
---|---|
State | Changes Requested, archived |
Delegated to: | David Miller |
Headers | show |
> In order to stay compatible with existing configurations, the > driver will try the normal reset first and only falls back to > to the internal clock, after the first reset fails. If the > second reset fails as well, it will give up as before. Hi Christian This gets things probed correctly. But should you swap back to the PHY clock when the PHY declares the link up? Is there code already to do this? Andrew
On Monday, June 5, 2017 11:26:17 PM CEST Andrew Lunn wrote: > > In order to stay compatible with existing configurations, the > > driver will try the normal reset first and only falls back to > > to the internal clock, after the first reset fails. If the > > second reset fails as well, it will give up as before. > > Hi Christian > > This gets things probed correctly. But should you swap back to the PHY > clock when the PHY declares the link up? Is there code already to do > this? > > Andrew > Oh, sorry. I omitted this from the commit message. But the proposed emac_reset() code switched to the internal clock only after the first attempt has failed AND only for the duration of the reset. If the reset succeeds or the reset times out, the clock is always switched back to the external clock. Thanks, Christian
On Mon, Jun 05, 2017 at 11:44:46PM +0200, Christian Lamparter wrote: > On Monday, June 5, 2017 11:26:17 PM CEST Andrew Lunn wrote: > > > In order to stay compatible with existing configurations, the > > > driver will try the normal reset first and only falls back to > > > to the internal clock, after the first reset fails. If the > > > second reset fails as well, it will give up as before. > > > > Hi Christian > > > > This gets things probed correctly. But should you swap back to the PHY > > clock when the PHY declares the link up? Is there code already to do > > this? > > > > Andrew > > > Oh, sorry. I omitted this from the commit message. But the proposed > emac_reset() code switched to the internal clock only after the first attempt > has failed AND only for the duration of the reset. > > If the reset succeeds or the reset times out, the clock is always switched > back to the external clock. Thanks for the clarification. Maybe add it to the commit message. Andrew
From: Andrew Lunn <andrew@lunn.ch> Date: Mon, 5 Jun 2017 23:48:57 +0200 > On Mon, Jun 05, 2017 at 11:44:46PM +0200, Christian Lamparter wrote: >> On Monday, June 5, 2017 11:26:17 PM CEST Andrew Lunn wrote: >> > > In order to stay compatible with existing configurations, the >> > > driver will try the normal reset first and only falls back to >> > > to the internal clock, after the first reset fails. If the >> > > second reset fails as well, it will give up as before. >> > >> > Hi Christian >> > >> > This gets things probed correctly. But should you swap back to the PHY >> > clock when the PHY declares the link up? Is there code already to do >> > this? >> > >> > Andrew >> > >> Oh, sorry. I omitted this from the commit message. But the proposed >> emac_reset() code switched to the internal clock only after the first attempt >> has failed AND only for the duration of the reset. >> >> If the reset succeeds or the reset times out, the clock is always switched >> back to the external clock. > > Thanks for the clarification. Maybe add it to the commit message. Indeed, please do.
Hi Christian, [auto build test ERROR on net-next/master] [also build test ERROR on v4.12-rc4 next-20170605] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Christian-Lamparter/net-emac-fix-reset-timeout-with-AR8035-phy/20170606-113953 config: powerpc-allmodconfig (attached as .config) compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=powerpc All errors (new ones prefixed by >>): drivers/net//ethernet/ibm/emac/core.c: In function 'emac_reset': >> drivers/net//ethernet/ibm/emac/core.c:414:4: error: label 'do_retry' used but not defined goto do_retry; ^~~~ vim +/do_retry +414 drivers/net//ethernet/ibm/emac/core.c 408 return 0; 409 } else { 410 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX) && 411 !try_internal_clock) { 412 /* do a retry with the internal clock */ 413 try_internal_clock = true; > 414 goto do_retry; 415 } else { 416 emac_report_timeout_error(dev, "reset timeout"); 417 dev->reset_failed = 1; --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/net/ethernet/ibm/emac/core.c b/drivers/net/ethernet/ibm/emac/core.c index 508923f39ccf..18af1116fa1d 100644 --- a/drivers/net/ethernet/ibm/emac/core.c +++ b/drivers/net/ethernet/ibm/emac/core.c @@ -343,6 +343,7 @@ static int emac_reset(struct emac_instance *dev) { struct emac_regs __iomem *p = dev->emacp; int n = 20; + bool try_internal_clock = false; DBG(dev, "reset" NL); @@ -355,6 +356,7 @@ static int emac_reset(struct emac_instance *dev) } #ifdef CONFIG_PPC_DCR_NATIVE +do_retry: /* * PPC460EX/GT Embedded Processor Advanced User's Manual * section 28.10.1 Mode Register 0 (EMACx_MR0) states: @@ -362,10 +364,19 @@ static int emac_reset(struct emac_instance *dev) * of the EMAC. If none is present, select the internal clock * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). * After a soft reset, select the external clock. + * + * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the + * ethernet cable is not attached. This causes the reset to timeout + * and the PHY detection code in emac_init_phy() is unable to + * communicate and detect the AR8035-A PHY. As a result, the emac + * driver bails out early and the user has no ethernet. + * In order to stay compatible with existing configurations, the + * driver will fall back to and switch to the internal clock, after + * the first reset fails. */ if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { - if (dev->phy_address == 0xffffffff && - dev->phy_map == 0xffffffff) { + if (try_internal_clock || (dev->phy_address == 0xffffffff && + dev->phy_map == 0xffffffff)) { /* No PHY: select internal loop clock before reset */ dcri_clrset(SDR0, SDR0_ETH_CFG, 0, SDR0_ETH_CFG_ECS << dev->cell_index); @@ -383,8 +394,8 @@ static int emac_reset(struct emac_instance *dev) #ifdef CONFIG_PPC_DCR_NATIVE if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { - if (dev->phy_address == 0xffffffff && - dev->phy_map == 0xffffffff) { + if (try_internal_clock || (dev->phy_address == 0xffffffff && + dev->phy_map == 0xffffffff)) { /* No PHY: restore external clock source after reset */ dcri_clrset(SDR0, SDR0_ETH_CFG, SDR0_ETH_CFG_ECS << dev->cell_index, 0); @@ -396,9 +407,16 @@ static int emac_reset(struct emac_instance *dev) dev->reset_failed = 0; return 0; } else { - emac_report_timeout_error(dev, "reset timeout"); - dev->reset_failed = 1; - return -ETIMEDOUT; + if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX) && + !try_internal_clock) { + /* do a retry with the internal clock */ + try_internal_clock = true; + goto do_retry; + } else { + emac_report_timeout_error(dev, "reset timeout"); + dev->reset_failed = 1; + return -ETIMEDOUT; + } } }
This patch fixes a problem where the AR8035 PHY can't be detected on an Cisco Meraki MR24, if the ethernet cable is not connected on boot. Russell Senior provided steps to reproduce the issue: |Disconnect ethernet cable, apply power, wait until device has booted, |plug in ethernet, check for interfaces, no eth0 is listed. | |This appears to be a problem during probing of the AR8035 Phy chip. |When ethernet has no link, the phy detection fails, and eth0 is not |created. Plugging ethernet later has no effect, because there is no |interface as far as the kernel is concerned. The relevant part of |the boot log looks like this: |this is the failing case: | |[ 0.876611] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode |[ 0.882532] /plb/opb/ethernet@ef600c00: reset timeout |[ 0.888546] /plb/opb/ethernet@ef600c00: can't find PHY! |and the succeeding case: | |[ 0.876672] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode |[ 0.883952] eth0: EMAC-0 /plb/opb/ethernet@ef600c00, MAC 00:01:.. |[ 0.890822] eth0: found Atheros 8035 Gigabit Ethernet PHY (0x01) Based on the comment and the commit message of commit 23fbb5a87c56 ("emac: Fix EMAC soft reset on 460EX/GT"). This is because the AR8035 PHY of the Meraki MR24 does not provide the TX Clk, if the ethernet cable is not attached. This causes the reset to timeout and the PHY detection code in emac_init_phy() is unable to detect the AR8035 PHY. As a result, the emac driver bails out early and the user has no ethernet. In order to stay compatible with existing configurations, the driver will try the normal reset first and only falls back to to the internal clock, after the first reset fails. If the second reset fails as well, it will give up as before. LEDE-Bug: #687 <https://bugs.lede-project.org/index.php?do=details&task_id=687> Cc: Chris Blake <chrisrblake93@gmail.com> Reported-by: Russell Senior <russell@personaltelco.net> Fixes: 23fbb5a87c56e98 ("emac: Fix EMAC soft reset on 460EX/GT") Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> --- drivers/net/ethernet/ibm/emac/core.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-)