| Message ID | d53b7a9b1bab818536680123136ac58481d959c8.1494415174.git.chunkeey@googlemail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > From: Ram Chandra Jangir <rjangir@codeaurora.org> > > Populate default values for various GPIO functions. > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: John Crispin <john@phrozen.org> > Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Thanks Christian for attempting to forward this, when doing so you should add your sob here. I do however have some comments and requests for changes. @Ram would you be interested in this feedback and be willing to work on getting these additions upstream? Or do you have the ability to do this Christian? Regards, Bjorn > --- > Ram Chandra Jangir has posted this patch as part of a bigger > "add platform support" patch on LEDE-DEV mailing list: > <http://lists.infradead.org/pipermail/lede-dev/2017-April/007106.html> > --- > drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1250 ++++++++++++++++++++++++++++++-- > 1 file changed, 1172 insertions(+), 78 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > index 743d1f458205..7219d1e33c71 100644 > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > @@ -276,16 +276,531 @@ DECLARE_QCA_GPIO_PINS(99); > > > enum ipq4019_functions { > + qca_mux_rmii0_refclk, > + qca_mux_wifi0_rfsilient0, > + qca_mux_wifi1_rfsilient0, > + qca_mux_smart2, > + qca_mux_led4, > + qca_mux_wifi0_cal, > + qca_mux_wifi1_cal, > + qca_mux_wifi_wci0, > + qca_mux_rmii0_dv, > + qca_mux_wifi_wci1, > + qca_mux_rmii1_refclk, > + qca_mux_blsp_spi1, > + qca_mux_led5, > + qca_mux_rmii10, > + qca_mux_led6, > + qca_mux_rmii11, > + qca_mux_led7, > + qca_mux_rmii1_dv, > + qca_mux_led8, > + qca_mux_rmii1_tx, > + qca_mux_aud_pin, > + qca_mux_led9, > + qca_mux_rmii1_rx, > + qca_mux_led10, > + qca_mux_wifi0_rfsilient1, > + qca_mux_wifi1_rfsilient1, > + qca_mux_led11, > + qca_mux_boot7, > + qca_mux_qpic_pad, > + qca_mux_pcie_clk, > + qca_mux_tm_clk0, > + qca_mux_wifi00, > + qca_mux_wifi10, > + qca_mux_mdio1, > + qca_mux_prng_rosc, > + qca_mux_dbg_out, > + qca_mux_tm0, > + qca_mux_wifi01, > + qca_mux_wifi11, > + qca_mux_atest_char3, > + qca_mux_pmu0, > + qca_mux_boot8, > + qca_mux_tm1, > + qca_mux_atest_char2, > + qca_mux_pmu1, > + qca_mux_boot9, > + qca_mux_tm2, > + qca_mux_atest_char1, > + qca_mux_tm_ack, > + qca_mux_wifi03, > + qca_mux_wifi13, > + qca_mux_qpic_pad4, > + qca_mux_atest_char0, > + qca_mux_tm3, > + qca_mux_wifi02, > + qca_mux_wifi12, > + qca_mux_qpic_pad5, > + qca_mux_smart3, > + qca_mux_wcss0_dbg14, > + qca_mux_tm4, > + qca_mux_wifi04, > + qca_mux_wifi14, > + qca_mux_qpic_pad6, > + qca_mux_wcss0_dbg15, > + qca_mux_qdss_tracectl_a, > + qca_mux_boot18, > + qca_mux_tm5, > + qca_mux_qpic_pad7, > + qca_mux_atest_char, > + qca_mux_wcss0_dbg4, > + qca_mux_qdss_traceclk_a, > + qca_mux_boot19, > + qca_mux_tm6, > + qca_mux_wcss0_dbg5, > + qca_mux_qdss_cti_trig_out_a0, > + qca_mux_boot14, > + qca_mux_tm7, > + qca_mux_chip_rst, > + qca_mux_wcss0_dbg6, > + qca_mux_qdss_cti_trig_out_b0, > + qca_mux_boot11, > + qca_mux_tm8, > + qca_mux_wcss0_dbg7, > + qca_mux_wcss1_dbg7, > + qca_mux_boot20, > + qca_mux_tm9, > + qca_mux_qpic_pad1, > + qca_mux_wcss0_dbg8, > + qca_mux_wcss1_dbg8, > + qca_mux_qpic_pad2, > + qca_mux_wcss0_dbg9, > + qca_mux_wcss1_dbg9, > + qca_mux_qpic_pad3, > + qca_mux_wcss0_dbg10, > + qca_mux_wcss1_dbg10, > + qca_mux_qpic_pad0, > + qca_mux_wcss0_dbg11, > + qca_mux_wcss1_dbg11, > + qca_mux_qpic_pad8, > + qca_mux_wcss0_dbg12, > + qca_mux_wcss1_dbg12, > + qca_mux_wifi034, > + qca_mux_wifi134, > + qca_mux_jtag_tdi, > qca_mux_gpio, > + qca_mux_i2s_rx_bclk, > + qca_mux_jtag_tck, > + qca_mux_i2s_rx_fsync, > + qca_mux_jtag_tms, > + qca_mux_i2s_rxd, > + qca_mux_smart0, > + qca_mux_jtag_tdo, > + qca_mux_jtag_rst, > + qca_mux_jtag_trst, > + qca_mux_mdio0, > + qca_mux_wcss0_dbg18, > + qca_mux_wcss1_dbg18, > + qca_mux_qdss_tracedata_a, > + qca_mux_mdc, > + qca_mux_wcss0_dbg19, > + qca_mux_wcss1_dbg19, > qca_mux_blsp_uart1, > + qca_mux_wifi0_uart, > + qca_mux_wifi1_uart, > + qca_mux_smart1, > + qca_mux_wcss0_dbg20, > + qca_mux_wcss1_dbg20, > + qca_mux_wifi0_uart0, > + qca_mux_wifi1_uart0, > + qca_mux_wcss0_dbg21, > + qca_mux_wcss1_dbg21, > qca_mux_blsp_i2c0, > + qca_mux_wcss0_dbg22, > + qca_mux_wcss1_dbg22, > + qca_mux_wcss0_dbg23, > + qca_mux_wcss1_dbg23, > + qca_mux_blsp_spi0, > qca_mux_blsp_i2c1, > + qca_mux_wcss0_dbg24, > + qca_mux_wcss1_dbg24, > + qca_mux_wcss0_dbg25, > + qca_mux_wcss1_dbg25, > + qca_mux_wcss0_dbg26, > + qca_mux_wcss1_dbg26, > + qca_mux_wcss0_dbg, > + qca_mux_wcss1_dbg, > qca_mux_blsp_uart0, > - qca_mux_blsp_spi1, > - qca_mux_blsp_spi0, > + qca_mux_led0, > + qca_mux_wcss0_dbg28, > + qca_mux_wcss1_dbg28, > + qca_mux_led1, > + qca_mux_wcss0_dbg29, > + qca_mux_wcss1_dbg29, > + qca_mux_wifi0_uart1, > + qca_mux_wifi1_uart1, > + qca_mux_wcss0_dbg30, > + qca_mux_wcss1_dbg30, > + qca_mux_wcss0_dbg31, > + qca_mux_wcss1_dbg31, > + qca_mux_i2s_rx_mclk, > + qca_mux_wcss0_dbg16, > + qca_mux_wcss1_dbg16, > + qca_mux_wcss0_dbg17, > + qca_mux_wcss1_dbg17, > + qca_mux_rgmii0, > + qca_mux_sdio0, > + qca_mux_rgmii1, > + qca_mux_sdio1, > + qca_mux_rgmii2, > + qca_mux_i2s_tx_mclk, > + qca_mux_sdio2, > + qca_mux_rgmii3, > + qca_mux_i2s_tx_bclk, > + qca_mux_sdio3, > + qca_mux_rgmii_rx, > + qca_mux_i2s_tx_fsync, > + qca_mux_sdio_clk, > + qca_mux_rgmii_txc, > + qca_mux_i2s_td1, > + qca_mux_sdio_cmd, > + qca_mux_i2s_td2, > + qca_mux_sdio4, > + qca_mux_i2s_td3, > + qca_mux_sdio5, > + qca_mux_audio_pwm0, > + qca_mux_sdio6, > + qca_mux_audio_pwm1, > + qca_mux_wcss0_dbg27, > + qca_mux_wcss1_dbg27, > + qca_mux_sdio7, > + qca_mux_rgmii_rxc, > + qca_mux_audio_pwm2, > + qca_mux_rgmii_tx, > + qca_mux_audio_pwm3, > + qca_mux_boot2, > + qca_mux_i2s_spdif_in, > + qca_mux_i2s_spdif_out, > + qca_mux_rmii00, > + qca_mux_led2, > + qca_mux_rmii01, > + qca_mux_wifi0_wci, > + qca_mux_wifi1_wci, > + qca_mux_boot4, > + qca_mux_rmii0_tx, > + qca_mux_boot5, > + qca_mux_rmii0_rx, > + qca_mux_pcie_clk1, > + qca_mux_led3, > + qca_mux_sdio_cd, > qca_mux_NA, > }; > > +static const char * const rmii0_refclk_groups[] = { > + "gpio40", > +}; > +static const char * const wifi0_rfsilient0_groups[] = { > + "gpio40", > +}; > +static const char * const wifi1_rfsilient0_groups[] = { > + "gpio40", > +}; > +static const char * const smart2_groups[] = { > + "gpio40", "gpio41", "gpio48", "gpio49", > +}; > +static const char * const led4_groups[] = { > + "gpio40", > +}; > +static const char * const wifi0_cal_groups[] = { > + "gpio41", "gpio51", > +}; > +static const char * const wifi1_cal_groups[] = { > + "gpio41", "gpio51", > +}; > +static const char * const wifi_wci0_groups[] = { > + "gpio42", > +}; > +static const char * const rmii0_dv_groups[] = { > + "gpio43", > +}; > +static const char * const wifi_wci1_groups[] = { > + "gpio43", > +}; > +static const char * const rmii1_refclk_groups[] = { > + "gpio44", > +}; > +static const char * const blsp_spi1_groups[] = { > + "gpio44", "gpio45", "gpio46", "gpio47", > +}; > +static const char * const led5_groups[] = { > + "gpio44", > +}; > +static const char * const rmii10_groups[] = { > + "gpio45", "gpio50", > +}; > +static const char * const led6_groups[] = { > + "gpio45", > +}; > +static const char * const rmii11_groups[] = { > + "gpio46", "gpio51", > +}; > +static const char * const led7_groups[] = { > + "gpio46", > +}; > +static const char * const rmii1_dv_groups[] = { > + "gpio47", > +}; > +static const char * const led8_groups[] = { > + "gpio47", > +}; > +static const char * const rmii1_tx_groups[] = { > + "gpio48", > +}; > +static const char * const aud_pin_groups[] = { > + "gpio48", "gpio49", "gpio50", "gpio51", > +}; > +static const char * const led9_groups[] = { > + "gpio48", > +}; > +static const char * const rmii1_rx_groups[] = { > + "gpio49", > +}; > +static const char * const led10_groups[] = { > + "gpio49", > +}; > +static const char * const wifi0_rfsilient1_groups[] = { > + "gpio50", > +}; > +static const char * const wifi1_rfsilient1_groups[] = { > + "gpio50", > +}; > +static const char * const led11_groups[] = { > + "gpio50", > +}; > +static const char * const boot7_groups[] = { > + "gpio51", > +}; > +static const char * const qpic_pad_groups[] = { > + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio61", "gpio62", > + "gpio63", "gpio69", > +}; > +static const char * const pcie_clk_groups[] = { > + "gpio52", > +}; > +static const char * const tm_clk0_groups[] = { > + "gpio52", > +}; > +static const char * const wifi00_groups[] = { > + "gpio52", > +}; > +static const char * const wifi10_groups[] = { > + "gpio52", > +}; > +static const char * const mdio1_groups[] = { > + "gpio53", > +}; > +static const char * const prng_rosc_groups[] = { > + "gpio53", > +}; > +static const char * const dbg_out_groups[] = { > + "gpio53", > +}; > +static const char * const tm0_groups[] = { > + "gpio53", > +}; > +static const char * const wifi01_groups[] = { > + "gpio53", > +}; > +static const char * const wifi11_groups[] = { > + "gpio53", > +}; > +static const char * const atest_char3_groups[] = { > + "gpio54", > +}; > +static const char * const pmu0_groups[] = { > + "gpio54", > +}; > +static const char * const boot8_groups[] = { > + "gpio54", > +}; > +static const char * const tm1_groups[] = { > + "gpio54", > +}; > +static const char * const atest_char2_groups[] = { > + "gpio55", > +}; > +static const char * const pmu1_groups[] = { > + "gpio55", > +}; > +static const char * const boot9_groups[] = { > + "gpio55", > +}; > +static const char * const tm2_groups[] = { > + "gpio55", > +}; > +static const char * const atest_char1_groups[] = { > + "gpio56", > +}; > +static const char * const tm_ack_groups[] = { > + "gpio56", > +}; > +static const char * const wifi03_groups[] = { > + "gpio56", > +}; > +static const char * const wifi13_groups[] = { > + "gpio56", > +}; > +static const char * const qpic_pad4_groups[] = { > + "gpio57", > +}; > +static const char * const atest_char0_groups[] = { > + "gpio57", > +}; > +static const char * const tm3_groups[] = { > + "gpio57", > +}; > +static const char * const wifi02_groups[] = { > + "gpio57", > +}; > +static const char * const wifi12_groups[] = { > + "gpio57", > +}; > +static const char * const qpic_pad5_groups[] = { > + "gpio58", > +}; > +static const char * const smart3_groups[] = { > + "gpio58", "gpio59", "gpio60", "gpio61", > +}; > +static const char * const wcss0_dbg14_groups[] = { > + "gpio58", > +}; > +static const char * const tm4_groups[] = { > + "gpio58", > +}; > +static const char * const wifi04_groups[] = { > + "gpio58", > +}; > +static const char * const wifi14_groups[] = { > + "gpio58", > +}; > +static const char * const qpic_pad6_groups[] = { > + "gpio59", > +}; > +static const char * const wcss0_dbg15_groups[] = { > + "gpio59", > +}; > +static const char * const qdss_tracectl_a_groups[] = { > + "gpio59", > +}; > +static const char * const boot18_groups[] = { > + "gpio59", > +}; > +static const char * const tm5_groups[] = { > + "gpio59", > +}; > +static const char * const qpic_pad7_groups[] = { > + "gpio60", > +}; > +static const char * const atest_char_groups[] = { > + "gpio60", > +}; > +static const char * const wcss0_dbg4_groups[] = { > + "gpio60", > +}; > +static const char * const qdss_traceclk_a_groups[] = { > + "gpio60", > +}; > +static const char * const boot19_groups[] = { > + "gpio60", > +}; > +static const char * const tm6_groups[] = { > + "gpio60", > +}; > +static const char * const wcss0_dbg5_groups[] = { > + "gpio61", > +}; > +static const char * const qdss_cti_trig_out_a0_groups[] = { > + "gpio61", > +}; > +static const char * const boot14_groups[] = { > + "gpio61", > +}; > +static const char * const tm7_groups[] = { > + "gpio61", > +}; > +static const char * const chip_rst_groups[] = { > + "gpio62", > +}; > +static const char * const wcss0_dbg6_groups[] = { > + "gpio62", > +}; > +static const char * const qdss_cti_trig_out_b0_groups[] = { > + "gpio62", > +}; > +static const char * const boot11_groups[] = { > + "gpio62", > +}; > +static const char * const tm8_groups[] = { > + "gpio62", > +}; > +static const char * const wcss0_dbg7_groups[] = { > + "gpio63", > +}; > +static const char * const wcss1_dbg7_groups[] = { > + "gpio63", > +}; > +static const char * const boot20_groups[] = { > + "gpio63", > +}; > +static const char * const tm9_groups[] = { > + "gpio63", > +}; > +static const char * const qpic_pad1_groups[] = { > + "gpio64", > +}; > +static const char * const wcss0_dbg8_groups[] = { > + "gpio64", > +}; > +static const char * const wcss1_dbg8_groups[] = { > + "gpio64", > +}; > +static const char * const qpic_pad2_groups[] = { > + "gpio65", > +}; > +static const char * const wcss0_dbg9_groups[] = { > + "gpio65", > +}; > +static const char * const wcss1_dbg9_groups[] = { > + "gpio65", > +}; > +static const char * const qpic_pad3_groups[] = { > + "gpio66", > +}; > +static const char * const wcss0_dbg10_groups[] = { > + "gpio66", > +}; > +static const char * const wcss1_dbg10_groups[] = { > + "gpio66", > +}; > +static const char * const qpic_pad0_groups[] = { > + "gpio67", > +}; > +static const char * const wcss0_dbg11_groups[] = { > + "gpio67", > +}; > +static const char * const wcss1_dbg11_groups[] = { > + "gpio67", > +}; > +static const char * const qpic_pad8_groups[] = { > + "gpio68", > +}; > +static const char * const wcss0_dbg12_groups[] = { > + "gpio68", > +}; > +static const char * const wcss1_dbg12_groups[] = { > + "gpio68", > +}; > +static const char * const wifi034_groups[] = { > + "gpio98", > +}; > +static const char * const wifi134_groups[] = { > + "gpio98", > +}; > +static const char * const jtag_tdi_groups[] = { > + "gpio0", > +}; > static const char * const gpio_groups[] = { > "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", > "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", > @@ -303,13 +818,103 @@ static const char * const gpio_groups[] = { > "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", > "gpio99", > }; > - > +static const char * const i2s_rx_bclk_groups[] = { > + "gpio0", "gpio21", "gpio60", > +}; > +static const char * const jtag_tck_groups[] = { > + "gpio1", > +}; > +static const char * const i2s_rx_fsync_groups[] = { > + "gpio1", "gpio22", "gpio61", > +}; > +static const char * const jtag_tms_groups[] = { > + "gpio2", > +}; > +static const char * const i2s_rxd_groups[] = { > + "gpio2", "gpio23", "gpio63", > +}; > +static const char * const smart0_groups[] = { > + "gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46", > + "gpio47", > +}; > +static const char * const jtag_tdo_groups[] = { > + "gpio3", > +}; > +static const char * const jtag_rst_groups[] = { > + "gpio4", > +}; > +static const char * const jtag_trst_groups[] = { > + "gpio5", > +}; > +static const char * const mdio0_groups[] = { > + "gpio6", > +}; > +static const char * const wcss0_dbg18_groups[] = { > + "gpio6", "gpio22", "gpio39", > +}; > +static const char * const wcss1_dbg18_groups[] = { > + "gpio6", "gpio22", "gpio39", > +}; > +static const char * const qdss_tracedata_a_groups[] = { > + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", > + "gpio17", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", > + "gpio43", > +}; > +static const char * const mdc_groups[] = { > + "gpio7", "gpio52", > +}; > +static const char * const wcss0_dbg19_groups[] = { > + "gpio7", "gpio23", "gpio40", > +}; > +static const char * const wcss1_dbg19_groups[] = { > + "gpio7", "gpio23", "gpio40", > +}; > static const char * const blsp_uart1_groups[] = { > "gpio8", "gpio9", "gpio10", "gpio11", > }; > +static const char * const wifi0_uart_groups[] = { > + "gpio8", "gpio9", "gpio11", "gpio19", "gpio62", > +}; > +static const char * const wifi1_uart_groups[] = { > + "gpio8", "gpio11", "gpio19", "gpio62", "gpio63", > +}; > +static const char * const smart1_groups[] = { > + "gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60", > + "gpio61", > +}; > +static const char * const wcss0_dbg20_groups[] = { > + "gpio8", "gpio24", "gpio41", > +}; > +static const char * const wcss1_dbg20_groups[] = { > + "gpio8", "gpio24", "gpio41", > +}; > +static const char * const wifi0_uart0_groups[] = { > + "gpio9", "gpio10", > +}; > +static const char * const wifi1_uart0_groups[] = { > + "gpio9", "gpio10", > +}; > +static const char * const wcss0_dbg21_groups[] = { > + "gpio9", "gpio25", "gpio42", > +}; > +static const char * const wcss1_dbg21_groups[] = { > + "gpio9", "gpio25", "gpio42", > +}; > static const char * const blsp_i2c0_groups[] = { > "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59", > }; > +static const char * const wcss0_dbg22_groups[] = { > + "gpio10", "gpio26", "gpio43", > +}; > +static const char * const wcss1_dbg22_groups[] = { > + "gpio10", "gpio26", "gpio43", > +}; > +static const char * const wcss0_dbg23_groups[] = { > + "gpio11", "gpio27", "gpio44", > +}; > +static const char * const wcss1_dbg23_groups[] = { > + "gpio11", "gpio27", "gpio44", > +}; > static const char * const blsp_spi0_groups[] = { > "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", > "gpio54", "gpio55", "gpio56", "gpio57", > @@ -317,94 +922,582 @@ static const char * const blsp_spi0_groups[] = { > static const char * const blsp_i2c1_groups[] = { > "gpio12", "gpio13", "gpio34", "gpio35", > }; > +static const char * const wcss0_dbg24_groups[] = { > + "gpio12", "gpio28", "gpio45", > +}; > +static const char * const wcss1_dbg24_groups[] = { > + "gpio12", "gpio28", "gpio45", > +}; > +static const char * const wcss0_dbg25_groups[] = { > + "gpio13", "gpio29", "gpio46", > +}; > +static const char * const wcss1_dbg25_groups[] = { > + "gpio13", "gpio29", "gpio46", > +}; > +static const char * const wcss0_dbg26_groups[] = { > + "gpio14", "gpio30", "gpio47", > +}; > +static const char * const wcss1_dbg26_groups[] = { > + "gpio14", "gpio30", "gpio47", > +}; > +static const char * const wcss0_dbg_groups[] = { > + "gpio15", "gpio69", > +}; > +static const char * const wcss1_dbg_groups[] = { > + "gpio15", > +}; > static const char * const blsp_uart0_groups[] = { > "gpio16", "gpio17", "gpio60", "gpio61", > }; > -static const char * const blsp_spi1_groups[] = { > - "gpio44", "gpio45", "gpio46", "gpio47", > +static const char * const led0_groups[] = { > + "gpio16", "gpio36", "gpio60", > +}; > +static const char * const wcss0_dbg28_groups[] = { > + "gpio16", "gpio32", "gpio49", > +}; > +static const char * const wcss1_dbg28_groups[] = { > + "gpio16", "gpio32", "gpio49", > +}; > +static const char * const led1_groups[] = { > + "gpio17", "gpio37", "gpio61", > +}; > +static const char * const wcss0_dbg29_groups[] = { > + "gpio17", "gpio33", "gpio50", > +}; > +static const char * const wcss1_dbg29_groups[] = { > + "gpio17", "gpio33", "gpio50", > +}; > +static const char * const wifi0_uart1_groups[] = { > + "gpio18", "gpio63", > +}; > +static const char * const wifi1_uart1_groups[] = { > + "gpio18", "gpio63", > +}; > +static const char * const wcss0_dbg30_groups[] = { > + "gpio18", "gpio34", "gpio51", > +}; > +static const char * const wcss1_dbg30_groups[] = { > + "gpio18", "gpio34", "gpio51", > +}; > +static const char * const wcss0_dbg31_groups[] = { > + "gpio19", "gpio35", "gpio52", > +}; > +static const char * const wcss1_dbg31_groups[] = { > + "gpio19", "gpio35", > +}; > +static const char * const i2s_rx_mclk_groups[] = { > + "gpio20", "gpio58", > +}; > +static const char * const wcss0_dbg16_groups[] = { > + "gpio20", "gpio37", > +}; > +static const char * const wcss1_dbg16_groups[] = { > + "gpio20", "gpio37", > +}; > +static const char * const wcss0_dbg17_groups[] = { > + "gpio21", "gpio38", > +}; > +static const char * const wcss1_dbg17_groups[] = { > + "gpio21", "gpio38", > +}; > +static const char * const rgmii0_groups[] = { > + "gpio22", "gpio28", > +}; > +static const char * const sdio0_groups[] = { > + "gpio23", > +}; > +static const char * const rgmii1_groups[] = { > + "gpio23", "gpio29", > +}; > +static const char * const sdio1_groups[] = { > + "gpio24", > +}; > +static const char * const rgmii2_groups[] = { > + "gpio24", "gpio30", > +}; > +static const char * const i2s_tx_mclk_groups[] = { > + "gpio24", "gpio52", > +}; > +static const char * const sdio2_groups[] = { > + "gpio25", > +}; > +static const char * const rgmii3_groups[] = { > + "gpio25", "gpio31", > +}; > +static const char * const i2s_tx_bclk_groups[] = { > + "gpio25", "gpio53", "gpio60", > +}; > +static const char * const sdio3_groups[] = { > + "gpio26", > +}; > +static const char * const rgmii_rx_groups[] = { > + "gpio26", > +}; > +static const char * const i2s_tx_fsync_groups[] = { > + "gpio26", "gpio57", "gpio61", > +}; > +static const char * const sdio_clk_groups[] = { > + "gpio27", > +}; > +static const char * const rgmii_txc_groups[] = { > + "gpio27", > +}; > +static const char * const i2s_td1_groups[] = { > + "gpio27", "gpio54", "gpio63", > +}; > +static const char * const sdio_cmd_groups[] = { > + "gpio28", > +}; > +static const char * const i2s_td2_groups[] = { > + "gpio28", "gpio55", > +}; > +static const char * const sdio4_groups[] = { > + "gpio29", > +}; > +static const char * const i2s_td3_groups[] = { > + "gpio29", "gpio56", > +}; > +static const char * const sdio5_groups[] = { > + "gpio30", > +}; > +static const char * const audio_pwm0_groups[] = { > + "gpio30", "gpio64", > +}; > +static const char * const sdio6_groups[] = { > + "gpio31", > +}; > +static const char * const audio_pwm1_groups[] = { > + "gpio31", "gpio65", > +}; > +static const char * const wcss0_dbg27_groups[] = { > + "gpio31", "gpio48", > +}; > +static const char * const wcss1_dbg27_groups[] = { > + "gpio31", "gpio48", > +}; > +static const char * const sdio7_groups[] = { > + "gpio32", > +}; > +static const char * const rgmii_rxc_groups[] = { > + "gpio32", > +}; > +static const char * const audio_pwm2_groups[] = { > + "gpio32", "gpio66", > +}; > +static const char * const rgmii_tx_groups[] = { > + "gpio33", > +}; > +static const char * const audio_pwm3_groups[] = { > + "gpio33", "gpio67", > +}; > +static const char * const boot2_groups[] = { > + "gpio33", > +}; > +static const char * const i2s_spdif_in_groups[] = { > + "gpio34", "gpio59", "gpio63", > +}; > +static const char * const i2s_spdif_out_groups[] = { > + "gpio35", "gpio62", "gpio63", > +}; > +static const char * const rmii00_groups[] = { > + "gpio36", "gpio41", > +}; > +static const char * const led2_groups[] = { > + "gpio36", "gpio38", "gpio58", > +}; > +static const char * const rmii01_groups[] = { > + "gpio37", "gpio42", > +}; > +static const char * const wifi0_wci_groups[] = { > + "gpio37", > +}; > +static const char * const wifi1_wci_groups[] = { > + "gpio37", > +}; > +static const char * const boot4_groups[] = { > + "gpio37", > +}; > +static const char * const rmii0_tx_groups[] = { > + "gpio38", > +}; > +static const char * const boot5_groups[] = { > + "gpio38", > +}; > +static const char * const rmii0_rx_groups[] = { > + "gpio39", > +}; > +static const char * const pcie_clk1_groups[] = { > + "gpio39", > +}; > +static const char * const led3_groups[] = { > + "gpio39", > +}; > +static const char * const sdio_cd_groups[] = { > + "gpio22", > }; > > static const struct msm_function ipq4019_functions[] = { > + FUNCTION(rmii0_refclk), > + FUNCTION(wifi0_rfsilient0), > + FUNCTION(wifi1_rfsilient0), > + FUNCTION(smart2), > + FUNCTION(led4), > + FUNCTION(wifi0_cal), > + FUNCTION(wifi1_cal), > + FUNCTION(wifi_wci0), > + FUNCTION(rmii0_dv), > + FUNCTION(wifi_wci1), > + FUNCTION(rmii1_refclk), > + FUNCTION(blsp_spi1), > + FUNCTION(led5), > + FUNCTION(rmii10), > + FUNCTION(led6), > + FUNCTION(rmii11), > + FUNCTION(led7), > + FUNCTION(rmii1_dv), > + FUNCTION(led8), > + FUNCTION(rmii1_tx), > + FUNCTION(aud_pin), > + FUNCTION(led9), > + FUNCTION(rmii1_rx), > + FUNCTION(led10), > + FUNCTION(wifi0_rfsilient1), > + FUNCTION(wifi1_rfsilient1), > + FUNCTION(led11), > + FUNCTION(boot7), > + FUNCTION(qpic_pad), > + FUNCTION(pcie_clk), > + FUNCTION(tm_clk0), > + FUNCTION(wifi00), > + FUNCTION(wifi10), > + FUNCTION(mdio1), > + FUNCTION(prng_rosc), > + FUNCTION(dbg_out), > + FUNCTION(tm0), > + FUNCTION(wifi01), > + FUNCTION(wifi11), > + FUNCTION(atest_char3), > + FUNCTION(pmu0), > + FUNCTION(boot8), > + FUNCTION(tm1), > + FUNCTION(atest_char2), > + FUNCTION(pmu1), > + FUNCTION(boot9), > + FUNCTION(tm2), > + FUNCTION(atest_char1), > + FUNCTION(tm_ack), > + FUNCTION(wifi03), > + FUNCTION(wifi13), > + FUNCTION(qpic_pad4), > + FUNCTION(atest_char0), > + FUNCTION(tm3), > + FUNCTION(wifi02), > + FUNCTION(wifi12), > + FUNCTION(qpic_pad5), > + FUNCTION(smart3), > + FUNCTION(wcss0_dbg14), > + FUNCTION(tm4), > + FUNCTION(wifi04), > + FUNCTION(wifi14), > + FUNCTION(qpic_pad6), > + FUNCTION(wcss0_dbg15), > + FUNCTION(qdss_tracectl_a), > + FUNCTION(boot18), > + FUNCTION(tm5), > + FUNCTION(qpic_pad7), > + FUNCTION(atest_char), > + FUNCTION(wcss0_dbg4), > + FUNCTION(qdss_traceclk_a), > + FUNCTION(boot19), > + FUNCTION(tm6), > + FUNCTION(wcss0_dbg5), > + FUNCTION(qdss_cti_trig_out_a0), > + FUNCTION(boot14), > + FUNCTION(tm7), > + FUNCTION(chip_rst), > + FUNCTION(wcss0_dbg6), > + FUNCTION(qdss_cti_trig_out_b0), > + FUNCTION(boot11), > + FUNCTION(tm8), > + FUNCTION(wcss0_dbg7), > + FUNCTION(wcss1_dbg7), > + FUNCTION(boot20), > + FUNCTION(tm9), > + FUNCTION(qpic_pad1), > + FUNCTION(wcss0_dbg8), > + FUNCTION(wcss1_dbg8), > + FUNCTION(qpic_pad2), > + FUNCTION(wcss0_dbg9), > + FUNCTION(wcss1_dbg9), > + FUNCTION(qpic_pad3), > + FUNCTION(wcss0_dbg10), > + FUNCTION(wcss1_dbg10), > + FUNCTION(qpic_pad0), > + FUNCTION(wcss0_dbg11), > + FUNCTION(wcss1_dbg11), > + FUNCTION(qpic_pad8), > + FUNCTION(wcss0_dbg12), > + FUNCTION(wcss1_dbg12), > + FUNCTION(wifi034), > + FUNCTION(wifi134), > + FUNCTION(jtag_tdi), > FUNCTION(gpio), > + FUNCTION(i2s_rx_bclk), > + FUNCTION(jtag_tck), > + FUNCTION(i2s_rx_fsync), > + FUNCTION(jtag_tms), > + FUNCTION(i2s_rxd), > + FUNCTION(smart0), > + FUNCTION(jtag_tdo), > + FUNCTION(jtag_rst), > + FUNCTION(jtag_trst), > + FUNCTION(mdio0), > + FUNCTION(wcss0_dbg18), > + FUNCTION(wcss1_dbg18), > + FUNCTION(qdss_tracedata_a), > + FUNCTION(mdc), > + FUNCTION(wcss0_dbg19), > + FUNCTION(wcss1_dbg19), > FUNCTION(blsp_uart1), > + FUNCTION(wifi0_uart), > + FUNCTION(wifi1_uart), > + FUNCTION(smart1), > + FUNCTION(wcss0_dbg20), > + FUNCTION(wcss1_dbg20), > + FUNCTION(wifi0_uart0), > + FUNCTION(wifi1_uart0), > + FUNCTION(wcss0_dbg21), > + FUNCTION(wcss1_dbg21), > FUNCTION(blsp_i2c0), > + FUNCTION(wcss0_dbg22), > + FUNCTION(wcss1_dbg22), > + FUNCTION(wcss0_dbg23), > + FUNCTION(wcss1_dbg23), > + FUNCTION(blsp_spi0), > FUNCTION(blsp_i2c1), > + FUNCTION(wcss0_dbg24), > + FUNCTION(wcss1_dbg24), > + FUNCTION(wcss0_dbg25), > + FUNCTION(wcss1_dbg25), > + FUNCTION(wcss0_dbg26), > + FUNCTION(wcss1_dbg26), > + FUNCTION(wcss0_dbg), > + FUNCTION(wcss1_dbg), > FUNCTION(blsp_uart0), > - FUNCTION(blsp_spi1), > - FUNCTION(blsp_spi0), > + FUNCTION(led0), > + FUNCTION(wcss0_dbg28), > + FUNCTION(wcss1_dbg28), > + FUNCTION(led1), > + FUNCTION(wcss0_dbg29), > + FUNCTION(wcss1_dbg29), > + FUNCTION(wifi0_uart1), > + FUNCTION(wifi1_uart1), > + FUNCTION(wcss0_dbg30), > + FUNCTION(wcss1_dbg30), > + FUNCTION(wcss0_dbg31), > + FUNCTION(wcss1_dbg31), > + FUNCTION(i2s_rx_mclk), > + FUNCTION(wcss0_dbg16), > + FUNCTION(wcss1_dbg16), > + FUNCTION(wcss0_dbg17), > + FUNCTION(wcss1_dbg17), > + FUNCTION(rgmii0), > + FUNCTION(sdio0), > + FUNCTION(rgmii1), > + FUNCTION(sdio1), > + FUNCTION(rgmii2), > + FUNCTION(i2s_tx_mclk), > + FUNCTION(sdio2), > + FUNCTION(rgmii3), > + FUNCTION(i2s_tx_bclk), > + FUNCTION(sdio3), > + FUNCTION(rgmii_rx), > + FUNCTION(i2s_tx_fsync), > + FUNCTION(sdio_clk), > + FUNCTION(rgmii_txc), > + FUNCTION(i2s_td1), > + FUNCTION(sdio_cmd), > + FUNCTION(i2s_td2), > + FUNCTION(sdio4), > + FUNCTION(i2s_td3), > + FUNCTION(sdio5), > + FUNCTION(audio_pwm0), > + FUNCTION(sdio6), > + FUNCTION(audio_pwm1), > + FUNCTION(wcss0_dbg27), > + FUNCTION(wcss1_dbg27), > + FUNCTION(sdio7), > + FUNCTION(rgmii_rxc), > + FUNCTION(audio_pwm2), > + FUNCTION(rgmii_tx), > + FUNCTION(audio_pwm3), > + FUNCTION(boot2), > + FUNCTION(i2s_spdif_in), > + FUNCTION(i2s_spdif_out), > + FUNCTION(rmii00), > + FUNCTION(led2), > + FUNCTION(rmii01), > + FUNCTION(wifi0_wci), > + FUNCTION(wifi1_wci), > + FUNCTION(boot4), > + FUNCTION(rmii0_tx), > + FUNCTION(boot5), > + FUNCTION(rmii0_rx), > + FUNCTION(pcie_clk1), > + FUNCTION(led3), > + FUNCTION(sdio_cd), > }; > > static const struct msm_pingroup ipq4019_groups[] = { > - PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(0, jtag_tdi, smart0, i2s_rx_bclk, NA, NA, NA, NA, NA, NA, NA, > + NA, NA, NA, NA), > + PINGROUP(1, jtag_tck, smart0, i2s_rx_fsync, NA, NA, NA, NA, NA, NA, NA, > + NA, NA, NA, NA), > + PINGROUP(2, jtag_tms, smart0, i2s_rxd, NA, NA, NA, NA, NA, NA, NA, NA, > + NA, NA, NA), > + PINGROUP(3, jtag_tdo, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, > + NA), > + PINGROUP(4, jtag_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, > + NA), > + PINGROUP(5, jtag_trst, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, > + NA, NA), > + PINGROUP(6, mdio0, NA, wcss0_dbg18, wcss1_dbg18, NA, qdss_tracedata_a, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(7, mdc, NA, wcss0_dbg19, wcss1_dbg19, NA, qdss_tracedata_a, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(8, blsp_uart1, wifi0_uart, wifi1_uart, smart1, NA, > + wcss0_dbg20, wcss1_dbg20, NA, qdss_tracedata_a, NA, NA, NA, > + NA, NA), > + PINGROUP(9, blsp_uart1, wifi0_uart0, wifi1_uart0, smart1, wifi0_uart, > + NA, wcss0_dbg21, wcss1_dbg21, NA, qdss_tracedata_a, NA, NA, > + NA, NA), > + PINGROUP(10, blsp_uart1, wifi0_uart0, wifi1_uart0, blsp_i2c0, NA, > + wcss0_dbg22, wcss1_dbg22, NA, qdss_tracedata_a, NA, NA, NA, > + NA, NA), > + PINGROUP(11, blsp_uart1, wifi0_uart, wifi1_uart, blsp_i2c0, NA, > + wcss0_dbg23, wcss1_dbg23, NA, qdss_tracedata_a, NA, NA, NA, > + NA, NA), > + PINGROUP(12, blsp_spi0, blsp_i2c1, NA, wcss0_dbg24, wcss1_dbg24, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(13, blsp_spi0, blsp_i2c1, NA, wcss0_dbg25, wcss1_dbg25, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(14, blsp_spi0, NA, wcss0_dbg26, wcss1_dbg26, NA, NA, NA, NA, > + NA, NA, NA, NA, NA, NA), > + PINGROUP(15, blsp_spi0, NA, wcss0_dbg, wcss1_dbg, NA, NA, NA, NA, NA, > + NA, NA, NA, NA, NA), > + PINGROUP(16, blsp_uart0, led0, smart1, NA, wcss0_dbg28, wcss1_dbg28, > + NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), > + PINGROUP(17, blsp_uart0, led1, smart1, NA, wcss0_dbg29, wcss1_dbg29, > + NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), > + PINGROUP(18, wifi0_uart1, wifi1_uart1, NA, wcss0_dbg30, wcss1_dbg30, > + NA, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(19, wifi0_uart, wifi1_uart, NA, wcss0_dbg31, wcss1_dbg31, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(20, blsp_i2c0, i2s_rx_mclk, NA, wcss0_dbg16, wcss1_dbg16, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(21, blsp_i2c0, i2s_rx_bclk, NA, wcss0_dbg17, wcss1_dbg17, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(22, rgmii0, i2s_rx_fsync, NA, wcss0_dbg18, wcss1_dbg18, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(23, sdio0, rgmii1, i2s_rxd, NA, wcss0_dbg19, wcss1_dbg19, NA, > + NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(24, sdio1, rgmii2, i2s_tx_mclk, NA, wcss0_dbg20, wcss1_dbg20, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(25, sdio2, rgmii3, i2s_tx_bclk, NA, wcss0_dbg21, wcss1_dbg21, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(26, sdio3, rgmii_rx, i2s_tx_fsync, NA, wcss0_dbg22, > + wcss1_dbg22, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(27, sdio_clk, rgmii_txc, i2s_td1, NA, wcss0_dbg23, > + wcss1_dbg23, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(28, sdio_cmd, rgmii0, i2s_td2, NA, wcss0_dbg24, wcss1_dbg24, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(29, sdio4, rgmii1, i2s_td3, NA, wcss0_dbg25, wcss1_dbg25, NA, > + NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(30, sdio5, rgmii2, audio_pwm0, NA, wcss0_dbg26, wcss1_dbg26, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(31, sdio6, rgmii3, audio_pwm1, NA, wcss0_dbg27, wcss1_dbg27, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(32, sdio7, rgmii_rxc, audio_pwm2, NA, wcss0_dbg28, > + wcss1_dbg28, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(33, rgmii_tx, audio_pwm3, NA, wcss0_dbg29, wcss1_dbg29, NA, > + boot2, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, wcss0_dbg30, wcss1_dbg30, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, wcss0_dbg31, wcss1_dbg31, > + NA, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(36, rmii00, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, > + NA, NA), > + PINGROUP(37, rmii01, wifi0_wci, wifi1_wci, led1, NA, NA, wcss0_dbg16, > + wcss1_dbg16, NA, qdss_tracedata_a, boot4, NA, NA, NA), > + PINGROUP(38, rmii0_tx, led2, NA, NA, wcss0_dbg17, wcss1_dbg17, NA, > + qdss_tracedata_a, boot5, NA, NA, NA, NA, NA), > + PINGROUP(39, rmii0_rx, pcie_clk1, led3, NA, NA, wcss0_dbg18, > + wcss1_dbg18, NA, NA, qdss_tracedata_a, NA, NA, NA, NA), > + PINGROUP(40, rmii0_refclk, wifi0_rfsilient0, wifi1_rfsilient0, smart2, > + led4, NA, NA, wcss0_dbg19, wcss1_dbg19, NA, NA, > + qdss_tracedata_a, NA, NA), > + PINGROUP(41, rmii00, wifi0_cal, wifi1_cal, smart2, NA, NA, wcss0_dbg20, > + wcss1_dbg20, NA, NA, qdss_tracedata_a, NA, NA, NA), > + PINGROUP(42, rmii01, wifi_wci0, NA, NA, wcss0_dbg21, wcss1_dbg21, NA, > + NA, qdss_tracedata_a, NA, NA, NA, NA, NA), > + PINGROUP(43, rmii0_dv, wifi_wci1, NA, NA, wcss0_dbg22, wcss1_dbg22, NA, > + NA, qdss_tracedata_a, NA, NA, NA, NA, NA), > + PINGROUP(44, rmii1_refclk, blsp_spi1, smart0, led5, NA, NA, > + wcss0_dbg23, wcss1_dbg23, NA, NA, NA, NA, NA, NA), > + PINGROUP(45, rmii10, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, > + wcss0_dbg24, wcss1_dbg24, NA, NA, NA, NA, NA), > + PINGROUP(46, rmii11, blsp_spi1, smart0, led7, NA, NA, wcss0_dbg25, > + wcss1_dbg25, NA, NA, NA, NA, NA, NA), > + PINGROUP(47, rmii1_dv, blsp_spi1, smart0, led8, NA, NA, wcss0_dbg26, > + wcss1_dbg26, NA, NA, NA, NA, NA, NA), > + PINGROUP(48, rmii1_tx, aud_pin, smart2, led9, NA, NA, wcss0_dbg27, > + wcss1_dbg27, NA, NA, NA, NA, NA, NA), > + PINGROUP(49, rmii1_rx, aud_pin, smart2, led10, NA, NA, wcss0_dbg28, > + wcss1_dbg28, NA, NA, NA, NA, NA, NA), > + PINGROUP(50, rmii10, aud_pin, wifi0_rfsilient1, wifi1_rfsilient1, > + led11, NA, NA, wcss0_dbg29, wcss1_dbg29, NA, NA, NA, NA, NA), > + PINGROUP(51, rmii11, aud_pin, wifi0_cal, wifi1_cal, NA, NA, > + wcss0_dbg30, wcss1_dbg30, NA, boot7, NA, NA, NA, NA), > + PINGROUP(52, qpic_pad, mdc, pcie_clk, i2s_tx_mclk, NA, NA, wcss0_dbg31, > + tm_clk0, wifi00, wifi10, NA, NA, NA, NA), > + PINGROUP(53, qpic_pad, mdio1, i2s_tx_bclk, prng_rosc, dbg_out, tm0, > + wifi01, wifi11, NA, NA, NA, NA, NA, NA), > + PINGROUP(54, qpic_pad, blsp_spi0, i2s_td1, atest_char3, pmu0, NA, NA, > + boot8, tm1, NA, NA, NA, NA, NA), > + PINGROUP(55, qpic_pad, blsp_spi0, i2s_td2, atest_char2, pmu1, NA, NA, > + boot9, tm2, NA, NA, NA, NA, NA), > + PINGROUP(56, qpic_pad, blsp_spi0, i2s_td3, atest_char1, NA, tm_ack, > + wifi03, wifi13, NA, NA, NA, NA, NA, NA), > + PINGROUP(57, qpic_pad4, blsp_spi0, i2s_tx_fsync, atest_char0, NA, tm3, > + wifi02, wifi12, NA, NA, NA, NA, NA, NA), > + PINGROUP(58, qpic_pad5, led2, blsp_i2c0, smart3, smart1, i2s_rx_mclk, > + NA, wcss0_dbg14, tm4, wifi04, wifi14, NA, NA, NA), > + PINGROUP(59, qpic_pad6, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, > + NA, wcss0_dbg15, qdss_tracectl_a, boot18, tm5, NA, NA, NA), > + PINGROUP(60, qpic_pad7, blsp_uart0, smart1, smart3, led0, i2s_tx_bclk, > + i2s_rx_bclk, atest_char, NA, wcss0_dbg4, qdss_traceclk_a, > + boot19, tm6, NA), > + PINGROUP(61, qpic_pad, blsp_uart0, smart1, smart3, led1, i2s_tx_fsync, > + i2s_rx_fsync, NA, NA, wcss0_dbg5, qdss_cti_trig_out_a0, > + boot14, tm7, NA), > + PINGROUP(62, qpic_pad, chip_rst, wifi0_uart, wifi1_uart, i2s_spdif_out, > + NA, NA, wcss0_dbg6, qdss_cti_trig_out_b0, boot11, tm8, NA, NA, > + NA), > + PINGROUP(63, qpic_pad, wifi0_uart1, wifi1_uart1, wifi1_uart, i2s_td1, > + i2s_rxd, i2s_spdif_out, i2s_spdif_in, NA, wcss0_dbg7, > + wcss1_dbg7, boot20, tm9, NA), > + PINGROUP(64, qpic_pad1, audio_pwm0, NA, wcss0_dbg8, wcss1_dbg8, NA, NA, > + NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(65, qpic_pad2, audio_pwm1, NA, wcss0_dbg9, wcss1_dbg9, NA, NA, > + NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(66, qpic_pad3, audio_pwm2, NA, wcss0_dbg10, wcss1_dbg10, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(67, qpic_pad0, audio_pwm3, NA, wcss0_dbg11, wcss1_dbg11, NA, > + NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(68, qpic_pad8, NA, wcss0_dbg12, wcss1_dbg12, NA, NA, NA, NA, > + NA, NA, NA, NA, NA, NA), > + PINGROUP(69, qpic_pad, NA, wcss0_dbg, NA, NA, NA, NA, NA, NA, NA, NA, > + NA, NA, NA), > PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > @@ -433,7 +1526,8 @@ static const struct msm_pingroup ipq4019_groups[] = { > PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > - PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > + PINGROUP(98, wifi034, wifi134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, > + NA, NA), > PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), > }; > > -- > 2.11.0 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, May 10, 2017 at 01:27:10PM +0200, Christian Lamparter wrote: > This patch adds the remaining pin functions and mux groups. > It also fixes a typo in the existing binding document. > > Cc: Varadarajan Narayanan <varada@codeaurora.org> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Ram Chandra Jangir <rjangir@codeaurora.org> > Cc: John Crispin <john@phrozen.org> > Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> > --- > --- > .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt | 36 ++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > index 743d1f458205..7219d1e33c71 100644 > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > @@ -276,16 +276,531 @@ DECLARE_QCA_GPIO_PINS(99); > > > enum ipq4019_functions { Please sort these alphabetically - and the following two lists accordingly. > + qca_mux_rmii0_refclk, > + qca_mux_wifi0_rfsilient0, > + qca_mux_wifi1_rfsilient0, > + qca_mux_smart2, > + qca_mux_led4, What drives ledX? Is it 11 different LED controllers or is it a single LED controller with 11 outputs. [..] > + qca_mux_wifi01, Please make these "wifi0" and include all "wifi0XY", rather than having a group per pin. > + qca_mux_wifi11, "wifi1" > + qca_mux_atest_char3, > + qca_mux_pmu0, > + qca_mux_boot8, > + qca_mux_tm1, > + qca_mux_atest_char2, > + qca_mux_pmu1, > + qca_mux_boot9, > + qca_mux_tm2, > + qca_mux_atest_char1, > + qca_mux_tm_ack, > + qca_mux_wifi03, > + qca_mux_wifi13, > + qca_mux_qpic_pad4, Please keep an eye on the ipq8074 patch from Varadarajan and make this follow the same scheme. > + qca_mux_atest_char0, > + qca_mux_tm3, > + qca_mux_wifi02, > + qca_mux_wifi12, > + qca_mux_qpic_pad5, > + qca_mux_smart3, > + qca_mux_wcss0_dbg14, Please squash these into "wcss0_dbg" > + qca_mux_tm4, > + qca_mux_wifi04, > + qca_mux_wifi14, > + qca_mux_qpic_pad6, > + qca_mux_wcss0_dbg15, > + qca_mux_qdss_tracectl_a, > + qca_mux_boot18, Do you know what the "boot" function is and what 2, 4, 5, 7, 8, 9 11, 14, 18, 19 and 20 means? [..] > + qca_mux_sdio0, There are 8 of these, so that's more likely the 8 data pins in a single function. Please squash them into "sdio_data". Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wednesday, May 17, 2017 1:07:29 PM CEST Bjorn Andersson wrote: > On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > index 743d1f458205..7219d1e33c71 100644 > > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > + qca_mux_rmii0_refclk, > > + qca_mux_wifi0_rfsilient0, > > + qca_mux_wifi1_rfsilient0, > > + qca_mux_smart2, > > + qca_mux_led4, > > What drives ledX? Is it 11 different LED controllers or is it a single > LED controller with 11 outputs. The latter. The IPQ40xx have one LED controller @ 0x1937000. According to the driver (leds-ipq40xx.c in the SDK), it does control up to 11 LEDs. A LED can either be muxed to one of the hardware sources (wifi, lan or wan-ports activity/linkspeed), or it can be operated by one of four software-programmable "blink" sources (each with a variable blink rate and duty cycle). The driver labels each LED as "ipq40xx::led%d". That said: ASUS, Cisco, Compex, Netgear, Zyxel... opted to either 1. export the individual GPIOs with sysfs 2. gpio-leds > [..] > > + qca_mux_wifi01, > > Please make these "wifi0" and include all "wifi0XY", rather than having > a group per pin. > > > + qca_mux_wifi11, > > "wifi1" Ok. Can I leave wifi1_cal, _wci, uartX... the way they are? > > + qca_mux_atest_char3, > > + qca_mux_pmu0, > > + qca_mux_boot8, > > + qca_mux_tm1, > > + qca_mux_atest_char2, > > + qca_mux_pmu1, > > + qca_mux_boot9, > > + qca_mux_tm2, > > + qca_mux_atest_char1, > > + qca_mux_tm_ack, > > + qca_mux_wifi03, > > + qca_mux_wifi13, > > + qca_mux_qpic_pad4, > > Please keep an eye on the ipq8074 patch from Varadarajan and make this > follow the same scheme. Ok, I'll wait for how qca8074 plays out then. By the way, can you ask if the QCA8074 follows the IPQ40XX SoC's GPIO Pull-up config? I'm asking because Varadarajan was also involved in the pinctrl-ipq4019 back in 2015: <https://patchwork.kernel.org/patch/7662241/> Back then, this wasn't mentioned anywhere. In fact, the special pull-up configuration was only discovered due to an issue with the NAND on the Cisco Meraki MR33. So I think it is better ask them now, when the devs are actually present/responding. > > + qca_mux_atest_char0, > > + qca_mux_tm3, > > + qca_mux_wifi02, > > + qca_mux_wifi12, > > + qca_mux_qpic_pad5, > > + qca_mux_smart3, > > + qca_mux_wcss0_dbg14, > > Please squash these into "wcss0_dbg" Ok. > > + qca_mux_tm4, > > + qca_mux_wifi04, > > + qca_mux_wifi14, > > + qca_mux_qpic_pad6, > > + qca_mux_wcss0_dbg15, > > + qca_mux_qdss_tracectl_a, > > + qca_mux_boot18, > > Do you know what the "boot" function is and what 2, 4, 5, 7, 8, 9 11, > 14, 18, 19 and 20 means? Sadly no. That said, neither the u-boot nor the linux kernel sources set any pin to bootX. I think I'll remove it for now. > [..] > > + qca_mux_sdio0, > > There are 8 of these, so that's more likely the 8 data pins in a single > function. Please squash them into "sdio_data". Yes, this is very likely. We know that this is the case for the qpic_padX. Regards, Christian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu 18 May 11:38 PDT 2017, Christian Lamparter wrote: > On Wednesday, May 17, 2017 1:07:29 PM CEST Bjorn Andersson wrote: > > On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > index 743d1f458205..7219d1e33c71 100644 > > > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > + qca_mux_rmii0_refclk, > > > + qca_mux_wifi0_rfsilient0, > > > + qca_mux_wifi1_rfsilient0, > > > + qca_mux_smart2, > > > + qca_mux_led4, > > > > What drives ledX? Is it 11 different LED controllers or is it a single > > LED controller with 11 outputs. > > The latter. The IPQ40xx have one LED controller @ 0x1937000. > According to the driver (leds-ipq40xx.c in the SDK), it > does control up to 11 LEDs. A LED can either be muxed to > one of the hardware sources (wifi, lan or wan-ports activity/linkspeed), > or it can be operated by one of four software-programmable "blink" > sources (each with a variable blink rate and duty cycle). > The driver labels each LED as "ipq40xx::led%d". > As they all stem from the same hardware block I suggest we name the function "led". > That said: ASUS, Cisco, Compex, Netgear, Zyxel... opted to either > 1. export the individual GPIOs with sysfs > 2. gpio-leds > For any software-driven LED control it makes sense to configure the pins as gpio and just rely on the gpio-leds driver. But as you have both hardware driven control and hardware blink support it sounds like there's good reason to have a specific LED driver as well. > > [..] > > > + qca_mux_wifi01, > > > > Please make these "wifi0" and include all "wifi0XY", rather than having > > a group per pin. > > > > > + qca_mux_wifi11, > > > > "wifi1" > > Ok. Can I leave wifi1_cal, _wci, uartX... the way they are? > Yes, that sounds reasonable > > > + qca_mux_atest_char3, > > > + qca_mux_pmu0, > > > + qca_mux_boot8, > > > + qca_mux_tm1, > > > + qca_mux_atest_char2, > > > + qca_mux_pmu1, > > > + qca_mux_boot9, > > > + qca_mux_tm2, > > > + qca_mux_atest_char1, > > > + qca_mux_tm_ack, > > > + qca_mux_wifi03, > > > + qca_mux_wifi13, > > > + qca_mux_qpic_pad4, > > > > Please keep an eye on the ipq8074 patch from Varadarajan and make this > > follow the same scheme. > Ok, I'll wait for how qca8074 plays out then. > By the way, can you ask if the QCA8074 follows the IPQ40XX SoC's > GPIO Pull-up config? > > I'm asking because Varadarajan was also involved in the > pinctrl-ipq4019 back in 2015: <https://patchwork.kernel.org/patch/7662241/> > > Back then, this wasn't mentioned anywhere. In fact, the special pull-up > configuration was only discovered due to an issue with the NAND on the > Cisco Meraki MR33. So I think it is better ask them now, when the devs > are actually present/responding. > I do unfortunately not have access to the specification or either platform, I would appreciate if you could post a reply on Varadarajan's IPQ8074 patch asking him to verify the layout of the config register. [..] > > > + qca_mux_boot18, > > > > Do you know what the "boot" function is and what 2, 4, 5, 7, 8, 9 11, > > 14, 18, 19 and 20 means? > Sadly no. That said, neither the u-boot nor the linux kernel > sources set any pin to bootX. I think I'll remove it for now. > Better leave them out for now then. > > [..] > > > + qca_mux_sdio0, > > > > There are 8 of these, so that's more likely the 8 data pins in a single > > function. Please squash them into "sdio_data". > Yes, this is very likely. We know that this is the case for the qpic_padX. > Sounds good. Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Friday, May 19, 2017 10:08:24 PM CEST Bjorn Andersson wrote: > On Thu 18 May 11:38 PDT 2017, Christian Lamparter wrote: > > On Wednesday, May 17, 2017 1:07:29 PM CEST Bjorn Andersson wrote: > > > On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > index 743d1f458205..7219d1e33c71 100644 > > > > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > + qca_mux_rmii0_refclk, > > > > + qca_mux_wifi0_rfsilient0, > > > > + qca_mux_wifi1_rfsilient0, > > > > + qca_mux_smart2, > > > > + qca_mux_led4, > > > > > > What drives ledX? Is it 11 different LED controllers or is it a single > > > LED controller with 11 outputs. > > > > The latter. The IPQ40xx have one LED controller @ 0x1937000. > > According to the driver (leds-ipq40xx.c in the SDK), it > > does control up to 11 LEDs. A LED can either be muxed to > > one of the hardware sources (wifi, lan or wan-ports activity/linkspeed), > > or it can be operated by one of four software-programmable "blink" > > sources (each with a variable blink rate and duty cycle). > > The driver labels each LED as "ipq40xx::led%d". > > > > As they all stem from the same hardware block I suggest we name the > function "led". This is going to be a problem for Pin 36: PINGROUP(36, rmii0, *led2*, *led0*, NA, ...) I checked the other pins too, but this seems to be the only time two LED-lines share the same pin. What's the recommended/prefered option in this case? Something like led_alt, or should I keep the led0-led11? There are a few more collisions with other functions as well: smartX, i2s_*, wifi1_uart*: PINGROUP(58, qpic, led2, blsp_i2c0, *smart3*, *smart1*, i2s_rx_mclk, NA, wcss0_dbg, tm4, wifi0, wifi1, NA, NA, NA), PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, *i2s_tx_bclk*, *i2s_rx_bclk*, atest_char, NA, wcss0_dbg, qdss_traceclk_a, NA, tm6, NA), PINGROUP(61, qpic, blsp_uart0, *smart1*, *smart3*, led1, *i2s_tx_fsync*, *i2s_rx_fsync*, NA, NA, wcss0_dbg, qdss_cti_trig_out_a0, NA, tm7, NA), PINGROUP(63, qpic, wifi0_uart1, *wifi1_uart1*, *wifi1_uart*, *i2s_td1*, *i2s_rxd*, *i2s_spdif_out*, *i2s_spdif_in*, NA, wcss0_dbg, wcss1_dbg, NA, tm, NA), ... > > > > + qca_mux_qpic_pad4, > > > > > > Please keep an eye on the ipq8074 patch from Varadarajan and make this > > > follow the same scheme. > > Ok, I'll wait for how qca8074 plays out then. <https://www.spinics.net/lists/arm-kernel/msg582958.html>: | On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson wrote: | [...] | > If you consider that you are defining the available functions for this | > pinmuxer and then define the sets of pins exposing these available | > functions it does make sense to just name it "qpic". | > | > I think that naming them _common, _lcd and _nand is just adding | > confusion when it comes to writing the dts files. | > | > @Linus, do you have a different preference here? | |No I pretty much trust the driver maintainer to know this best. | |Yours, |Linus Walleij Thanks for the answer, I'll go with "qpic" then. I'll also combine the various sdio_* to sdio and look at the other candidates (rgmii*, rmii0/1*, pmuX, pcie_clk*, jtag*, tmX, audio_pwmX). Unless someone comes up with a good reason not to. Regards, Christian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue 23 May 09:58 PDT 2017, Christian Lamparter wrote: > On Friday, May 19, 2017 10:08:24 PM CEST Bjorn Andersson wrote: > > On Thu 18 May 11:38 PDT 2017, Christian Lamparter wrote: > > > On Wednesday, May 17, 2017 1:07:29 PM CEST Bjorn Andersson wrote: > > > > On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > index 743d1f458205..7219d1e33c71 100644 > > > > > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > + qca_mux_rmii0_refclk, > > > > > + qca_mux_wifi0_rfsilient0, > > > > > + qca_mux_wifi1_rfsilient0, > > > > > + qca_mux_smart2, > > > > > + qca_mux_led4, > > > > > > > > What drives ledX? Is it 11 different LED controllers or is it a single > > > > LED controller with 11 outputs. > > > > > > The latter. The IPQ40xx have one LED controller @ 0x1937000. > > > According to the driver (leds-ipq40xx.c in the SDK), it > > > does control up to 11 LEDs. A LED can either be muxed to > > > one of the hardware sources (wifi, lan or wan-ports activity/linkspeed), > > > or it can be operated by one of four software-programmable "blink" > > > sources (each with a variable blink rate and duty cycle). > > > The driver labels each LED as "ipq40xx::led%d". > > > > > > > As they all stem from the same hardware block I suggest we name the > > function "led". > > This is going to be a problem for Pin 36: > > PINGROUP(36, rmii0, *led2*, *led0*, NA, ...) > > I checked the other pins too, but this seems to be the only time two > LED-lines share the same pin. What's the recommended/prefered option > in this case? Something like led_alt, or should I keep the led0-led11? > > There are a few more collisions with other functions as well: > smartX, i2s_*, wifi1_uart*: > Looks like we're stuck with individually named functions for these then... > PINGROUP(58, qpic, led2, blsp_i2c0, *smart3*, *smart1*, > i2s_rx_mclk, NA, wcss0_dbg, tm4, wifi0, wifi1, NA, NA, NA), > > PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, > *i2s_tx_bclk*, *i2s_rx_bclk*, atest_char, NA, wcss0_dbg, > qdss_traceclk_a, NA, tm6, NA), > > PINGROUP(61, qpic, blsp_uart0, *smart1*, *smart3*, led1, *i2s_tx_fsync*, > *i2s_rx_fsync*, NA, NA, wcss0_dbg, qdss_cti_trig_out_a0, > NA, tm7, NA), > > PINGROUP(63, qpic, wifi0_uart1, *wifi1_uart1*, *wifi1_uart*, *i2s_td1*, > *i2s_rxd*, *i2s_spdif_out*, *i2s_spdif_in*, NA, wcss0_dbg, > wcss1_dbg, NA, tm, NA), > ... This makes me wonder what wifi1_uart (and uart1) actually is... The wifi\d_uart seems to have 5 pins in its group and wifi\d_uart\d seems to be two sets of two pins. So perhaps this is some alternative routing and wifi0_uart0 and wifi0_uart1 is actually the same function? @Ram, can you help us out here? > > > > > + qca_mux_qpic_pad4, > > > > > > > > Please keep an eye on the ipq8074 patch from Varadarajan and make this > > > > follow the same scheme. > > > Ok, I'll wait for how qca8074 plays out then. > > <https://www.spinics.net/lists/arm-kernel/msg582958.html>: > | On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson wrote: > | [...] > | > If you consider that you are defining the available functions for this > | > pinmuxer and then define the sets of pins exposing these available > | > functions it does make sense to just name it "qpic". > | > > | > I think that naming them _common, _lcd and _nand is just adding > | > confusion when it comes to writing the dts files. > | > > | > @Linus, do you have a different preference here? > | > |No I pretty much trust the driver maintainer to know this best. > | > |Yours, > |Linus Walleij > > Thanks for the answer, I'll go with "qpic" then. > I'll also combine the various sdio_* to sdio and look at the other candidates > (rgmii*, rmii0/1*, pmuX, pcie_clk*, jtag*, tmX, audio_pwmX). Unless someone > comes up with a good reason not to. > Sounds good! Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wednesday, May 24, 2017 12:59 AM CEST Bjorn Andersson wrote: >On Tue 23 May 09:58 PDT 2017, Christian Lamparter wrote: > On Friday, May 19, 2017 10:08:24 PM CEST Bjorn Andersson wrote: > > On Thu 18 May 11:38 PDT 2017, Christian Lamparter wrote: > > > On Wednesday, May 17, 2017 1:07:29 PM CEST Bjorn Andersson wrote: > > > > On Wed 10 May 04:27 PDT 2017, Christian Lamparter wrote: > > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > index 743d1f458205..7219d1e33c71 100644 > > > > > --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c > > > > > + qca_mux_rmii0_refclk, > > > > > + qca_mux_wifi0_rfsilient0, > > > > > + qca_mux_wifi1_rfsilient0, > > > > > + qca_mux_smart2, > > > > > + qca_mux_led4, > > > > > > > > What drives ledX? Is it 11 different LED controllers or is it a > > > > single LED controller with 11 outputs. > > > > > > The latter. The IPQ40xx have one LED controller @ 0x1937000. > > > According to the driver (leds-ipq40xx.c in the SDK), it does > > > control up to 11 LEDs. A LED can either be muxed to one of the > > > hardware sources (wifi, lan or wan-ports activity/linkspeed), or > > > it can be operated by one of four software-programmable "blink" > > > sources (each with a variable blink rate and duty cycle). > > > The driver labels each LED as "ipq40xx::led%d". > > > > > > > As they all stem from the same hardware block I suggest we name the > > function "led". > > This is going to be a problem for Pin 36: > > PINGROUP(36, rmii0, *led2*, *led0*, NA, ...) > > I checked the other pins too, but this seems to be the only time two > LED-lines share the same pin. What's the recommended/prefered option > in this case? Something like led_alt, or should I keep the led0-led11? > > There are a few more collisions with other functions as well: > smartX, i2s_*, wifi1_uart*: > >Looks like we're stuck with individually named functions for these then... > PINGROUP(58, qpic, led2, blsp_i2c0, *smart3*, *smart1*, > i2s_rx_mclk, NA, wcss0_dbg, tm4, wifi0, wifi1, NA, NA, NA), > > PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, > *i2s_tx_bclk*, *i2s_rx_bclk*, atest_char, NA, wcss0_dbg, > qdss_traceclk_a, NA, tm6, NA), > > PINGROUP(61, qpic, blsp_uart0, *smart1*, *smart3*, led1, *i2s_tx_fsync*, > *i2s_rx_fsync*, NA, NA, wcss0_dbg, qdss_cti_trig_out_a0, > NA, tm7, NA), > > PINGROUP(63, qpic, wifi0_uart1, *wifi1_uart1*, *wifi1_uart*, *i2s_td1*, > *i2s_rxd*, *i2s_spdif_out*, *i2s_spdif_in*, NA, wcss0_dbg, > wcss1_dbg, NA, tm, NA), > ... >This makes me wonder what wifi1_uart (and uart1) actually is... >The wifi\d_uart seems to have 5 pins in its group and wifi\d_uart\d seems to be two sets of two pins. So perhaps this is some alternative routing and wifi0_uart0 and wifi0_uart1 is actually the same function? >@Ram, can you help us out here? wifi0_uart0 and wifi0_uart1 are different functions, and they are mapped as below: wifi0_uart --> wifi0 uart RTS wifi0_uart0 --> wifi0 uart RxD wifi0_uart1 --> wifi0 uart CTS wifi1_uart --> wifi1 uart TxD wifi1_uart0 --> wifi1 uart RxD wifi1_uart1 --> wifi1 uart CTS Thanks, Ram > > > > > + qca_mux_qpic_pad4, > > > > > > > > Please keep an eye on the ipq8074 patch from Varadarajan and > > > > make this follow the same scheme. > > > Ok, I'll wait for how qca8074 plays out then. > > <https://www.spinics.net/lists/arm-kernel/msg582958.html>: > | On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson wrote: > | [...] > | > If you consider that you are defining the available functions for > | > this pinmuxer and then define the sets of pins exposing these > | > available functions it does make sense to just name it "qpic". > | > > | > I think that naming them _common, _lcd and _nand is just adding > | > confusion when it comes to writing the dts files. > | > > | > @Linus, do you have a different preference here? > | > |No I pretty much trust the driver maintainer to know this best. > | > |Yours, > |Linus Walleij > > Thanks for the answer, I'll go with "qpic" then. > I'll also combine the various sdio_* to sdio and look at the other > candidates (rgmii*, rmii0/1*, pmuX, pcie_clk*, jtag*, tmX, > audio_pwmX). Unless someone comes up with a good reason not to. > >Sounds good! >Regards, >Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed 24 May 06:04 PDT 2017, Ram Chandra Jangir wrote: > > > On Wednesday, May 24, 2017 12:59 AM CEST Bjorn Andersson wrote: [..] > >This makes me wonder what wifi1_uart (and uart1) actually is... > > >The wifi\d_uart seems to have 5 pins in its group and wifi\d_uart\d seems > to be two sets of two pins. So perhaps this is some alternative routing and > wifi0_uart0 and wifi0_uart1 is actually the same function? > > >@Ram, can you help us out here? > Ram, thanks for your answer. Unfortunately I missed this mail until Christian posted the new version of the patch. Unfortunately I don't understand the functions provided here, so I hope you can help me better understand what's going on. > wifi0_uart0 and wifi0_uart1 are different functions, and they are mapped as > below: > wifi0_uart --> wifi0 uart RTS > wifi0_uart0 --> wifi0 uart RxD > wifi0_uart1 --> wifi0 uart CTS Christian has the following groups of pins for each function: wifi0_uart: pin 8, 9, 11, 19 and 62 wifi0_uart0: pin 9 and 10 wifi0_uart1: pin 18 and 63 It's common to see alternative muxing of functions, so I'm guessing that wifi0_uart1 is one of these. Is this correct? But why is there 5 pins for RTS? Why is receive (wifi0_uart0) two adjacent pins? Are they perhaps Rx and Tx? Why do we have a CTS line if we only have RxD, no TxD? > > wifi1_uart --> wifi1 uart TxD > wifi1_uart0 --> wifi1 uart RxD > wifi1_uart1 --> wifi1 uart CTS > Why is there no RTS for this when it seems bidirectional? Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wednesday, July 5, 2017 11:02:43 PM CEST Bjorn Andersson wrote: > On Wed 24 May 06:04 PDT 2017, Ram Chandra Jangir wrote: > > On Wednesday, May 24, 2017 12:59 AM CEST Bjorn Andersson wrote: > [..] > > >This makes me wonder what wifi1_uart (and uart1) actually is... > > > > >The wifi\d_uart seems to have 5 pins in its group and wifi\d_uart\d seems > > to be two sets of two pins. So perhaps this is some alternative routing and > > wifi0_uart0 and wifi0_uart1 is actually the same function? > > > > >@Ram, can you help us out here? > > > > Ram, thanks for your answer. Unfortunately I missed this mail until > Christian posted the new version of the patch. > > Unfortunately I don't understand the functions provided here, so I hope > you can help me better understand what's going on. > > > wifi0_uart0 and wifi0_uart1 are different functions, and they are mapped as > > below: > > wifi0_uart --> wifi0 uart RTS > > wifi0_uart0 --> wifi0 uart RxD > > wifi0_uart1 --> wifi0 uart CTS > > Christian has the following groups of pins for each function: > > wifi0_uart: pin 8, 9, 11, 19 and 62 > wifi0_uart0: pin 9 and 10 > wifi0_uart1: pin 18 and 63 > > It's common to see alternative muxing of functions, so I'm guessing that > wifi0_uart1 is one of these. Is this correct? > > But why is there 5 pins for RTS? > > Why is receive (wifi0_uart0) two adjacent pins? Are they perhaps Rx and > Tx? > > Why do we have a CTS line if we only have RxD, no TxD? > > > > > wifi1_uart --> wifi1 uart TxD > > wifi1_uart0 --> wifi1 uart RxD > > wifi1_uart1 --> wifi1 uart CTS > > > > Why is there no RTS for this when it seems bidirectional? no response in over a week. :-/ I removed the wifi*_uart* definitions in V3. I think we can life without them. If QCA ever releases the firmware code to the public, they would be of some use but until them, we can do without. Regards, Christian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt index cfb8500dd56b..4b1c583c51e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt @@ -39,7 +39,7 @@ information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: - pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength. + pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength. Non-empty subnodes must specify the 'pins' property. Note that not all properties are valid for all pins. @@ -50,7 +50,39 @@ Valid values for qcom,pins are: Supports mux, bias and drive-strength Valid values for qcom,function are: -gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0 +gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0, +atest_char, atest_char0, atest_char1, atest_char2, atest_char3, +audio_pwm0, audio_pwm1, audio_pwm2, audio_pwm3, aud_pin, +boot2, boot4, boot5, boot7, boot8, boot9, boot11, boot14, boot18, boot19, boot20, +chip_rst, dbg_out, mdc, mdio0, mdio1, pcie_clk, pcie_clk1, +i2s_rx_bclk, i2s_rxd, i2s_rx_fsync, i2s_rx_mclk, i2s_spdif_in, i2s_spdif_out, +i2s_td1, i2s_td2, i2s_td3, i2s_tx_bclk, i2s_tx_fsync, i2s_tx_mclk, +jtag_rst, jtag_tck, jtag_tdi, jtag_tdo, jtag_tms, jtag_trst, +led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11, +qdss_cti_trig_out_a0, qdss_cti_trig_out_b0, qdss_traceclk_a, +qdss_tracectl_a, qdss_tracedata_a, pmu0, pmu1, prng_rosc, +qpic_pad, qpic_pad0, qpic_pad1, qpic_pad2, qpic_pad3, +qpic_pad4, qpic_pad5, qpic_pad6, qpic_pad7, qpic_pad8, +rgmii0, rgmii1, rgmii2, rgmii3, rgmii_rx, rgmii_rxc, rgmii_tx, rgmii_txc, +rmii00, rmii01, rmii0_dv, rmii0_refclk, rmii0_rx, rmii0_tx, +rmii10, rmii11, rmii1_dv, rmii1_refclk, rmii1_rx, rmii1_tx, +sdio0, sdio1, sdio2, sdio3, sdio4, sdio5, sdio6, sdio7, sdio_cd, +sdio_clk, sdio_cmd, smart0, smart1, smart2, smart3, +tm0, tm1, tm2, tm3, tm4, tm5, tm6, tm7, tm8, tm9, tm_ack, tm_clk0, +wcss0_dbg, wcss0_dbg4, wcss0_dbg5, wcss0_dbg6, wcss0_dbg7, wcss0_dbg8, +wcss0_dbg9, wcss0_dbg10, wcss0_dbg11, wcss0_dbg12, wcss0_dbg14, wcss0_dbg15, +wcss0_dbg16, wcss0_dbg17, wcss0_dbg18, wcss0_dbg19, wcss0_dbg20, wcss0_dbg21, +wcss0_dbg22, wcss0_dbg23, wcss0_dbg24, wcss0_dbg25, wcss0_dbg26, wcss0_dbg27, +wcss0_dbg28, wcss0_dbg29, wcss0_dbg30, wcss0_dbg31, +wcss1_dbg, wcss1_dbg7, wcss1_dbg8, wcss1_dbg9, wcss1_dbg10, wcss1_dbg11, +wcss1_dbg12, wcss1_dbg16, wcss1_dbg17, wcss1_dbg18, wcss1_dbg19, wcss1_dbg20, +wcss1_dbg21, wcss1_dbg22, wcss1_dbg23, wcss1_dbg24, wcss1_dbg25, wcss1_dbg26, +wcss1_dbg27, wcss1_dbg28, wcss1_dbg29, wcss1_dbg30, wcss1_dbg31, +wifi00, wifi01, wifi02, wifi03, wifi04, wifi034, wifi0_cal, wifi0_rfsilient0, +wifi0_rfsilient1, wifi0_uart, wifi0_uart0, wifi0_uart1, wifi0_wci, +wifi10, wifi11, wifi12, wifi13, wifi14, wifi134, wifi1_cal, wifi1_rfsilient0, +wifi1_rfsilient1, wifi1_uart, wifi1_uart0, wifi1_uart1, wifi1_wci, +wifi_wci0, wifi_wci1 Example:
This patch adds the remaining pin functions and mux groups. It also fixes a typo in the existing binding document. Cc: Varadarajan Narayanan <varada@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Ram Chandra Jangir <rjangir@codeaurora.org> Cc: John Crispin <john@phrozen.org> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> --- --- .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt | 36 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-)