| Message ID | 1494514306-4167-8-git-send-email-siddhesh@sourceware.org |
|---|---|
| State | New |
| Headers | show |
On 11/05/2017 11:51, Siddhesh Poyarekar wrote: > Now that LD_HWCAP_MASK (or glibc.tune.hwcap_mask) is read early enough > to influence cpu feature check in aarch64, use it to influence > multiarch selection. Setting LD_HWCAP_MASK such that it clears > HWCAP_CPUID will now disable multiarch for the binary. > > * sysdeps/unix/sysv/linux/aarch64/cpu-features.c > (init_cpu_features): Use glibc.tune.hwcap_mask. LGTM. > > Change-Id: Ia801ed6b8166b79a0cae184ee7417272f2f60593 > --- > sysdeps/unix/sysv/linux/aarch64/cpu-features.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > index 7025062..0478fcc 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c > @@ -18,18 +18,25 @@ > > #include <cpu-features.h> > #include <sys/auxv.h> > +#include <elf/dl-tunables.h> > > static inline void > init_cpu_features (struct cpu_features *cpu_features) > { > - if (GLRO(dl_hwcap) & HWCAP_CPUID) > +#if HAVE_TUNABLES > + uint64_t hwcap_mask = TUNABLE_GET (glibc, tune, hwcap_mask, uint64_t); > +#else > + uint64_t hwcap_mask = GLRO (dl_hwcap_mask); > +#endif I noted the hwcap_mask get logic is duplicated over various places. Should we define a helper macro for it? > + > + uint64_t hwcap = GLRO (dl_hwcap) & hwcap_mask; > + > + if (hwcap & HWCAP_CPUID) > { > register uint64_t id = 0; > asm volatile ("mrs %0, midr_el1" : "=r"(id)); > cpu_features->midr_el1 = id; > } > else > - { > - cpu_features->midr_el1 = 0; > - } > + cpu_features->midr_el1 = 0; > } >
On Thursday 18 May 2017 12:52 AM, Adhemerval Zanella wrote: > I noted the hwcap_mask get logic is duplicated over various places. Should we > define a helper macro for it? Sorry I missed this suggestion, I have posted a patch for it now that applies on top of my patchset. https://sourceware.org/ml/libc-alpha/2017-05/msg00578.html Siddhesh
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index 7025062..0478fcc 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -18,18 +18,25 @@ #include <cpu-features.h> #include <sys/auxv.h> +#include <elf/dl-tunables.h> static inline void init_cpu_features (struct cpu_features *cpu_features) { - if (GLRO(dl_hwcap) & HWCAP_CPUID) +#if HAVE_TUNABLES + uint64_t hwcap_mask = TUNABLE_GET (glibc, tune, hwcap_mask, uint64_t); +#else + uint64_t hwcap_mask = GLRO (dl_hwcap_mask); +#endif + + uint64_t hwcap = GLRO (dl_hwcap) & hwcap_mask; + + if (hwcap & HWCAP_CPUID) { register uint64_t id = 0; asm volatile ("mrs %0, midr_el1" : "=r"(id)); cpu_features->midr_el1 = id; } else - { - cpu_features->midr_el1 = 0; - } + cpu_features->midr_el1 = 0; }