diff mbox

0001-Basic-support-for-Core-i7

Message ID 4CBD805D.6000208@codesourcery.com
State New
Headers show

Commit Message

Maxim Kuvyrkov Oct. 19, 2010, 11:26 a.m. UTC 
This patch adds handling of "corei7" to -mtune= and -march= options. 
Tuning for -mtune=corei7 is set to that of -mtune=generic or 
-mtune=generic64 depending on the selected ABI.

Tested by bootstrapping on i686-pc-linux-gnu.

OK to commit?

Thank you,

Comments

H.J. Lu Oct. 19, 2010, 11:31 a.m. UTC | #1 
On Tue, Oct 19, 2010 at 4:26 AM, Maxim Kuvyrkov <maxim@codesourcery.com> wrote:
> This patch adds handling of "corei7" to -mtune= and -march= options. Tuning
> for -mtune=corei7 is set to that of -mtune=generic or -mtune=generic64
> depending on the selected ABI.
>
> Tested by bootstrapping on i686-pc-linux-gnu.
>
> OK to commit?
>

I suggest you use

if (TARGET_64BIT)
  {
  }
else
   switch (ix86_tune)
     {
     case  PROCESSOR_GENERIC64:
	  ix86_tune = PROCESSOR_GENERIC32;
          ix86_schedule = CPU_PENTIUMPRO;
          break;
    default:
         break;
   }

since you may add more cases.
Andi Kleen Oct. 19, 2010, 1:16 p.m. UTC | #2 
Maxim Kuvyrkov <maxim@codesourcery.com> writes:

> This patch adds handling of "corei7" to -mtune= and -march=
> options. Tuning for -mtune=corei7 is set to that of -mtune=generic or
> -mtune=generic64 depending on the selected ABI.
>
> Tested by bootstrapping on i686-pc-linux-gnu.
>
> OK to commit?

The problem I have with "corei7" is that it is an Nehalem tuning
target, but there are more corei7s than just Nehalems
(and also there are Nehalems which are not called core i7)

Particularly in gcc a CPU comes with a cache size,
but there is already a wide range of cache sizes in CPUs
called corei7.

We had a similar problem in other projects, where naming something
corei7 that identifies a special CPU was a pain later, when there were
different micro architectures with the same names.

Intel manuals often avoid this problem by also adding
the process like, "corei7-45nm" (and there's also
a corei7-32nm which has many similarities but not all)

You also probably want an alias from "xeon55xx" 

-andi
H.J. Lu Oct. 19, 2010, 1:24 p.m. UTC | #3 
On Tue, Oct 19, 2010 at 6:16 AM, Andi Kleen <andi@firstfloor.org> wrote:
> Maxim Kuvyrkov <maxim@codesourcery.com> writes:
>
>> This patch adds handling of "corei7" to -mtune= and -march=
>> options. Tuning for -mtune=corei7 is set to that of -mtune=generic or
>> -mtune=generic64 depending on the selected ABI.
>>
>> Tested by bootstrapping on i686-pc-linux-gnu.
>>
>> OK to commit?
>
> The problem I have with "corei7" is that it is an Nehalem tuning
> target, but there are more corei7s than just Nehalems
> (and also there are Nehalems which are not called core i7)
>
> Particularly in gcc a CPU comes with a cache size,
> but there is already a wide range of cache sizes in CPUs
> called corei7.
>
> We had a similar problem in other projects, where naming something
> corei7 that identifies a special CPU was a pain later, when there were
> different micro architectures with the same names.
>
> Intel manuals often avoid this problem by also adding
> the process like, "corei7-45nm" (and there's also
> a corei7-32nm which has many similarities but not all)
>
> You also probably want an alias from "xeon55xx"
>

I don't think we need cover all models unless they
require different tuning. Otherwise, it will be too
confusing. For the current Core i3/5/7/Xeon,
-mtune=corei7 sounds good to me. For native, you
can use -march=native.  Otherwise, you can use
-march=corei7 -maes, ...
diff mbox

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 33510a7..d04c20e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2894,6 +2894,9 @@  ix86_option_override_internal (bool main_args_p)
       {"core2", PROCESSOR_CORE2, CPU_CORE2,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16},
+      {"corei7", PROCESSOR_GENERIC64, CPU_GENERIC64,
+       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16},
       {"atom", PROCESSOR_ATOM, CPU_ATOM,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
@@ -3233,23 +3236,31 @@  ix86_option_override_internal (bool main_args_p)
       {
 	ix86_schedule = processor_alias_table[i].schedule;
 	ix86_tune = processor_alias_table[i].processor;
-	if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
+	if (TARGET_64BIT)
 	  {
-	    if (ix86_tune_defaulted)
+	    if (!(processor_alias_table[i].flags & PTA_64BIT))
 	      {
-		ix86_tune_string = "x86-64";
-		for (i = 0; i < pta_size; i++)
-		  if (! strcmp (ix86_tune_string,
-				processor_alias_table[i].name))
-		    break;
-		ix86_schedule = processor_alias_table[i].schedule;
-		ix86_tune = processor_alias_table[i].processor;
+		if (ix86_tune_defaulted)
+		  {
+		    ix86_tune_string = "x86-64";
+		    for (i = 0; i < pta_size; i++)
+		      if (! strcmp (ix86_tune_string,
+				    processor_alias_table[i].name))
+			break;
+		    ix86_schedule = processor_alias_table[i].schedule;
+		    ix86_tune = processor_alias_table[i].processor;
+		  }
+		else
+		  error ("CPU you selected does not support x86-64 "
+			 "instruction set");
 	      }
-	    else
-	      error ("CPU you selected does not support x86-64 "
-		     "instruction set");
 	  }
-        /* Intel CPUs have always interpreted SSE prefetch instructions as
+	else if (ix86_tune == PROCESSOR_GENERIC64)
+	  {
+	    ix86_tune = PROCESSOR_GENERIC32;
+	    ix86_schedule = CPU_PENTIUMPRO;
+	  }
+	/* Intel CPUs have always interpreted SSE prefetch instructions as
 	   NOPs; so, we can enable SSE prefetch instructions even when
 	   -mtune (rather than -march) points us to a processor that has them.
 	   However, the VIA C3 gives a SIGILL, so we only do that for i686 and