| Message ID | 20170217173738.13414-1-svaidy@linux.vnet.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
On 02/17/2017 11:07 PM, Vaidyanathan Srinivasan wrote: > + prlog(PR_NOTICE, "SLW: Enabling: %s\n", states[i].name); > + Sorry I picked this up from Mikey's patch https://lists.ozlabs.org/pipermail/skiboot/2017-February/006403.html
On Fri, 2017-02-17 at 23:07 +0530, Vaidyanathan Srinivasan wrote: > From: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> > > POWER9 DD1 chip can work with lite stop states now. These > STOP states have ESL=EC=0 and provide fast entry/exit. > > Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> > Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> > --- > hw/slw.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/hw/slw.c b/hw/slw.c > index 81e4e4a..2415019 100644 > --- a/hw/slw.c > +++ b/hw/slw.c > @@ -649,6 +649,8 @@ void add_cpu_idle_state_properties(void) > u32 *residency_ns_buf; > u32 *flags_buf; > > + bool only_lite = false; > + > prlog(PR_DEBUG, "CPU idle state device tree init\n"); > > /* Create /ibm,opal/power-mgt if it doesn't exist already */ > @@ -683,6 +685,9 @@ void add_cpu_idle_state_properties(void) > if (!stop_levels) > prerror("SLW: No stop levels available. Power saving > is disabled!\n"); > > + /* Force only lite states for DD1.0 */ > + if (chip->ec_level == 0x10) > + only_lite = true; > } else if (chip->type == PROC_CHIP_P8_MURANO || > chip->type == PROC_CHIP_P8_VENICE || > chip->type == PROC_CHIP_P8_NAPLES) { > @@ -757,10 +762,15 @@ void add_cpu_idle_state_properties(void) > supported_states_mask |= OPAL_PM_WINKLE_ENABLED; > } > for (i = 0; i < nr_states; i++) { > + u64 esl = states[i].pm_ctrl_reg_val & OPAL_PM_PSSCR_ESL; > + > /* For each state, check if it is one of the supported > states. */ > if (!(states[i].flags & supported_states_mask)) > continue; > > + if (only_lite && esl) > + continue; > + Can we just check the ec_level here and eliminate the only_lite variable? Mikey > /* We can only use the stop levels that HB has made available > */ > if (has_stop_inst) { > u32 level = 31 - (states[i].pm_ctrl_reg_val & > @@ -770,6 +780,8 @@ void add_cpu_idle_state_properties(void) > continue; > } > > + prlog(PR_NOTICE, "SLW: Enabling: %s\n", states[i].name); > + > /* > * If a state is supported add each of its property > * to its corresponding property buffer.
diff --git a/hw/slw.c b/hw/slw.c index 81e4e4a..2415019 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -649,6 +649,8 @@ void add_cpu_idle_state_properties(void) u32 *residency_ns_buf; u32 *flags_buf; + bool only_lite = false; + prlog(PR_DEBUG, "CPU idle state device tree init\n"); /* Create /ibm,opal/power-mgt if it doesn't exist already */ @@ -683,6 +685,9 @@ void add_cpu_idle_state_properties(void) if (!stop_levels) prerror("SLW: No stop levels available. Power saving is disabled!\n"); + /* Force only lite states for DD1.0 */ + if (chip->ec_level == 0x10) + only_lite = true; } else if (chip->type == PROC_CHIP_P8_MURANO || chip->type == PROC_CHIP_P8_VENICE || chip->type == PROC_CHIP_P8_NAPLES) { @@ -757,10 +762,15 @@ void add_cpu_idle_state_properties(void) supported_states_mask |= OPAL_PM_WINKLE_ENABLED; } for (i = 0; i < nr_states; i++) { + u64 esl = states[i].pm_ctrl_reg_val & OPAL_PM_PSSCR_ESL; + /* For each state, check if it is one of the supported states. */ if (!(states[i].flags & supported_states_mask)) continue; + if (only_lite && esl) + continue; + /* We can only use the stop levels that HB has made available */ if (has_stop_inst) { u32 level = 31 - (states[i].pm_ctrl_reg_val & @@ -770,6 +780,8 @@ void add_cpu_idle_state_properties(void) continue; } + prlog(PR_NOTICE, "SLW: Enabling: %s\n", states[i].name); + /* * If a state is supported add each of its property * to its corresponding property buffer.