| Message ID | 20170127232307.110483-1-xow@google.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
I still don't follow. Is this changing it to drop bytes until the host powers on? Is this change making it so the device won't open? On Fri, Jan 27, 2017 at 3:23 PM, Xo Wang <xow@google.com> wrote: > Currently, UART1 on Zaius BMC is unusable until brought out of reset by > powering the host on. In this reset state, ttyS0 can still be opened > and UART1 silently drops bytes, which is not obviously expected > behavior. > > Clear the LPC block control bit that enables LPCRST# as a reset source > for UART1. > > Signed-off-by: Xo Wang <xow@google.com > --- > arch/arm/mach-aspeed/aspeed.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c > index 4bd3680d742d..fa99d8bde5e0 100644 > --- a/arch/arm/mach-aspeed/aspeed.c > +++ b/arch/arm/mach-aspeed/aspeed.c > @@ -185,6 +185,13 @@ static void __init do_zaius_setup(void) > > /* Set SPI1 CE0 decoding window to 0x30000000 */ > writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); > + > + /* Disable LPC reset for UART1, otherwise held in reset by LPCRST#, > + * silently dropping bytes until released (usually by host power > on) > + * */ > + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); > + /* Clear "Enable UART1 reset source from LPC" */ > + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); > } > > static void __init do_witherspoon_setup(void) > -- > 2.11.0.483.g087da7b7c-goog > > _______________________________________________ > openbmc mailing list > openbmc@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/openbmc >
On Fri, 2017-01-27 at 15:32 -0800, Rick Altherr wrote: > I still don't follow. Is this changing it to drop bytes until the > host powers on? Is this change making it so the device won't open? I understand it to be the other way around: In the existing configuration UART1 will drop bytes by being held in reset until the host initialises the LPC bus (i.e. releases LPCRST#) during boot. Xo's change reconfigures the SoC so that UART1 reset state doesn't depend on LPCRST# (i.e. the host initialising the LPC bus), so it is immediately useful in that it won't discard bytes. Xo? Andrew > > > On Fri, Jan 27, 2017 at 3:23 PM, Xo Wang <xow@google.com> wrote: > > Currently, UART1 on Zaius BMC is unusable until brought out of reset by > > powering the host on. In this reset state, ttyS0 can still be opened > > and UART1 silently drops bytes, which is not obviously expected > > behavior. > > > > Clear the LPC block control bit that enables LPCRST# as a reset source > > for UART1. > > > > Signed-off-by: Xo Wang <xow@google.com > > --- > > arch/arm/mach-aspeed/aspeed.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c > > index 4bd3680d742d..fa99d8bde5e0 100644 > > --- a/arch/arm/mach-aspeed/aspeed.c > > +++ b/arch/arm/mach-aspeed/aspeed.c > > @@ -185,6 +185,13 @@ static void __init do_zaius_setup(void) > > > > /* Set SPI1 CE0 decoding window to 0x30000000 */ > > writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); > > + > > + /* Disable LPC reset for UART1, otherwise held in reset by LPCRST#, > > + * silently dropping bytes until released (usually by host power on) > > + * */ > > + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); > > + /* Clear "Enable UART1 reset source from LPC" */ > > + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); > > } > > > > static void __init do_witherspoon_setup(void) > > -- > > 2.11.0.483.g087da7b7c-goog > > > > _______________________________________________ > > openbmc mailing list > > openbmc@lists.ozlabs.org > > https://lists.ozlabs.org/listinfo/openbmc > > > > _______________________________________________ > openbmc mailing list > openbmc@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/openbmc
On Sat, Jan 28, 2017 at 12:00 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > On Fri, 2017-01-27 at 15:32 -0800, Rick Altherr wrote: >> I still don't follow. Is this changing it to drop bytes until the >> host powers on? Is this change making it so the device won't open? > > I understand it to be the other way around: > > In the existing configuration UART1 will drop bytes by being held in > reset until the host initialises the LPC bus (i.e. releases LPCRST#) > during boot. > > Xo's change reconfigures the SoC so that UART1 reset state doesn't > depend on LPCRST# (i.e. the host initialising the LPC bus), so it is > immediately useful in that it won't discard bytes. > > Xo? Yes, what Andrew said. It releases UART1 from being controlled by LPC reset, so that it's available regardless of the host being up. cheers xo
OK. I didn't get that from the commit message or comments as written. On Tue, Jan 31, 2017 at 2:23 PM, Xo Wang via openbmc < openbmc@lists.ozlabs.org> wrote: > On Sat, Jan 28, 2017 at 12:00 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > > On Fri, 2017-01-27 at 15:32 -0800, Rick Altherr wrote: > >> I still don't follow. Is this changing it to drop bytes until the > >> host powers on? Is this change making it so the device won't open? > > > > I understand it to be the other way around: > > > > In the existing configuration UART1 will drop bytes by being held in > > reset until the host initialises the LPC bus (i.e. releases LPCRST#) > > during boot. > > > > Xo's change reconfigures the SoC so that UART1 reset state doesn't > > depend on LPCRST# (i.e. the host initialising the LPC bus), so it is > > immediately useful in that it won't discard bytes. > > > > Xo? > > Yes, what Andrew said. It releases UART1 from being controlled by LPC > reset, so that it's available regardless of the host being up. > > cheers > xo > _______________________________________________ > openbmc mailing list > openbmc@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/openbmc >
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c index 4bd3680d742d..fa99d8bde5e0 100644 --- a/arch/arm/mach-aspeed/aspeed.c +++ b/arch/arm/mach-aspeed/aspeed.c @@ -185,6 +185,13 @@ static void __init do_zaius_setup(void) /* Set SPI1 CE0 decoding window to 0x30000000 */ writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); + + /* Disable LPC reset for UART1, otherwise held in reset by LPCRST#, + * silently dropping bytes until released (usually by host power on) + * */ + reg = readl(AST_IO(AST_BASE_LPC | 0x98)); + /* Clear "Enable UART1 reset source from LPC" */ + writel(reg & ~BIT(4), AST_IO(AST_BASE_LPC | 0x98)); } static void __init do_witherspoon_setup(void)
Currently, UART1 on Zaius BMC is unusable until brought out of reset by powering the host on. In this reset state, ttyS0 can still be opened and UART1 silently drops bytes, which is not obviously expected behavior. Clear the LPC block control bit that enables LPCRST# as a reset source for UART1. Signed-off-by: Xo Wang <xow@google.com --- arch/arm/mach-aspeed/aspeed.c | 7 +++++++ 1 file changed, 7 insertions(+)